IEEE ELECTRON DEVICE LETTERS, VOL. 27, NO.
5, MAY 2006
MOSFET Design for Forward Body Biasing Scheme
Akira Hokazono, Member, IEEE, Sriram Balasubramanian, Student Member, IEEE,
Kazunari Ishimaru, Member, IEEE, Hidemi Ishiuchi, Member, IEEE,
Tsu-Jae King Liu, Senior Member, IEEE, and Chenming Hu, Fellow, IEEE
Abstract—Forward body biasing is a solution for continued
scaling of bulk-Si CMOS technology. In this letter, the depen-
dence of 30-nm-gate MOSFET performance on body bias is ex-
perimentally evaluated for devices with various channel-doping
profiles to provide guidance for channel engineering in a forward
body-biasing scheme. Furthermore, simulations of 10-nm-gate
CMOS (hp22-nm node) devices are performed to study the optimal
channel-doping profile and gate work function engineering for a
forward biasing scheme.
Index Terms—Body bias, forward bias, MOSFET, reverse bias,
substrate bias, work function.
I. I NTRODUCTION
S UBTHRESHOLD leakage control by body biasing [1]–[3]
to adjust the threshold voltage (VTH ) has been proposed
to avoid large static power dissipation and optimize system
performance. There are two options for body bias (VSUB ):
reverse bias (VR ) to increase VTH and reduce leakage power
[4], [5] and forward bias (VF ) to decrease VTH and increase
device performance. The application of a forward body bias
improves VTH rolloff behavior and enables the use of shorter
gates, as can be explained by a quasi-two-dimensional (2-D)
model [6]. A reverse body bias has the opposite effect and also
enhances the band-to-band tunneling current, resulting in IOFF
increase. Therefore, a forward body-biasing scheme is prefer-
able in some important aspects for extending bulk-Si CMOS
technology scaling. In previous studies, VF and VR were sepa-
rately applied to the same device and the resultant performance
characteristics were compared. This method is incorrect, how-
ever, because of the vastly different values of VTH .
In this letter, the two body-bias options are systemati-
cally compared utilizing devices with different VTH0 (VTH at
VSUB = 0 V): For one set of devices, VTH0 is high and VF is
applied to lower VTH ; for the other set of devices, VTH0 is low
and VR is applied to raise VTH . The devices with VF applied
are evaluated against the devices with VR applied, at the same
VTH . MOSFET design optimization (channel dopant profile
Manuscript received October 19, 2005; revised February 28, 2006. The
review of this letter was arranged by Editor M. Ostling.
A. Hokazono is with the Department of Electrical Engineering and Computer
Sciences, University of California at Berkeley, Berkeley, CA 94720-1770 USA
and also with the SoC Research and Development Center, Toshiba Corpora-
tion Semiconductor Company, Isogo-ku, Yokohama 35-8522, Japan (e-mail:
akira.hokazono@toshiba.co.jp).
S. Balasubramanian, T.-J. K. Liu, and C. Hu are with the Department of
Electrical Engineering and Computer Sciences, University of California at
Berkeley, Berkeley, CA 94720-1770 USA.
K. Ishimaru and H. Ishiuchi are with the SoC Research and Development
Center, Toshiba Corporation Semiconductor Company, Yokohama 35-8522,
Japan.
Digital Object Identifier 10.1109/LED.2006.873382
0741-3106/$20.00 © 2006 IEEE
387
engineering and gate work-function engineering) to enhance
device performance for a forward body biasing strategy is
discussed for the first time.
II. D EVICE F ABRICATION AND S IMULATION
CMOSFETs fabricated using hp45-nm-node technology
with various vertical channel-doping profiles were used in this
letter. Retrograde channel profiles were formed by implan-
tation of indium for nMOS and arsenic for pMOS. Uniform
channel profiles were formed by implantation of boron for
nMOS and phosphorus for pMOS. The gate dielectric [1.1-nm
equivalent oxide thickness (EOT)] was formed by an oxynitri-
dation process. Following the formation of poly-Si gate elec-
trodes, offset spacers were formed beside the gate electrodes.
Next, source/drain-extension ion implantation was applied. Af-
ter the formation of gate sidewall spacers (45-nm wide), the
source/drain contact junctions were formed by high-dose ion
implantation and spike annealing. Front-end processing was
completed with a nickel salicide process followed by low-
thermal-budget premetal dielectric (PMD) deposition.
The dependence of CMOSFET performance characteristics
on substrate bias was experimentally measured. From these
results, the optimal channel-doping profile for a forward body-
biasing scheme can be deduced. In order to study the per-
formance of hp22-nm-node bulk-Si CMOSFETs (10-nm gate
length), 2-D device simulations were then performed using
Taurus-Device (Synopsys, Inc.) with drift-diffusion transport
and the density gradient model to capture quantum–mechanical
effects. Channel-profile engineering and gate work-function
engineering for a forward body-biasing scheme were proposed
in this letter.
III. R ESULTS AND D ISCUSSION
A. Channel-Profile Engineering for
Forward Body-Biasing Scheme
The ION −IOFF tradeoff was studied for two sets of samples
(Fig. 1); the desired VTH (IOFF ) is achieved with VF for one
set and with VR for the other. For nMOS [Fig. 1(a)] and pMOS
[Fig. 1(b)] devices with a broad vertical channel-doping profile
(boron- or phosphorus-doped channels, respectively), the VF
device shows lower ION than the VR device does. This is due
to the higher surface doping concentration (to achieve higher
VTH0 ), which degrades carrier mobility in the VF device. For
nMOS [Fig. 1(c)] and pMOS [Fig. 1(d)] devices with steep
retrograde channel doping (indium- or arsenic-doped channels,
respectively), the mobility degradation is less severe, so that
388 IEEE ELECTRON DEVICE LETTERS, VOL. 27, NO. 5, MAY 2006

Fig. 1. Measured ION −IOFF characteristics for various channel-doping

conditions and various body-biasing conditions. (a) nMOS with a broad
channel-doping profile (boron-doped channel). (b) pMOS with a broad channel-
doping profile (phosphorus-doped channel). (c) nMOS with a retrograde
channel (indium-doped channel). (d) pMOS with a retrograde channel (arsenic-
doped channel). Devices subjected to VF have high native threshold voltage
VTH0 . Devices subjected to VR have low VTH0 .

VF yields ION comparable to VR . This indicates that a steep

retrograde channel-doping profile is more important for achiev-
ing higher performance in a VF device than a VR device. From
Fig. 1, it can be seen that VTH is more sensitive to VSUB for a
device designed for VF operation than a device designed for VR
operation. This is an important advantage of the forward body-
biasing strategy because the range of VSUB will become more
limited as technology advances [3].
The experimentally observed dependence of transistor per-
formance on the vertical channel-doping profile is also seen
from simulation results for 10-nm LG MOSFETs with various
channel-doping profiles (Fig. 2). In this figure, the devices with
reverse-bias VSUB have low |VTH0 |, and |VTH | is increased to
0.05 V by applying VR . The devices without any substrate bias
have |VTH0 | = 0.05 V set by channel doping; the devices with
forward-bias VSUB have high |VTH0 |, and |VTH | is decreased to
0.05 V by applying VF . The transition rate of ION (∆ION ) is
defined as
ION at each condition
∆ION = 100 ∗ − 100
ION (retrograde channel, w/o VSUB )
(1)
where “∆ION ” is the percentage improvement in ION as com-
pared to that of the device with retrograde channel doping and
VSUB = 0 V. The simulations confirm that even at a 10-nm gate
length, a steep channel-doping profile is particularly favorable
for a VF device; therefore, a stepped or delta-doped channel
Fig. 2. Simulated performance of 10-nm-gate-length MOSFET versus body
bias, for various channel profiles. (a) nMOS. (b) pMOS. The performance is
evaluated at the same VTH . Reverse-biased device: low VTH0 (low channel
doping); VR applied to set VTH . Without body bias device: VTH0 = VTH with
VSUB = 0 V. Forward-biased device: high VTH0 (high channel doping); VF
applied to set VTH .
is desirable for a forward body-biasing scheme. Furthermore,
the better VTH rolloff makes well forward bias an attractive
option (Fig. 3). As the gate length (LG ) of a bulk-Si MOSFET
is scaled down, the channel dopant concentration should be
increased to reduce the channel depletion width (XDEP ). A
forward body bias (VF ) also makes XDEP smaller, hence VF
improves the scalability of the MOSFET.
The advantage of MOSFET performance cannot been seen
in Fig. 2 due to VTH0 adjustment by channel engineering.
Therefore, the adjustment of VTH0 via gate work-function
engineering is proposed to show the advantage of performance
improvement by the forward body-biasing scheme.
B. Gate Work-Function Engineering for
Forward Body-Biasing Scheme
The adjustment of VTH0 via gate work-function engineering
(possible with metallic gate materials) versus channel doping is
HOKAZONO et al.: MOSFET DESIGN FOR FORWARD BODY BIASING SCHEME
Fig. 3. Comparison of simulated VTH rolloff behavior for various device
designs and body biasing to achieve |VTH | = 0.05 V for LG = 10 nm.
Fig. 4. Comparison of VTH0 adjustment by channel engineering versus gate
work-function engineering for 10-nm-gate-length MOSFET (simulation result).
(a) nMOS; (b) pMOS.
compared in Fig. 4. A steep retrograde channel-doping profile
was used for these simulations. For an nMOS device, a higher
|VTH0 | for a forward biasing scheme is achieved by increasing
the gate work function, whereas a lower |VTH0 | for a reverse-
biasing-scheme device is achieved by decreasing the gate work
function. For a pMOS device, the required changes in gate work
function are just the opposite of those for an nMOS device.
Taking into consideration that the range of gate work function
between VF and VR is 60 meV for nMOS and 50 meV for
pMOS, precise gate work-function control is necessary. By
389
adjusting VTH0 via gate work-function engineering, carrier-
mobility degradation is avoided so that the device designed for
a forward body-biasing scheme shows higher performance than
the device designed for a reverse body-biasing scheme. The
mobility improvement is due to a reduction in the transverse
electric field. In [7], Assaderaghi et al. noted that decreased
transverse field improves electron and hole drift velocity for
a fixed lateral electric field, due to reduced surface roughness
scattering. Moreover, the increase in linear peak transconduc-
tance with the forward body bias was experimentally con-
firmed. Since VF also improves short-channel behavior, then
it will yield an improved ION −IOFF tradeoff. Gate work-
function tunability is therefore desirable for transistor design
optimization for a forward body-biasing scheme.
It should be noted that a practical upper limit for |VF | is 0.6 V,
in consideration of well current and latch-up considerations.
IV. C ONCLUSION
The impact of body biasing on MOSFET performance is
studied for various channel-doping profiles, for gate lengths
down to 10 nm. Forward body biasing improves short-channel
behavior, and therefore offers a solution for extending the scal-
ing limit of bulk-Si MOSFETs. It should be seriously consid-
ered as the preferred strategy over reverse body biasing. Steep
retrograde channel doping and gate work-function engineering
over an ∼ 60-meV range are desirable to maximize MOSFET
performance under a forward body-bias operation.
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