Input/ Output Organization

Input Output Operations

Basic I/O Operations

There are basically three methods available for data transfer when I/O
devices are considered. They are:
 Program- controlled I/O
 Interrupt I/O and
 Direct Memory Access (DMA) or Hardware controlled I/O.
When I/O devices are to be accessed, they need to be addressed.
There are two ways of doing this as described below.
1) Memory mapped I/O:
In this case, the I/O device is also considered as memory and the memory
addresses are used to refer to the buffers and registers of the device. The total
address space of the computer is divided between memory and I/O device. Data
transfer takes place through the use of normal instructions like Move, Load etc.,
and no special instructions are needed to access the contents of the device buffer
registers.
2) I/O mapped I/O or Standard I/O:
In this case, the input/output devices are considered as separate entities.
So, we have separate memory space and I/O space. Also special instructions like
IN and OUT are used to access I/O devices. General instructions like MOVE
cannot be used for I/O data transfer.

Accessing I/O Devices

A simple arrangement of connecting I/O devices using a single-bus is own
in Fig below.

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The processor memory and all the I/O devices are connected to Js common
bus. The bus consists of three sets of lines address, data and control lines. Since
there is a common bus, if more than one device is enabled at a time, the data on
the bus will be ambiguous and results in a problem called bus contention. Hence,
to avoid this condition, each I/O device is assigned a unique address. Only the
addressed device is enabled and responds to the commands issued on the control
lines. The processor can request either a read or write operation.
As discussed in the beginning, the type and number of 1/0 devices vary in a
system. As is evident, the physical and electrical characteristics of these devices
are also not compatible with that of the processor. Hence, in order to have an
efficient and organized data transfer, an intermediary is required between the
processor and I/O devices. This is called as an I/O interface. The I/O interface
consists of all the logic required to ensure proper operation by acting as a format
translator. If the designed interface can work on different types of I/O devices, it is
called a general purpose interface. In some cases like to access hard disk in a
system, we need a specialized interface to control and coordinate the data transfer.
They are called special purpose I/O interfaces. Nowadays, the complete interface
circuitry is available as single integrated circuit (IC) chip. For example, Intel has
produced a chip called 8255 PPI (Programmable Peripheral Interface) which can
be used to interface an Analog-to-Digital Converter (ADC) or Digital-to-Analog
Converter (DAC) or a printer to the bus. There are special interface ICs like Intel
8275 CRT controller, 8251 USART (Universal Synchronous Asynchronous
Receiver Transmitter used for serial communication of data over telephone lines)
and so on.
Fig above shows a simple I/O interface to connect an input device to the
bus. The address decoder decodes the address sent on the bus so as to enable the
input device. The data register holds the data being transferred to or from the
processor. The status register contains flags to indicate conditions like buffer full,
buffer empty etc., which are used by the processor to verify the status of the
device.
The speed of operation of the processor and I/O devices differ greatly.
Also, since I/O devices are manually operated in many cases (like pressing a key
on the keyboard), there may not be synchronization between the CPU operations
and I/O operations with reference to CPU clock. To cater to the different needs of
I/O operations, three mechanisms have been developed for interfacing I/O devices.
They are: 1) Program Controlled I/O
2) Interrupt I/O
3) Hardware Controlled I/O or Direct Memory Access (DMA).

Program Controlled I/O

Consider an example of connecting a video terminal to a processor. A video
terminal consists of a keyboard and a display unit.
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Consider Fig below

The complete circuitry for each device is connected to the processor via a bus. The
keyboard needs a buffer register to store the code of the key pressed. Similarly the
display unit is required to store the character sent from the processor. These
registers are called DATAIN and DATAOUT, respectively.
Our task is to read a character from keyboard and display it on the screen.
Input data transfer rate is limited by the typing speed of the user, whereas, the
output data transfer rate is very high, since the computer can send thousands of
characters per second to the output unit. But, the display unit may not be able to
accept characters at that rate. Hence, when I/O devices are connected to the
processor, there will be speed mismatch and mechanisms are needed to
synchronize data transfer between them.
One solution to the problem is to use Program Controlled I/O technique. On the
input side, processor waits for user to key-in a character and its availability in the
buffer register of the keyboard is indicated to the processor using a status flag
called SIN. Then the processor reads the character code. On the output side, the
processor sends the first character to the display unit and waits for a signal. The
display sends the signal that the character has been received using a status flag
called SOUT. Now, the processor can send the next character.
The operation of reading a character from the keyboard and displaying it on the
output screen can now be formally stated as below:
We illustrate the idea using memory mapped I/O instructions.
 Write a program to monitor the status of SIN. When SIN is 1, a valid
character is present in DATAIN register and processor can read this
register. When the character is transferred to the processor register,
say Ri, SIN is automatically cleared to 0. If a second character is
entered, SIN is again set to 1 and the process repeats. Thus, SIN = 0
is the condition when processor waits and when SIN = 1, it can read
the data.
This operation can be written as,
READWAIT Branch to READWAIT if SIN = 0
Input from DATAIN to R1
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 Write a program structure to monitor SOUT flag. If SOUT is 1,

display is ready to receive a character and hence transfer a character
code from the processor register R1 to DATAOUT buffer register of
the output device. This transfer automatically clears SOUT to 0.
When the device is ready to receive another character, it sets SOUT
to 1. Now, the processor can send a second character. In this case
also, processor is in a wait loop when SOUT = 0. This operation can
be written as,
WRITE WAIT Branch to WRITEWAIT if SOUT = 0
Output from R1 to DATAOUT
 The data buffer registers DATAIN and DATAOUT and the
corresponding status flags SIN and SOUT form part of a circuitry
known as device interface.
 The two buffer registers DATAIN and DATAOUT can be accessed
as if they are two memory locations. The status flags SIN and SOUT
are made a part of device status register called STATUS, by
assigning bit position to them as shown:

Using this arrangement, it would be easy to check the status of these flags.
The I/O operation can be written more syntactically as below:
(i) Read (input) operation
RWAIT Testbit #0, STATUS
Branch=0 RWAIT
MoveByte DATAIN, R1

(ii) Write (output) operation

WWAIT Testbit #1, STATUS
Branch=0 WWAIT
MoveByte R1, DATAOUT
The Testbit instruction tests the state of the specified bit in the destination
specified. If the bit tested is equal to 0, then the branch condition is true and a
branch is made to the beginning of the wait loop. When the testbit is 1, data is read
from the input buffer or written into the output buffer.

Interrupts
In Program Controlled I/O technique, the processor initiates the action by
checking the status of the device by entering into a wait loop. During this time, the
processor would have performed other tasks instead of simply waiting for the
device to get ready. Hence, another method was developed wherein the I/O device
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initiates the action instead of the processor. This is done by sending a special
hardware signal to the processor called as interrupt, on the interrupt request line.
The processor can be performing its own task without the need to continuously
check the I/O device. When the device gets ready, it will “alert” the processor by
sending an interrupt signal. Thus, by using interrupts, processor waiting cycles can
be eliminated.
To illustrate the idea of Interrupt I/O, consider a task that requires some
computations and the results to be printed on a printer. Let the program consists of
two routines, COMPUTE and PRINT. COMPUTE produces a set of n lines as
output, to be printed by the PRINT routine.
As per the previous scheme, the COMPUTE routine repeats the actions of sending
one line of text to the printer, waiting for it to get printed by the PRINT routine,
till all the lines are printed. The printer accepts only one line of text at a time.
Hence, the processor spends a considerable amount of time waiting for the printer
to become ready. So, we try to speed up the process by overlapping computing and
printing process. Initially, the COMPUTE routine is executed to produce the first n
lines of output. Then, the PRINT routine is executed to send the first line of text to
the printer. Now, instead of waiting for the line to be printed, PRINT routine is
suspended and execution of the COMPUTE routine is continued. Whenever the
printer becomes ready, it alerts the processor by sending an interrupt request
signal. In response, the processor temporarily suspends the execution of
COMPUTE routine and transfers control to the PRINT routine. The PRINT
routine sends the second line to the printer suspends itself and gives control back
to the COMPUTE routine. This process continues until all n lines have been
printed.
The situation is depicted in Fig shown below showing transfer of control between
the two routines.

Interrupt I/O:
The routine executed in response to an interrupt is called the Interrupt-
Service-Routine (ISR). In our example, PRINT routine is the ISR. Assume that an
interrupt request comes during the execution of instruction i as shown in Fig.
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above. The processor first completes the execution of instruction i. Since, the
processor needs to come back to the COMPUTE routine, the contents of program
counter, PC, pointing to instruction at i + 1 is to be saved. This address is called
Return Address. The return address may be saved on the processor stack or in a
special register used for this purpose.
Then, the processor loads the PC with the address of the first instruction of the
ISR. This address can be hardwired in the processor or can be generated by the
device.
A Return-from-interrupt instruction at the end of ISR, reloads the return address
into PC, causing the execution to resume at instruction i + 1.
Once the interrupt request signal comes from the device, the processor has to
inform the device that its request has been recognized and will be serviced soon.
This is indicated by another hardware control signal on the processor bus called
interrupt-acknowledge signal. This is shown in the schematic of Fig below. After
receiving the interrupt-acknowledge signal, the external device will deactivate the
request signal.

Enabling and Disabling Interrupts

When an interrupt arrives, the processor suspends the execution of one
program and begins the execution of another program requested by an external
device. Since interrupt is an asynchronous event (can happen at any time) it may
alter the sequence of events. Hence facility must be provided to enable and disable
interrupts as desired. This can be done by the processor itself or by the user under
program control.
Consider the case of a single interrupt request from one device. The device keeps
the interrupt request signal activated until it is informed that the processor has
accepted its request. This activated signal, if not deactivated, may lead to
successive interruptions, causing the system to enter into an infinite loop. To
remedy such situations, there are three possibilities:
 The first option is that processor ignores the interrupt request line
until the execution of the first instruction of the TSR has been
completed. By using Interrupt-Disable instruction at the beginning of
TSR, the programmer can ensure that no further interruptions will
occur. At the end of the TSR, an Interrupt-Enable instruction before

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the Return-from-interrupt instruction is used to enable the interrupts

again.
 The second possibility is to have the processor automatically disable
the interrupts before starting the execution of the TSR. Prior to
disabling, the processor should save the contents of PC and the
processor status register (PS) on the stack. The processor status
register has one bit called Interrupt -enable which will enable
interrupts when set to 1. After saving the contents of the PS register
on the stack, the processor clears the Interrupt-enable bit in its PS
register, disabling further interrupts. When a Return-from-interrupt
instruction is executed, the contents of the PS register are restored
from the stack. Hence interrupts are again enabled.
 In the third approach, the processor has a special interrupt request
line for which the interrupt handling circuit responds only. to the
leading edge of the signal. Such art interrupt line is called edge
triggered. In this case, the processor responds only to the edge and
not to the 1eI the interrupt request signal. Thus, there will not be
multiple interruptions because of a single request and hence no need
to explicitly disable interrupt requests from this line.
To summarize, the actions that take place in handling an interrupt request from a
device are sequenced as under. (It is assumed that interrupts are initially enabled.)
1. The device raises an interrupt request.
2. The program currently being executed is interrupted (temporarily
suspended) by the processor.
3. All interrupts are disabled.
4. The device is informed that its request has been granted, and in response,
the device deactivates the interrupt-request signal.
5. Processor Status PS, and Return address are saved on stack.
6. The action requested by the interrupt is performed by the TSR.
7. Interrupts are enabled again and the execution of the interrupted program
is resumed.

Interrupt Hardware
Consider the case where all external devices request for a service over a
common interrupt-request line as shown in Fig below.

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All devices are connected to the line via switches to ground. If all signals INTR1to
INTRn are inactive, (all switches are open), the voltage on the interrupt request
line will be Vdd and hence no interrupt signal is generated. To raise an interrupt
request, a device closes its switch. When a device closes its switch, the voltage on
the line drops to 0, causing INTR signal to go to 1. Hence, the value of INTR is
the logical OR of the requests from individual devices, that is,
INTR = INTR1 + ... + INTRn.
For implementation of the circuit in Fig above, open-collector (open-drain) gates
are used to drive the INTR line. The output of such a gate is equivalent to a switch
to ground that is open when the gate’s input is in the 0 state and closed when it is
in the 1 state. The voltage level at the output of the gate is determined by the data
applied to all the gates connected to the bus. Resistor R is called as pull-up register
because it pulls the line voltage up to the high-voltage state when the switches are
open.
When a request is received over a common interrupt request line as in Fig above
additional information is needed to identify the particular device that activated the
line. This information is available in the status register of the device as shown
below.

When a device raises an interrupt request, it sets one of the bits in its status
register, called IRQ bit. As shown, KIRQ and DIRQ are the interrupt request bits
for keyboard and display. If any of these bits are 1, that particular device has
requested the service. Also, if two or more devices have activated the line at the
same time, then the tie is to be broken and one of them will get the service at a
time.
The simplest way to identify the interrupting device is to have the interrupt-
service-routine (ISR) poll all the I/O devices connected to the bus. The first device
encountered with its IRQ bit set, is the device that should be serviced. After
servicing this device, the next requests may be serviced.
The polling method is simple and easy to implement. Also, it gives a sort of
priority for simultaneously made interrupt requests. The disadvantage is the time
spent n polling the IRQ bits of all devices. So, another approach is used to solve
this problem.
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Interrupt Nesting and Priority Structures

Here, we can have two possibilities:
a) Multiple requests coming over a single interrupt-request line.
b) Multiple requests over multiple interrupt-request lines.
The first problem is as shown below.

One way to assign priority is to use software polling approach. Let us assume that
each device has an interrupt request (IR) flip-flop which will be set to 1 if the
device wants to make a request. All these interrupt request flip-flops are grouped
together into an interrupt-request status register where each bit corresponds to one
device request as shown below.

In the software polling approach, we can use logical shift instructions to check
each bit. If we use right shift instruction, device 1 gets highest priority,
whereas, for a shift left instruction, device m gets highest priority.
The polling is done at regular intervals under program control. When the processor
is executing the interrupt-service-routine of a device, and it finds that a higher
priority device is requesting service, the current interrupt service routine is
suspended and the program control is transferred to the interrupt service routine of
the higher priority device. The software polling method is flexible, but efficiency
of the processor is reduced, since it may result in a long delay in responding to an
interrupt request.
For case (b), the implementation is based on hardware organization. To implement
this scheme, we can assign a priority level to the processor that can be changed.
The priority level of the processor is the priority of the program that is currently
being executed. The processor accepts interrupts only from devices that have
priorities higher than its own. This action disables interrupts from devices at the
same level or lower level of priority.
The processor’s priority is usually encoded in few bits of the processor status word
(PSW). It can be changed by program instructions called privileged instructions,
which write into the processor status word. These instructions can r e executed
only when the processor is running in supervisor mode, that is, while executing the
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operating system routines. The processor switches to the user mode before
beginning to execute application programs. This will guarantee that a user
program cannot change the priority of the processor deliberately or accidentally.
A multiple priority scheme using hardware logic can be easily implemented by
using separate interrupt-request and interrupt-acknowledge lines for each device.
This is shown in Fig. below. The processor has a priority arbitration circuit, which
assigns a different priority level to the devices. The arbiter (or priority resolver)
gets requests on different lines, evaluates them and issues an acknowledge signal
to the highest priority device amongst the currently requesting devices. Later, a
request is accepted only if it has a higher priority level than that currently assigned
to the processor.

Fig G
A simplest possible priority arbiter may consist of a single priority encoder.
Suppose, we have 8 devices, then we can use a 8-to-3 priority encoder to encode
the priority as a 3-bit binary number from 000 to 111.

Simultaneous Requests
When multiple requests are received over a single interrupt request line at the
same time, polling the status request is a straightforward but time consuming
method. So, another method called as daisy-chain is a commonly used hardware
arrangement for handling many requests over a single interrupt request line. The
structure is shown in Fig. below. The interrupt-request line, (INTR)’ is common to
all devices The interrupt-acknowledge line, INTA is connected in a daisy-chain
fashion. The INTA signal propagates serially through the devices.
When several devices raise an interrupt request and (INTR)’ line is activated
the processor responds by setting the INTA line to 1. This signal is received by
device 1. If device 1 has requested the interrupt, it blocks the INTA signal and
sends its identifying interrupt vector on the data bus. If device 1 has not requested
the service, it passes the INTA signal to device 2 and so on. Hence, in the daisy-
chain arrangement, the device that is etricl1y closer to the processor

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as the highest priority. This arrangement requires fewer wires than that required in
the Fig. G.

The two schemes discussed can be combined to produce a general structure, which
is shown in Fig(b).

Devices are organized into groups and each group connected at a different priority
level. Within a group, devices are connected in daisy-chain.
Computer systems use specialized interface circuitry to handle multiple interrupt
requests from the devices. For example, Intel has developed an interface called
Programmable Interrupt Controller 8259 (PIC) which can handle up to 8 interrupt
requests at a time. Also, by cascading such PICs, more number of requests can be
handled.

Controlling Device Requests

When several devices are in the system, we need a mechanism in the interface
circuits of individual devices to control whether a device is allowed to generate an
interrupt request.
The control is usually provided in the form of an interrupt-enable bit in the
device’s interface circuit in a register called CONTROL register.

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The keyboard interrupt enable KEN and display interrupt enable DEN bits of the
CONTROL register are used for controlling. If either of these flags is set, the
interface circuit generates an interrupt request whenever the corresponding status
flag in register STATUS is set.

At the same time, the interrupt circuit sets bit KIRQ or DIRQ to indicate that the
keyboard or display unit is requesting an interrupt. If an interrupt enable bit is
equal to 0, the interface circuit will not generate an interrupt request, regardless of
the state of the status flag.
Thus, at the device end, a terrupt-enab1e bit in a control register determines
whether the device is allowed to generate an interrupt request. At the processor
end, either an interrupt-enable bit in the processor status (PS) word register or a
priority structure determine whether a given interrupt request will be accepted.

Exceptions
The term ‘exception’ is used to refer to any event that causes an
interruption. (I/O interrupts are one example of an exception). An interrupt is any
event that causes the execution of one program to be suspended and of another
program to begin.
In a computer system, large number of I/O operations like data transfer,
operations, file handling and so on are handled using interrupt technique.
The operating system performs these operations on behalf of application programs
written by user. Thus, an interrupt need not always be caused by an external
device.
Intel literature uses the term ‘exception’ to refer to any internal condition caused
due to software or hardware. For example, as discussed earlier, processor will
have privileged instructions to be run in the supervisor mod. An attempt to execute
a privileged instruction in the user mode causes an interrupt called privilege
exception.
Generally, exceptions occur when some invalid operation or malfunction of the
system happens. The interrupt-service-routines written for these cases are used to
protect the computer system as well as to inform the user about the problem. For
example, when a divide-by-zero operation happens, the operating system raises an
exception and prompts the user about this malfunction. We now consider a few
kinds of exceptions.

Recovery and Errors:

A variety of techniques are available to ensure that all hardware
components are operating properly. Many computers include an error-checking-
code in the main memory. If an error occurs, the control hardware detects it and
informs the processor by raising an interrupt.

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A program may be interrupted if the processor detects an error or an

unusual condition while executing the instructions of this program. For example,
the OP-code field of an instruction may not correspond to any legal instruction or
an arithmetic instruction may attempt a division by zero.
When exception processing is initiated as a result of such errors, the
processor suspends the program being executed and starts an exception service
routine. This routine takes appropriate action to recover from the error if possible;
else informs the user about it.

Debugging:
The system software usually includes a program called debugger, which
helps the programmer to find errors in the program. The debugger uses exceptions
to provide two important capabilities: trace mode and breakpoints.
When a processor is operating in trace mode, an exception occurs after
execution of every instruction. This uses the debugging program as the exception
service routine, which enables the user to examine the contents of registers,
memory locations etc. After the processor returns from the debugging program,
the next instruction in the main program is executed and the debugging program is
activated again. During the execution of the debugging program, the trace
exception is disabled.
Break points provide a facility to interrupt the program at specific points
selected by the user. An instruction called Trap or Software interrupt is usually
provided for this purpose. The execution of this instruction causes the same
actions as when a hardware interrupt occurs. While debugging a program, the user
may wish to interrupt program execution after say, instruction i, in the program.
The debugging routine saves instruction i + 1 and replaces it with a software-
interrupt instruction. When the program reaches this point, the debugging routine
is activated. This gives the user a chance to examine contents of register and
memory.
When the user is ready to continue executing his/her program, the debugging
routine restores the instruction that was at location i + 1 and executes a Return-
from-interrupt instruction.
High Level Languages like ‘C’, give options for breakpoints like set break point”
or “clear break point, as well as for trace mode operation. Trace mode operation is
also known as single stepping.

Privilege Exception:
To protect the operating system from being corrupted by user programs,
certain instructions can be executed only when the processor is in the supervisor
(monitor) mode. These instructions are called privileged instructions. When the
processor is running in the user mode, it cannot execute an instruction that changes

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the priority level of the processor or enables a user program to access areas in the
main memory that have been allocated to other users. An attempt to execute such
an instruction will produce a privilege exception. As a result, the processor
switches to the supervisor mode and begins to execute an appropriate routine in
the operating system (OS). The implementation details vary from one OS to
another OS.

Direct Memory Access

We described two techniques of interfacing I/O devices:
Program Controlled I/O where data are transferred by executing
instructions such as Move DATAIN, RO
and Interrupt Controlled I/O, where the processor is informed by the device using
interrupt signals.
In both these approaches, the processor is involved for each transfer.
Hence, in both these schemes, there is a considerable amount of delay involved for
each data transfer. This has been discussed in the previous Sections. So, for large
blocks of data transfer at a fast rate, another approach is used.
Thus, it is better to have a scheme, wherein a large block of data can be
directly transferred between an external device and main memory, without
continuous intervention by the processor. This approach is called Direct Memory
Access or DMA.
DMA transfers are performed by a control circuit that is part of the I/O interface.
The circuit referred to as DMA controller, performs the functions that would be
normally performed by the processor. For each word transferred, provides the
memory address and all the bus signals that control data transfer. Since, it has to
transfer blocks of data, the DMA controller must increment the memory address
for successive words and keep track of the number of transfers.
To initiate the transfer of a block of words, the processor sends the following
information to the DMA controller: the starting address, the number of words in
the block and the direction of the transfer. Upon receiving this information, the
DMA controller proceeds to perform the requested operation. When the entire
block has been transferred, the controller informs the processor by raising an
interrupt signal. While DMA transfer is taking place, the processor can be used to
execute another program.
As mentioned earlier, all I/O operations are always performed by the OS in
response to a request from an application program. For an I/O operation involving
DMA, the OS puts the program that requested the transfer in the blocked state,
initiates DMA operation, and starts the execution of another program. When the
transfer is completed, the DMA controller informs the processor by sending an

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interrupt request. In response, the OS puts the suspended program in the running
state.

DMA Operation:
Fig. below shows an example of registers in a DMA controller that are
accessed by the processor to initiate operations. Two registers are used for storing
the starting address and the word count. The third register contains status and
control flags. The R/W’ bit determine the direction of the transfer. When this bit is
set to 1 by a program instruction, the controller performs a read operation, that is,
it transfers data from memory to I/O device. When R/W’ = 0, DMA controller
performs a write operation, i.e., transfers data from I/O device to memory. When
the controller has completed transferring a block of data and is ready to receive
another command, it sets the ‘Done’ flag to 1. When interrupt-enable (IE) flag is
set to 1, this flag causes the DMA controller to raise an interrupt after it has
completed transferring a block of data. Finally, the controller sets the IRQ bit to 1
when it has requested an interrupt.

Registers in a DMA interface

Fig. below shows how DMA controllers are used in a computer system. A DMA
controller connects a high speed network to the computer bus. The disk controller
which controls two disks also has DMA capability and provides two DMA
channels. It can perform two independent DMA operations.

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Use of DMA controllers in a computer system

To start a DMA transfer of a block of data from main memory to one of the disks,
a routine in the OS writes the following information into the registers of the
corresponding channel of the disk controller:
• Memory address
• Word count
• Function to be performed (Read or Write)
Now, the DMA controller proceeds independently to implement the specified
function. When the DMA transfer is completed, this information is recorded in the
status and control register of the DMA controller by setting the ‘Done’ bit.
Memory accesses by the processor and the DMA controllers are inter- leaved.
Requests by DMA devices for using the bus are always given high priority than
the processor requests. Among different DMA devices, top priority is given to
high-speed peripherals such as a disk, or a network interface.

There are two ways in which the DMA operation can be carried out:
In one method, the DMA controller is given exclusive access to the memory to
transfer a block of data without any interruption. This is known as block or burst
mode DMA transfer. The draw back of this method is that, processor may have to
wait for longer time duration to access memory.
In the second method, the processor originates most memory access cycles The
DMA controller is said to steal memory cycles from the processor. When the
processor is not accessing the main memory, the cycles are taken by the DMA
controller. This method is known as cycle stealing DMA.

Buses

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The primary function of a bus connecting main memory, processor and I/O
devices, is to provide a communication path for the transfer of data. In addition,
the bus includes the lines needed to support interrupts and to implement arbitration
functions. In this Section, we discuss features of bus protocols used for
transferring data. A bus protocol is the set of rules that govern the behavior and
data transmission of various devices connected to the bus. The protocol specifies
parameters such as: asserting control signals, timing of placing the information on
the bus, rate of data transfer and so on. We also describe some details of I/O
interface circuits.
A typical bus consists of three pets of lines: address, data and control lines. The
control signals specify whether a read or a write operation is to be performed.
A single R/W’ line specifies a Read operation when set to 1 and Write operation,
when set to 0. The bus control signals also carry timing information, it specify the
times at which the processor and the I/O devices may place data n the bus or
receive data from the bus.
In any data transfer operation, one device plays the role of a bus master, which
initiates data transfers by issuing Read or Write commands on the bus. The master
is also called as initiator. The device addressed by the master is referred to as slave
or target.
The timing of data transfers over a bus is classified into two types:
 Synchronous.
 Asynchronous.

Synchronous Bus Transfer:

In a synchronous bus, all devices derive timing information from a common
clock line. Equally spaced pulses on this line define equal time intervals. Each of
these intervals constitutes a bus cycle during which one data transfer can place.
This scheme is shown in Fig below. The address lines as shown indicate that some
lines are high and some low, depending on the particular address or data pattern
being transmitted. The crossing points indicate the times at which these pattern
change. A signal line in a high-impedance state is represented by intermediate
level half-way between the low and high signal levels.

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Fig S
Timing of an input transfer on a synchronous bus
Input (Read) Operation:
At time to, the processor places the device address on the address lines and
sends an appropriate command on the control lines to indicate an input operation.
Information gets transmitted over the bus at a speed determined by its physical and
electrical characteristics. The clock pulse width t1 — t0 must be greater than the
maximum propagation delay between the processor and any device connected to
the bus. It also has to be long enough to allow all devices to decode the address
and control signals so that the addressed device (slave) can respond at time t1. The
information on the bus during the period t0 to t1 is unreliable. The slave places the
requested input data on the data lines at time t1. At the end of the clock cycle, at
time t2, the processor (master) strobes (captures) the data on the data lines into its
input buffer. For proper data loading, the period t2 - t1 must be greater than the
maximum propagation time on the bus plus the setup time of the input buffer
register of the processor.

Output (Write) Operation:

The procedure is similar to that of input operation. The processor sends the
address and places the output data on the data lines. It then issues a Write
command signal. At time t1, the addressed device strobes the data lines and loads
the data into its data buffer.
Fig. below shows the actual timings of data transfer. A given signal transition
seen by different devices at different times. Fig. below shows the signal as seen by
the master as well as, as seen by the slave.

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A detailed timing diagram for the input transfer of Fig S

The master sends the address and command signals on the rising edge at
beginning of clock period 1(t0). These signals appear on the bus after a time tAM
due to the delay in the bus driver circuit. At time tAS, the signals reach the slave.
The slave decodes the address and at t1 sends the requested data. The data the bus
until tDS .They travel towards the master and arrive at tDM. At t2, the master loads
the data into its input buffer. Hence the period t2-tDM is the setup time for the
master’s input buffer. The data must be valid after t2 for a period equal to the hold
time of this buffer.
The data transfer scheme just discussed has some limitations. Since a
transfer has to be completed within one clock cycle, the clock period, t2-t0 should
be longer than the longest delays on the bus
From the timing diagram, it is clear that processor has no way of determining
whether the addressed device has actually responded. It assumes that, at t2, the
output data have been received by the I/O device or the input data are available on
the data lines. If the device does not respond, the error will not be detected.
To overcome these limitations, buses must have control signals that represent a
response from the device. These signals inform the master that the slave has
recognized its address and it is ready. The duration of the data transfer period is
also adjusted to suit the needs of the devices. A high-frequency clock is used such
that a complete data transfer cycle would take several clock cycles. This approach
is called Multi-Cycle Transfer.

Multiple-Cycle Transfers:
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The timing diagram of Fig. below shows synchronous bus operation using
multiple-cycle transfer. During clock cycle 1, the master sends address and
command information on the bus, requesting a read operation. The slave receives
this information and decodes it. On the next clock edge, at the beginning of clock
cycle 2, slave begins to access the requested data. The data become ready and are
placed on the bus in clock cycle 3. At the same time, the slave asserts a control
signal called Slave-ready. After receiving this signal, the master strobes the data
into its input buffer at the end of clock cycle 3. The bus transfer is complete and
the master may send a new address to start a new transfer.

An input transfer using multiple clock cycles

The Slave-ready signal is actually an acknowledgement to indicate that valid data
has been sent by the slave. It also allows the duration of a bus transfer to change
from one device to the other. PCI bus standard, to be explained later, uses a similar
approach.
Note: The clock signal on the bus may be different from processor clock.
Asynchronous Bus Transfer:
We now present a different scheme that does not use a clock signal for data
transfer. This method uses handshake signals between the master and the slave for
coordinating data transfers. There are two signals: Master-ready to indicate that
master is ready for a transaction and Slave-ready to indicate that slave is ready to
respond.
The operation proceeds as follows. The master places the address and command
information on the bus. It indicates this to all devices by activating the Master-
ready line. The devices will decode the address. The selected slave performs the
required operation and informs the processor by asserting Slave ready line.
Afterwards, the master removes the Master-ready line and strobes the data into its
input buffer, if it is read operation.

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Fig (I) Timing of an input operation on Asynchronous bus

Fig. above provides the signal information for asynchronous input operation. The
sequences of events are:
t0 →The master places the address and command information on the bus,
and all devices on the bus begin to decode this address.
t1 →The master sets the Master-ready line to 1. The delay t1-t0 is used allow
for any skew (see note) on the bus. To guarantee that the Master- ready signal does
not reach any device ahead of the address and command information, the delay t1-
t0 should be larger than the maximum possible bus skew. This delay also accounts
for the time required by any device to decode the address.
t2 →The selected slave, after decoding the information performs the
required input operation by placing the data from its data register or the data lines.
It also sets the Slave-ready signal to 1. The period t2— t1 depends on the distance
between the master and the slave and on the delays introduced by slave’s interface
circuitry. This is the factor which gives the bus its asynchronous nature.
t3 →The Slave-ready signal arrives at the master, indicating that the input
data are available on the bus. After a delay equivalent to the maximum bus skew
and minimum setup time of master’s input buffer, the master strobes the data into
its input buffer. At the same time, it drops the Master- ready signal, indicating that
it has received the data.
t4 →The master removes the address and command information from the
bus. The delay t4 — t3 is also used to allow for bus skew.
t5 →When the device interface receives the 1 to 0 transition of the Master-
ready signal; it removes the data and Slave-ready signal from the bus.
This completes the input transfer.
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Fig. below shows the timing for an output operation using Handshake control. In
this case, the master places the output data on the data lines and at the same time it
sends the address and command information. The selected slave, when it receives
the Master-ready signal, strobes the data into its output buffer and indicates so by
setting the Slave-ready signal to 1.

Timing of an output operation on Asynchronous bus

As evident from Fig. (I) and Fig. above, the handshake signals are fully
interlocked.
A change of state in one signal is followed by a change in the other signal. This
full handshake scheme provides highest degree of flexibility and reliability.
The main advantage of asynchronous bus is that it eliminates the need for
synchronization of the sender and receiver clocks. The timing of data transfers can
be adjusted easily for different delays introduced by the interface circuitry. But,
the rate of data transfer is slower compared to the synchronous bus.

Interface Circuits
An I/O interface c9nsists of logic circuitry required to connect an I/O
device to a computer bus. On one side of the interface, we have the bus signals for
address, data and control. Another side of the interface has a data path with its
associated controls to transfer data between the interface and the I/O device. This
side is called a port which can be classified as either a parallel or serial port.
An I/O interface generally provides the following functionalities:
A) Provides a storage buffer for at least one word of data.
B) Contains status flags that can be accessed by the processor to determine
whether the buffer is full (for input) or empty (for output).
C) Contains address-decoding circuitry to determine when it is being addressed by
the processor.

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D) Generates the appropriate timing signals required for data transfer the bus.
E) Performs any format conversion (for example, parallel-to-serial or serial-to-
parallel conversion in case of a serial port) that may be necessary to transfer data
between the bus and the I/O device.

Parallel Interface
We start with the discussion of design of a parallel interface for a keyboard.
We describe circuits for an 8-bit input port, 8-bit output port and a combined
general purpose 8-bit parallel port. The interface circuit is assumed to be
connected to 32-bit processor that uses memory-mapped I/O and the asynchronous
bus protocol.

Input Interface:
A simple hardware organization for connecting a keyboard to a processor is
shown in Fig below. The keyboard consists of mechanical switches that are
normally open. When a key is pressed, its switch closes forming a path for
electrical signal. This signal is detected by an encoder circuit that generates the
ASCII code for the corresponding character.

Keyboard to processor connection

The output of the encoder consists of the bits that represent the encoded character
and one control signal called valid, which indicates that a key is being pressed.
This information is sent to the interface circuit, which contains a data register
DATAIN and a status flag SIN. When a key is pressed, the valid signal changes
from 0 to 1, causing the ASCII code to be loaded into DATAIN and SIN will be
set to 1. When the processor reads the character from DATAIN, SIN is cleared to
0. The asynchronous handshake signals control the data transfer on the bus. The
R/W’ signal distinguishes between Read or Write operation.

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Input Interface Circuit

Fig. above shows a detailed circuit for an input interface. The output lines of the
DATAIN register are connected to the data lines of the bus using tri-state drivers.
The SIN signal is generated by a status flag circuit. This signal is sent to the bus
through a tri-state driver. SIN is connected to bit D0, that is, it is bit 0 of the status
register. An address decoder is used to select the input interface, using high-order
31 bits of the address. Address bit A0 determines whether the status or the data
register is to be read when the Master-ready signal is active. The Slave-ready
signal is activated when either Read-status or Read-data signal is 1.
A simple implementation of the status flag circuit is shown in Fig. below
edge-triggered D flip-flop is set to 1 by a rising edge on the ‘Valid signal line’.
This changes the state of the NOR latch such that SIN is set to 1.

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The circuit ensures that SIN can be set only while Master-ready is equal to 0. Both
the flip-flop and the latch are reset to 0 when Read-data is set to 1 to read
DATAIN register.

Circuit for the status flag block

Output Interface:
Fig. below shows the interface diagram to interface an output device like a
printer to a processor. The printer uses two handshake signals ‘Idle’ and ‘Valid’
for controlling the operation. When it is ready to accept a character, it asserts its
Idle signal. The interface circuit places a new character on the data lines and
activates, the Valid signal. Now, the printer removes the Idle signal and starts
printing the character it has received.

Fig (g) Printer to processor connection

The interface has a data register DATAOUT and a status flag SOUT. The SOUT
flag is set to I when the printer is ready to accept another character and cleared to 0
when a new character is loaded into DATAOUT by the processor. Fig (h) shows a
detailed implementation of the output interface.

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Fig (h) Output interface circuit

A single parallel interface can be designed by combining the input and output
interfaces described earlier. This is shown in Fig (j). The interface is selected by
the high-order 30 bits of the address. Address bits Al and A0 select any one of the
following three: two data registers and the STATUS register. We use the label RSI
and RSO (Register Select) to denote the two inputs that determine the register
being selected.
Fig (j) shows separate input and output data lines. A simple and flexible parallel
port can be designed if the data lines to the I/O devices are bidirectional, as in Fig
(k). Data lines P7-PU can be used as input or output lines. The DATAOUT
register is connected to these lines using tri-state drivers that are controlled by a
data direction register, DDR. The processor can write any 8-bit pattern into DDR.
For a given bit, if the DDR value is 1, the corresponding data line acts as a
output line; otherwise, it acts as input line. Two lines C1 and C2 are provided to
control the interaction between the interface circuit and the I/O device. C2 is
bidirectional to provide different modes of signaling. The Ready and Accept lines
are handshake control lines connected to Master-ready and Slave-ready. The input
signal My-address should be connected to the output of an address decoder. There
are three register select lines allowing eight registers in the interface, input and
output data, data direction and control and status registers. An interrupt request
output, INTR, is connected to the interrupt-request line on the computer bus.
Parallel interface circuits are used in Embedded Systems.

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Fig (j) Combined input output interface circuit

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Fig (k) A general 8-bit parallel interface.

Fig (l) shows the timing diagram for an output operation. In clock cycle 1,
the processor sends the address and data. The timing logic sets Go to 1 at the
beginning of clock cycle 2, and the rising edge of that signal loads the output data
into register DATAOUT. Normally, the Slave-ready signal is an open-drain signal
called Slave-ready. This line must have a pull-up resistor connected to ensure that
it is always in the negated (high-voltage) state except when it is asserted (pulled
down) by some device.

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Fig (l) Timing for the output interface.

Serial Interface
A serial port is used to connect the processor to I/O devices that require
transmission of data one bit at a time. The serial interface circuit is communicating
in bit-serial way on the device side and in bit-parallel format on the bus side. The
serial-to-parallel and parallel-to-serial conversion is performed using shift
registers. Fig (m) shows a serial interface circuit. The input shift register accepts
bit-serial input from the input device. When all 8 bits of data are received, the
contents of the shift register are transferred to DATAIN register, in parallel.
The output data in the DATAOUT register are loaded into the output shift
register parallel. The bits are shifted out serially and sent to the output device.
The chip and register select logic has the control signals whose functions
are similar to that described for parallel interface. The status flag SIN is set to 1
when new data are loaded in DATAIN; it is cleared to 0 when the processor reads
the contents of DATAIN.
The SOUT flag related to output buffer DATAOUT is set to 1 when data
are transferred from DATAOUT into the output shift register and is cleared to 0
when the processor writes new data into the DATAOUT register.
If DATAIN and DATAOUT themselves are shift registers, then input and
output shift registers shown in Fig (m) could be eliminated. But, this will
introduce delays when transferring data. After receiving one character from the
serial input, the device can read the next character only after the processor reads
the contents of DATAIN. So, a delay is introduced between the reading of two
successive characters.
The double buffering method shown in the Fig (m) provides some
advantages. As soon as the data are transferred from the input shift register into

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the DATAIN register, the shift register can start accepting the next character from
the device. In the meantime, the processor would be reading the first character
from DATAIN register parallel. Thus, the interface can receive a continuous
stream of serially transferred data. The same analogy works at the output path of
the interface.
Since serial transmission requires fewer wires, the serial interface is the
most convenient way of connecting devices that are physically far apart. For
example, two computers could be connected using a co-axial cable. Similarly, for
long distance communication, telephone line is used as a medium. The
disadvantage of the serial communication is that it is not as fast as parallel data
transfer. The speed of transmission, given as bit rate, depends on the nature of the
devices connected. So, a serial interface should be able to handle wide range of
clock speeds. The circuit of Fig (m) shows the use of separate transmitter and
receiver clocks, to provide flexibility in operations. The serial interface plays an
important role in connecting I/O devices. Different standards like RS-232-C, RS-
422 and RS429 have been developed for serial communication.
A standard circuit that includes the features shown in Fig (m) is known as a
Universal Asynchronous Receiver Transmitter (UART). It is intended to be used
with low speed devices.

Fig (m) A Serial interface circuit

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