Code

--------------------------------------------------------------------------------
--
-- BRAM8k32bit.vhd
--
-- Copyright (C) 2007 Jonas Diemer
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
--------------------------------------------------------------------------------
--
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Single Ported RAM, 32bit wide, 8k deep.
--
-- Instantiates 16 BRAM, each being 8k deep and 2 bit wide. These are
-- concatenated to form a 32bit wide, 8k deep RAM.
--
--------------------------------------------------------------------------------
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity BRAM8k32bit is
Port ( CLK : in STD_LOGIC;
ADDR : in STD_LOGIC_VECTOR (12 downto 0);
WE : in STD_LOGIC;
DOUT : out STD_LOGIC_VECTOR (31 downto 0);
DIN : in STD_LOGIC_VECTOR (31 downto 0));
end BRAM8k32bit;
architecture Behavioral of BRAM8k32bit is
begin
BlockRAMS: for i in 0 to 15 generate

RAMB16_S2_inst : RAMB16_S2
generic map (
INIT => X"0", -- Value of output RAM registers at startup
SRVAL => X"0", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST" -- WRITE_FIRST, READ_FIRST or NO_CHANGE
)
port map (
DO => DOUT(2*i+1 downto 2*i), -- 2-bit Data Output
ADDR => ADDR, -- 13-bit Address Input
CLK => CLK, -- Clock
DI => DIN(2*i+1 downto 2*i), -- 2-bit Data Input
EN => '1', -- RAM Enable Input
SSR => '0', -- Synchronous Set/Reset Input
WE => WE -- Write Enable Input
);
end generate;
end Behavioral;
*******************************************
--------------------------------------------------------------------------------
--
-- clockman.vhd
--
-- Author: Michael "Mr. Sump" Poppitz
--
--
-- This is only a wrapper for Xilinx' DCM component so it doesn't
-- have to go in the main code and can be replaced more easily.
--
-- Creates clk0 with 100MHz.
--
--------------------------------------------------------------------------------
--
library IEEE;
library UNISIM;
entity clockman is
Port (
clkin : in STD_LOGIC; -- clock input
clk0 : out std_logic -- double clock
rate output
);
end clockman;
architecture Behavioral of clockman is
signal clkfb, clkfbbuf, realclk0 : std_logic;
begin
-- DCM: Digital Clock Manager Circuit for Virtex-II/II-Pro and Spartan-3/3E
-- Xilinx HDL Language Template version 8.1i
DCM_baseClock : DCM
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.
0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0
or 16.0
CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 2, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two f
eature
CLKIN_PERIOD => 20.0, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VA
RIABLE
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNC
HRONOUS or
-- an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for freque
ncy synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => TRUE) -- Delay configuration DONE until DCM LOCK, TRUE/FA
LSE
port map (
CLKIN => clkin, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => '0', -- Dynamic phase adjust clock input
PSEN => '0', -- Dynamic phase adjust enable input
PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
RST => '0', -- DCM asynchronous reset input
CLK2X => realclk0,
CLK0 => clkfb,
CLKFB => clkfbbuf
);
-- clkfb is run through a BUFG only to shut up ISE 8.1
BUFG_clkfb : BUFG
port map (
O => clkfbbuf, -- Clock buffer output
I => clkfb -- Clock buffer input
);
clk0 <= realclk0;
end Behavioral;
*************************************
--------------------------------------------------------------------------------
--
-- controller.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
--
--
--
--------------------------------------------------------------------------------
--
--
--
-- Controls the capturing & readback operation.
--
-- If no other operation has been activated, the controller samples data
-- into the memory. When the run signal is received, it continues to do so
-- for fwd * 4 samples and then sends bwd * 4 samples to the transmitter.
-- This allows to capture data from before the trigger match which is a nice
-- feature.
--
--------------------------------------------------------------------------------
--
library IEEE;
entity controller is
Port ( clock : in STD_LOGIC;
reset : in std_logic;
input : in STD_LOGIC_VECTOR (31 downto 0);
inputReady : in std_logic;
run : in std_logic;
wrSize : in std_logic;
data : in STD_LOGIC_VECTOR (31 downto 0);
busy : in std_logic;
send : out std_logic;
output : out STD_LOGIC_VECTOR (31 downto 0);
memoryIn : in STD_LOGIC_VECTOR (31 downto 0);
memoryOut : out STD_LOGIC_VECTOR (31 downto 0);
memoryRead : out STD_LOGIC;
memoryWrite : out STD_LOGIC
);
end controller;
architecture Behavioral of controller is
type CONTROLLER_STATES is (SAMPLE, DELAY, READ, READWAIT);
signal fwd, bwd : std_logic_vector (15 downto 0);
signal ncounter, counter: std_logic_vector (17 downto 0);
signal nstate, state : CONTROLLER_STATES;
signal sendReg : std_logic;
begin
output <= memoryIn;
memoryOut <= input;
send <= sendReg;
-- synchronization and reset logic
process(run, clock, reset)
begin
if reset = '1' then
state <= SAMPLE;
elsif rising_edge(clock) then
state <= nstate;
counter <= ncounter;
end if;
end process;
-- FSM to control the controller action
process(state, run, counter, fwd, inputReady, bwd, busy)
begin
case state is
-- default mode: sample data from input to memory
when SAMPLE =>
if run = '1' then
nstate <= DELAY;
else
nstate <= state;
end if;
ncounter <= (others => '0');
memoryWrite <= inputReady;
memoryRead <= '0';
sendReg <= '0';
-- keep sampling for 4 * fwd + 4 samples after run condi
tion
when DELAY =>
if counter = fwd & "11" then
nstate <= READ;
else
if inputReady = '1' then
ncounter <= counter + 1;
else
ncounter <= counter;
end if;
nstate <= state;
end if;
memoryWrite <= inputReady;
memoryRead <= '0';
sendReg <= '0';
-- read back 4 * bwd + 4 samples after DELAY
-- go into wait state after each sample to give transmit
ter time
when READ =>
if counter = bwd & "11" then
nstate <= SAMPLE;
else
nstate <= READWAIT;
end if;
memoryWrite <= '0';
memoryRead <= '1';
sendReg <= '1';
-- wait for the transmitter to become ready again
when READWAIT =>
if busy = '0' and sendReg = '0' then
nstate <= READ;
else
nstate <= state;
end if;
memoryWrite <= '0';
memoryRead <= '0';
sendReg <= '0';
end case;
end process;
-- set speed and size registers if indicated
process(clock)
begin
if rising_edge(clock) then
if wrSize = '1' then
fwd <= data(31 downto 16);
bwd <= data(15 downto 0);
end if;
end if;
end process;
end Behavioral;
*************************************
--------------------------------------------------------------------------------
--
-- core.vhd
--
--
--
--
--
--------------------------------------------------------------------------------
--
--
--
-- The core contains all "platform independent" modules and provides a
-- simple interface to those components. The core makes the analyzer
-- memory type and computer interface independent.
--
-- This module also provides a better target for test benches as commands can
-- be sent to the core easily.
--
--------------------------------------------------------------------------------
--
library IEEE;
library UNISIM;
entity core is
extReset : in STD_LOGIC;
cmd : in STD_LOGIC_VECTOR (39 downto 0);
execute : in STD_LOGIC;
inputClock : in STD_LOGIC;
sampleReady50 : out STD_LOGIC;
outputSend : out STD_LOGIC;
outputBusy : in STD_LOGIC;
);
end core;
architecture Behavioral of core is
COMPONENT decoder
PORT ( opcode : in STD_LOGIC_VECTOR (7 downto 0);
execute : in std_logic;
clock : in std_logic;
wrtrigmask : out std_logic_vector(3 downto 0);
wrtrigval : out std_logic_vector(3 downto 0);
wrtrigcfg : out std_logic_vector(3 downto 0);
wrspeed : out STD_LOGIC;
wrsize : out std_logic;
wrFlags : out std_logic;
arm : out std_logic;
reset : out std_logic
);
END COMPONENT;
COMPONENT flags
PORT(
data : IN std_logic_vector(8 downto 0);
clock : IN std_logic;
write : IN std_logic;
demux : OUT std_logic;
filter : OUT std_logic;
external : out std_logic;
inverted : out std_logic;
rle : out std_logic
);
END COMPONENT;
COMPONENT sync is
PORT (
clock : in STD_LOGIC;
enableFilter : in STD_LOGIC;
enableDemux : in STD_LOGIC;
falling : in STD_LOGIC;
output : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT sampler
PORT(
input : IN std_logic_vector(31 downto 0);
exClock : in std_logic;
external : in std_logic;
wrDivider : IN std_logic;
sample : OUT std_logic_vector(31 downto 0);
ready : OUT std_logic;
ready50 : out std_logic
);
END COMPONENT;
COMPONENT trigger
PORT(
wrMask : IN std_logic_vector(3 downto 0);
wrValue : IN std_logic_vector(3 downto 0);
wrConfig : IN std_logic_vector(3 downto 0);
arm : IN std_logic;
demuxed : in std_logic;
run : out STD_LOGIC
);
END COMPONENT;
COMPONENT controller
PORT(
data : in std_logic_vector(31 downto 0);
wrSize : in std_logic;
run : in std_logic;
busy : in std_logic;
send : out std_logic;
output : out std_logic_vector(31 downto 0);
);
END COMPONENT;
COMPONENT rle_enc
PORT(
reset : IN std_logic;
dataIn : IN std_logic_vector(31 downto 0);
validIn : IN std_logic;
enable : IN std_logic;
dataOut : OUT std_logic_vector(31 downto 0);
validOut : OUT std_logic
);
END COMPONENT;
signal opcode : std_logic_vector (7 downto 0);
signal data, rleOut : std_logic_vector (31 downto 0);
signal sample, syncedInput : std_logic_vector (31 downto 0);
signal sampleClock, run, reset, rleValid, rleEnable : std_logic;
signal wrtrigmask, wrtrigval, wrtrigcfg : std_logic_vector(3 downto 0);
signal wrDivider, wrsize, arm, resetCmd: std_logic;
signal flagDemux, flagFilter, flagExternal, flagInverted, wrFlags, sampleReady:
std_logic;
begin
data <= cmd(39 downto 8);
opcode <= cmd(7 downto 0);
reset <= extReset or resetCmd;
-- select between internal and external sampling clock
BUFGMUX_intex: BUFGMUX
port map (
O => sampleClock, -- Clock MUX output
I0 => clock, -- Clock0 input
I1 => inputClock, -- Clock1 input
S => flagExternal -- Clock select input
);
Inst_decoder: decoder PORT MAP(
opcode => opcode,
execute => execute,
clock => clock,
wrtrigmask => wrtrigmask,
wrtrigval => wrtrigval,
wrtrigcfg => wrtrigcfg,
wrspeed => wrDivider,
wrsize => wrsize,
wrFlags => wrFlags,
arm => arm,
reset => resetCmd
);
Inst_flags: flags PORT MAP(
data => data(8 downto 0),
clock => clock,
write => wrFlags,
demux => flagDemux,
filter => flagFilter,
external => flagExternal,
inverted => flagInverted,
rle => rleEnable
);
Inst_sync: sync PORT MAP(
input => input,
clock => sampleClock,
enableFilter => flagFilter,
enableDemux => flagDemux,
falling => flagInverted,
output => syncedInput
);
Inst_sampler: sampler PORT MAP(
input => syncedInput,
clock => clock,
exClock => inputClock, -- use sampleClock?
external => flagExternal,
data => data(23 downto 0),
wrDivider => wrDivider,
sample => sample,
ready => sampleReady,
ready50 => sampleReady50
);
Inst_trigger: trigger PORT MAP(
input => sample,
inputReady => sampleReady,
data => data,
clock => clock,
reset => reset,
wrMask => wrtrigmask,
wrValue => wrtrigval,
wrConfig => wrtrigcfg,
arm => arm,
demuxed => flagDemux,
run => run
);
Inst_controller: controller PORT MAP(
clock => clock,
reset => reset,
input => rleOut,
inputReady => rleValid,
data => data,
wrSize => wrsize,
run => run,
busy => outputBusy,
send => outputSend,
output => output,
memoryIn => memoryIn,
memoryOut => memoryOut,
memoryRead => memoryRead,
memoryWrite => memoryWrite
);
Inst_rle_enc: rle_enc PORT MAP(
clock => clock,
reset => reset,
dataIn => sample,
validIn => sampleReady,
enable => rleEnable,
dataOut => rleOut,
validOut => rleValid
);
end Behavioral;
******************************************
--------------------------------------------------------------------------------
--
-- decoder.vhd
--
--
--
--
--
--------------------------------------------------------------------------------
--
--
--
-- Takes the opcode from the command received by the receiver and decodes it.
-- The decoded command will be executed for one cycle.
--
-- The receiver keeps the cmd output active long enough so all the
-- data is still available on its cmd output when the command has
-- been decoded and sent out to other modules with the next
-- clock cycle. (Maybe this paragraph should go in receiver.vhd?)
--
--------------------------------------------------------------------------------
--
library IEEE;
entity decoder is
Port (
opcode : in STD_LOGIC_VECTOR (7 downto 0);
execute : in std_logic;
wrtrigmask : out STD_LOGIC_VECTOR (3 downto 0);
wrtrigval : out STD_LOGIC_VECTOR (3 downto 0);
wrtrigcfg : out STD_LOGIC_VECTOR (3 downto 0);
wrspeed : out STD_LOGIC;
wrsize : out STD_LOGIC;
wrFlags : out std_logic;
arm : out STD_LOGIC;
reset : out STD_LOGIC
);
end decoder;
architecture Behavioral of decoder is
signal exe, exeReg: std_logic;
begin
exe <= execute;
process(clock)
begin
reset <= '0'; arm <= '0';
wrspeed <= '0'; wrsize <= '0'; wrFlags <= '0';
wrtrigmask <= "0000"; wrtrigval <= "0000"; wrtrigcfg <=
"0000";
if (exe and not exeReg) = '1' then
case opcode is
-- short commands
when x"00" => reset <= '1';
when x"01" => arm <= '1';
-- long commands
when x"80" => wrspeed <= '1';
when x"81" => wrsize <= '1';
when x"82" => wrFlags <= '1';
when x"C0" => wrtrigmask(0) <= '1';
when x"C1" => wrtrigval(0) <= '1';
when x"C2" => wrtrigcfg(0) <= '1';
when x"C6" => wrtrigcfg(1) <= '1';
when x"CA" => wrtrigcfg(2) <= '1';
when x"CC" => wrtrigmask(3) <= '1';
when x"CD" => wrtrigval(3) <= '1';
when x"CE" => wrtrigcfg(3) <= '1';
when others =>
end case;
end if;
exeReg <= exe;
end if;
end process;
end Behavioral;
*****************************************
--------------------------------------------------------------------------------
--
-- demux.vhd
--
--
--
--
--
--------------------------------------------------------------------------------
--
--
--
-- Demultiplexes 16 input channels into 32 output channels,
-- thus doubling the sampling rate for those channels.
--
-- This module barely does anything anymore, but is kept for historical reasons.
--
--------------------------------------------------------------------------------
--
library IEEE;
entity demux is
Port ( input : in STD_LOGIC_VECTOR (15 downto 0);
input180 : in STD_LOGIC_VECTOR (15 downto 0);
output : out STD_LOGIC_VECTOR (31 downto 0));
end demux;
architecture Behavioral of demux is
begin
output(15 downto 0) <= input;
process (clock)
begin
output(31 downto 16) <= input180;
end if;
end process;
end Behavioral;
********************************************
--------------------------------------------------------------------------------
--
-- display.vhd
--
--
--
--
--
--------------------------------------------------------------------------------
--
--
--
-- Provides 7 segment display multiplexing.
-- No encoding is performed. Input will be displayed in raw format.
-- This allows to display 32bit on the on-board 4 digit display.
-- (The dot serves as 8th bit.)
--
--------------------------------------------------------------------------------
--
library IEEE;
entity display is
Port ( data : in STD_LOGIC_VECTOR (31 downto 0);
an : inout std_logic_vector (3 downto 0);
segment : out STD_LOGIC_VECTOR (7 downto 0));
end display;
architecture Behavioral of display is
signal counter : STD_LOGIC_VECTOR (17 downto 0);
begin
an(0) <= counter(17) or counter(16);
an(1) <= counter(17) or not counter(16);
an(2) <= not counter(17) or counter(16);
an(3) <= not counter(17) or not counter(16);
segment(0) <= not ((an(0) or data(0)) and (an(1) or data( 8)) and (an(2)
or data(16)) and (an(3) or data(24)));
segment(1) <= not ((an(0) or data(1)) and (an(1) or data( 9)) and (an(2)
segment(2) <= not ((an(0) or data(2)) and (an(1) or data(10)) and (an(2)
process(clock)
begin
counter <= counter + 1;
end if;
end process;
end Behavioral;
***************************************
--------------------------------------------------------------------------------
--
-- eia232.vhd
--
--
--
--
--
--------------------------------------------------------------------------------
--
--
--
-- EIA232 aka RS232 interface.
--
--------------------------------------------------------------------------------
--
library IEEE;
entity eia232 is
generic (
FREQ : integer;
SCALE : integer;
RATE : integer
);
Port (
speed : in std_logic_vector (1 downto 0);
rx : in STD_LOGIC;
tx : out STD_LOGIC;
cmd : out STD_LOGIC_VECTOR (39 downto 0);
execute : out STD_LOGIC;
send : in STD_LOGIC;
busy : out STD_LOGIC
);
end eia232;
architecture Behavioral of eia232 is
COMPONENT prescaler
generic (
SCALE : integer
);
PORT(
div : IN std_logic_vector(1 downto 0);
scaled : OUT std_logic
);
END COMPONENT;
COMPONENT receiver
generic (
FREQ : integer;
RATE : integer
);
PORT(
rx : IN std_logic;
trxClock : IN std_logic;
reset : in STD_LOGIC;
op : out std_logic_vector(7 downto 0);
data : out std_logic_vector(31 downto 0);
execute : out STD_LOGIC
);
END COMPONENT;
COMPONENT transmitter
generic (
FREQ : integer;
RATE : integer
);
PORT(
disabledGroups : in std_logic_vector (3 downto 0);
id : in std_logic;
xon : in std_logic;
xoff : in std_logic;
tx : OUT std_logic;
busy : out std_logic
);
END COMPONENT;
constant TRXFREQ : integer := FREQ / SCALE; -- reduced rx & tx clock for rec
eiver and transmitter
signal trxClock, executeReg, executePrev, id, xon, xoff, wrFlags : std_logic;
signal disabledGroupsReg : std_logic_vector(3 downto 0);
signal opcode : std_logic_vector(7 downto 0);
signal opdata : std_logic_vector(31 downto 0);
begin
cmd <= opdata & opcode;
execute <= executeReg;
-- process special uart commands that do not belong in core decoder
process(clock)
begin
id <= '0'; xon <= '0'; xoff <= '0'; wrFlags <= '0';
executePrev <= executeReg;
if executePrev = '0' and executeReg = '1' then
case opcode is
when x"02" => id <= '1';
when x"11" => xon <= '1';
when x"13" => xoff <= '1';
when x"82" => wrFlags <= '1';
when others =>
end case;
end if;
end if;
end process;
process(clock)
begin
if wrFlags = '1' then
disabledGroupsReg <= opdata(5 downto 2);
end if;
end if;
end process;
Inst_prescaler: prescaler
generic map (
SCALE => SCALE
)
PORT MAP(
clock => clock,
reset => reset,
div => speed,
scaled => trxClock
);
Inst_receiver: receiver
generic map (
FREQ => TRXFREQ,
RATE => RATE
)
PORT MAP(
rx => rx,
clock => clock,
trxClock => trxClock,
reset => reset,
op => opcode,
data => opdata,
execute => executeReg
);
Inst_transmitter: transmitter
generic map (
FREQ => TRXFREQ,
RATE => RATE
)
PORT MAP(
data => data,
disabledGroups => disabledGroupsReg,
write => send,
id => id,
xon => xon,
xoff => xoff,
clock => clock,
trxClock => trxClock,
reset => reset,
tx => tx,
busy => busy
);
end Behavioral;
****************************************
--------------------------------------------------------------------------------
--
-- filter.vhd
--
--
--
--
--
--------------------------------------------------------------------------------
--
--
--
-- Fast 32 channel digital noise filter using a single LUT function for each
-- individual channel. It will filter out all pulses that only appear for half
-- a clock cycle. This way a pulse has to be at least 5-10ns long to be accepted
-- as valid. This is sufficient for sample rates up to 100MHz.
--
--------------------------------------------------------------------------------
--
library IEEE;
entity filter is
input180 : in STD_LOGIC_VECTOR (31 downto 0);
end filter;
architecture Behavioral of filter is
signal input360, input180Delay, result : STD_LOGIC_VECTOR (31 downto 0);
begin
process(clock)
begin
-- determine next result
for i in 31 downto 0 loop
result(i) <= (result(i) or input360(i) or input(
i)) and input180Delay(i);
end loop;
-- shift in input data
input360 <= input;
input180Delay <= input180;
end if;
end process;
output <= result;
end Behavioral;
*********************************
--------------------------------------------------------------------------------
--
-- flags.vhd
--
--
--
--
--
--------------------------------------------------------------------------------
--
--
--
-- Flags register.
--
--------------------------------------------------------------------------------
--
library IEEE;
entity flags is
Port ( data : in STD_LOGIC_VECTOR(8 downto 0);
write : in STD_LOGIC;
demux : out STD_LOGIC;
filter : out STD_LOGIC;
external : out std_logic;
inverted : out std_logic;
rle : out std_logic
);
end flags;
architecture Behavioral of flags is
begin
-- write flags
process (clock)
begin
if rising_edge(clock) and write = '1' then
demux <= data(0);
filter <= data(1);
external <= data(6);
inverted <= data(7);
rle <= data(8);
end if;
end process;
end Behavioral;
******************************
################################################################################
##
## la.ucf
##
## Author: Michael "Mr. Sump" Poppitz
##
## Details: http://sump.org/projects/analyzer/
##
## Contains assignment and iostandard information for
## all used pins as well as timing and area constraints.
################################################################################
##
NET "an<0>" LOC = "d14" | IOSTANDARD = LVTTL ;
NET "an<1>" LOC = "g14" | IOSTANDARD = LVTTL ;
NET "an<2>" LOC = "f14" | IOSTANDARD = LVTTL ;
NET "an<3>" LOC = "e13" | IOSTANDARD = LVTTL ;
NET "xtalClock" LOC = "t9" | IOSTANDARD = LVTTL ;
NET "exClock" LOC = "d9" | IOSTANDARD = LVTTL ;
NET "input<0>" LOC = "c10" | IOSTANDARD = LVTTL ;
NET "input<1>" LOC = "t3" | IOSTANDARD = LVTTL ;
NET "input<2>" LOC = "e10" | IOSTANDARD = LVTTL ;
NET "input<3>" LOC = "n11" | IOSTANDARD = LVTTL ;
NET "input<5>" LOC = "p10" | IOSTANDARD = LVTTL ;
NET "input<6>" LOC = "d11" | IOSTANDARD = LVTTL ;
NET "input<7>" LOC = "r10" | IOSTANDARD = LVTTL ;
NET "input<9>" LOC = "t7" | IOSTANDARD = LVTTL ;
NET "input<13>" LOC = "n6" | IOSTANDARD = LVTTL ;
NET "input<14>" LOC = "b16" | IOSTANDARD = LVTTL ;
NET "input<15>" LOC = "m6" | IOSTANDARD = LVTTL ;
NET "input<23>" LOC = "f15" | IOSTANDARD = LVTTL ;
NET "input<24>" LOC = "g15" | IOSTANDARD = LVTTL ;
NET "input<25>" LOC = "g16" | IOSTANDARD = LVTTL ;
NET "input<26>" LOC = "h15" | IOSTANDARD = LVTTL ;
NET "input<27>" LOC = "h16" | IOSTANDARD = LVTTL ;
NET "input<28>" LOC = "j16" | IOSTANDARD = LVTTL ;
NET "input<29>" LOC = "k16" | IOSTANDARD = LVTTL ;
NET "input<30>" LOC = "k15" | IOSTANDARD = LVTTL ;
NET "input<31>" LOC = "l15" | IOSTANDARD = LVTTL ;
NET "ready50" LOC = "m11" | IOSTANDARD = LVTTL ;
NET "led<0>" LOC = "k12" | IOSTANDARD = LVTTL ;
NET "led<1>" LOC = "p14" | IOSTANDARD = LVTTL ;
NET "led<2>" LOC = "l12" | IOSTANDARD = LVTTL ;
NET "led<3>" LOC = "n14" | IOSTANDARD = LVTTL ;
NET "led<5>" LOC = "n12" | IOSTANDARD = LVTTL ;
NET "ramA<0>" LOC = "l5" | IOSTANDARD = LVTTL ;
NET "ramA<10>" LOC = "g5" | IOSTANDARD = LVTTL ;
NET "ramA<11>" LOC = "h3" | IOSTANDARD = LVTTL ;
NET "ramA<12>" LOC = "h4" | IOSTANDARD = LVTTL ;
NET "ramA<13>" LOC = "j4" | IOSTANDARD = LVTTL ;
NET "ramA<14>" LOC = "j3" | IOSTANDARD = LVTTL ;
NET "ramA<15>" LOC = "k3" | IOSTANDARD = LVTTL ;
NET "ramA<16>" LOC = "k5" | IOSTANDARD = LVTTL ;
NET "ramA<1>" LOC = "n3" | IOSTANDARD = LVTTL ;
NET "ramA<2>" LOC = "m4" | IOSTANDARD = LVTTL ;
NET "ramA<3>" LOC = "m3" | IOSTANDARD = LVTTL ;
NET "ramA<5>" LOC = "g4" | IOSTANDARD = LVTTL ;
NET "ramA<6>" LOC = "f3" | IOSTANDARD = LVTTL ;
NET "ramA<7>" LOC = "f4" | IOSTANDARD = LVTTL ;
NET "ramA<8>" LOC = "e3" | IOSTANDARD = LVTTL ;
NET "ramA<9>" LOC = "e4" | IOSTANDARD = LVTTL ;
NET "ramCE1" LOC = "p7" | IOSTANDARD = LVTTL ;
NET "ramCE2" LOC = "n5" | IOSTANDARD = LVTTL ;
NET "ramIO1<0>" LOC = "n7" | IOSTANDARD = LVTTL | SLEW = FAST ;
NET "ramIO1<10>" LOC = "f2" | IOSTANDARD = LVTTL | SLEW = FAST ;
NET "ramIO1<11>" LOC = "h1" | IOSTANDARD = LVTTL | SLEW = FAST ;
NET "ramIO1<12>" LOC = "j2" | IOSTANDARD = LVTTL | SLEW = FAST ;
NET "ramIO1<13>" LOC = "l2" | IOSTANDARD = LVTTL | SLEW = FAST ;
NET "ramIO1<14>" LOC = "p1" | IOSTANDARD = LVTTL | SLEW = FAST ;
NET "ramIO1<15>" LOC = "r1" | IOSTANDARD = LVTTL | SLEW = FAST ;
NET "ramIO1<1>" LOC = "t8" | IOSTANDARD = LVTTL | SLEW = FAST ;
NET "ramIO1<3>" LOC = "t5" | IOSTANDARD = LVTTL | SLEW = FAST ;
NET "ramIO1<5>" LOC = "c2" | IOSTANDARD = LVTTL | SLEW = FAST ;
NET "ramIO1<7>" LOC = "b1" | IOSTANDARD = LVTTL | SLEW = FAST ;
NET "ramIO1<8>" LOC = "d3" | IOSTANDARD = LVTTL | SLEW = FAST ;
NET "ramIO2<10>" LOC = "g1" | IOSTANDARD = LVTTL | SLEW = FAST ;
NET "ramIO2<11>" LOC = "f5" | IOSTANDARD = LVTTL | SLEW = FAST ;
NET "ramIO2<13>" LOC = "k2" | IOSTANDARD = LVTTL | SLEW = FAST ;
NET "ramIO2<14>" LOC = "m1" | IOSTANDARD = LVTTL | SLEW = FAST ;
NET "ramIO2<2>" LOC = "m2" | IOSTANDARD = LVTTL | SLEW = FAST ;
NET "ramIO2<3>" LOC = "k1" | IOSTANDARD = LVTTL | SLEW = FAST ;
NET "ramIO2<4>" LOC = "j1" | IOSTANDARD = LVTTL | SLEW = FAST ;
NET "ramIO2<5>" LOC = "g2" | IOSTANDARD = LVTTL | SLEW = FAST ;
NET "ramIO2<6>" LOC = "e1" | IOSTANDARD = LVTTL | SLEW = FAST ;
NET "ramIO2<9>" LOC = "e2" | IOSTANDARD = LVTTL | SLEW = FAST ;
NET "ramLB1" LOC = "p6" | IOSTANDARD = LVTTL ;
NET "ramLB2" LOC = "p5" | IOSTANDARD = LVTTL ;
NET "ramOE" LOC = "k4" | IOSTANDARD = LVTTL ;
NET "ramUB1" LOC = "t4" | IOSTANDARD = LVTTL ;
NET "ramUB2" LOC = "r4" | IOSTANDARD = LVTTL ;
NET "ramWE" LOC = "g3" | IOSTANDARD = LVTTL ;
NET "resetSwitch" LOC = "l14" | IOSTANDARD = LVTTL ;
NET "rx" LOC = "t13" | IOSTANDARD = LVTTL ;
NET "segment<0>" LOC = "e14" | IOSTANDARD = LVTTL ;
NET "segment<1>" LOC = "g13" | IOSTANDARD = LVTTL ;
NET "segment<2>" LOC = "n15" | IOSTANDARD = LVTTL ;
NET "segment<3>" LOC = "p15" | IOSTANDARD = LVTTL ;
NET "segment<4>" LOC = "r16" | IOSTANDARD = LVTTL ;
NET "segment<5>" LOC = "f13" | IOSTANDARD = LVTTL ;
NET "segment<6>" LOC = "n16" | IOSTANDARD = LVTTL ;
NET "segment<7>" LOC = "p16" | IOSTANDARD = LVTTL ;
NET "switch<0>" LOC = "f12" | IOSTANDARD = LVTTL ;
NET "switch<1>" LOC = "g12" | IOSTANDARD = LVTTL ;
NET "tx" LOC = "r13" | IOSTANDARD = LVTTL ;
NET "xtalClock" TNM_NET = "xtalClock";

TIMESPEC "TS_xtalClock" = PERIOD "xtalClock" 20 ns HIGH 50 %;
# ignore paths resulting from flags as those will
# not change during time critical operations
NET "Inst_core/Inst_flags/demux" TIG;
NET "Inst_core/Inst_flags/filter" TIG;
NET "Inst_core/Inst_flags/inverted" TIG;
NET "Inst_core/Inst_flags/external" TIG;
#INST "Inst_sync/*" AREA_GROUP = "in";
#AREA_GROUP "in" COMPRESSION = 1;
******************************************
--------------------------------------------------------------------------------
--
-- la.vhd
--
--
--
--
--
--------------------------------------------------------------------------------
--
--
--
-- Logic Analyzer top level module. It connects the core with the hardware
-- dependend IO modules and defines all inputs and outputs that represent
-- phyisical pins of the fpga.
--
-- It defines two constants FREQ and RATE. The first is the clock frequency
-- used for receiver and transmitter for generating the proper baud rate.
-- The second defines the speed at which to operate the serial port.
--
--------------------------------------------------------------------------------
--
library IEEE;
library UNISIM;
entity la is
Port(
resetSwitch : in std_logic;
xtalClock : in std_logic;
input : in std_logic_vector(31 downto 0);
ready50 : out std_logic;
rx : in std_logic;
tx : inout std_logic;
an : OUT std_logic_vector(3 downto 0);
segment : OUT std_logic_vector(7 downto 0);
led : OUT std_logic_vector(7 downto 0);
switch : in std_logic_vector(1 downto 0);
ramIO1 : INOUT std_logic_vector(15 downto 0);
ramA : OUT std_logic_vector(17 downto 0);
ramWE : OUT std_logic;
ramOE : OUT std_logic;
ramCE1 : OUT std_logic;
ramUB1 : OUT std_logic;
ramLB1 : OUT std_logic;
ramLB2 : OUT std_logic
);
end la;
architecture Behavioral of la is
COMPONENT clockman
PORT(
clkin : in STD_LOGIC;
clk0 : out std_logic
);
END COMPONENT;
COMPONENT display
PORT(
an : OUT std_logic_vector(3 downto 0);
segment : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
COMPONENT eia232
generic (
FREQ : integer;
SCALE : integer;
RATE : integer
);
PORT(
speed : IN std_logic_vector(1 downto 0);
rx : IN std_logic;
send : IN std_logic;
tx : OUT std_logic;
cmd : OUT std_logic_vector(39 downto 0);
execute : OUT std_logic;
busy : OUT std_logic
);
END COMPONENT;
COMPONENT core
PORT(
extReset : IN std_logic;
cmd : IN std_logic_vector(39 downto 0);
execute : IN std_logic;
inputClock : IN std_logic;
sampleReady50 : OUT std_logic;
memoryIn : IN std_logic_vector(31 downto 0);
memoryOut : OUT std_logic_vector(31 downto 0);
memoryRead : OUT std_logic;
memoryWrite : OUT std_logic
);
END COMPONENT;
COMPONENT sram
PORT(
output : OUT std_logic_vector(31 downto 0);
read : IN std_logic;
);
END COMPONENT;
signal cmd : std_logic_vector (39 downto 0);
signal memoryIn, memoryOut : std_logic_vector (31 downto 0);
signal output : std_logic_vector (31 downto 0);
signal clock : std_logic;
signal read, write, execute, send, busy : std_logic;
constant FREQ : integer := 100000000; -- limited to 10
0M by onboard SRAM
constant TRXSCALE : integer := 28; -- 100M
/ 28 / 115200 = 31 (5bit)
constant RATE : integer := 115200; -- maxim
um & base rate
begin
led(7 downto 0) <= exClock & "00" & switch & "000";
Inst_clockman: clockman PORT MAP(
clkin => xtalClock,
clk0 => clock
);
Inst_display: display PORT MAP(
data => memoryIn,
clock => clock,
an => an,
segment => segment
);
Inst_eia232: eia232
generic map (
FREQ => FREQ,
SCALE => TRXSCALE,
RATE => RATE
)
PORT MAP(
clock => clock,
reset => resetSwitch,
speed => switch,
rx => rx,
tx => tx,
cmd => cmd,
execute => execute,
data => output,
send => send,
busy => busy
);
Inst_core: core PORT MAP(
clock => clock,
extReset => resetSwitch,
cmd => cmd,
execute => execute,
input => input,
inputClock => exClock,
sampleReady50 => ready50,
output => output,
outputSend => send,
outputBusy => busy,
memoryRead => read,
memoryWrite => write
);
Inst_sram: sram PORT MAP(
clock => clock,
input => memoryOut,
output => memoryIn,
read => read,
write => write,
ramA => ramA,
ramWE => ramWE,
ramOE => ramOE,
ramIO1 => ramIO1,
ramCE1 => ramCE1,
ramUB1 => ramUB1,
ramLB1 => ramLB1,
ramIO2 => ramIO2,
ramCE2 => ramCE2,
ramUB2 => ramUB2,
ramLB2 => ramLB2
);
end Behavioral;
*************************************************
################################################################################
##
## la.ucf
##
## Author: Michael "Mr. Sump" Poppitz
##
## Details: http://sump.org/projects/analyzer/
##
## Contains assignment and iostandard information for
## all used pins as well as timing and area constraints.
##
## MODIFIED for use of Xilinx Spartan 3e Starter Kit
################################################################################
##
# an (decimal points?) - removed
# Crystal Clock - use 50MHz onboard oscillator
NET "xtalClock" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
# Define clock period for 50 MHz oscillator (40%/60% duty-cycle)
NET "xtalClock" PERIOD = 20.0ns HIGH 40%;
# external Clock - use Auxiliary clock
NET "exClock" LOC = "B8" | IOSTANDARD = LVCMOS33 ;
# Capture inputs - use FX2 Connector (except those shared with the LED)
# These four connections are shared with the J1 6-pin accessory header
NET "input<0>" LOC = "B4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "input<1>" LOC = "A4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "input<2>" LOC = "D5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "input<3>" LOC = "C5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "input<6>" LOC = "E7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "input<7>" LOC = "F7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "input<10>" LOC = "F8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
# The discrete LEDs are shared with the following 8 FX2 connections
#NET "FX2_IO<13>" LOC = "F9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<14>" LOC = "E9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<15>" LOC = "D11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8
;
#NET "FX2_IO<16>" LOC = "C11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8
;
#NET "FX2_IO<17>" LOC = "F11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8
;
#NET "FX2_IO<18>" LOC = "E11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8
;
#NET "FX2_IO<19>" LOC = "E12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8
;
#NET "FX2_IO<20>" LOC = "F12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8
;
NET "input<25>" LOC = "G9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
# ready50 (next sample ready) - removed
# LED - use LED<7:0>
NET "led<0>" LOC = "f12" | IOSTANDARD = LVTTL ;
NET "led<1>" LOC = "e12" | IOSTANDARD = LVTTL ;
NET "led<4>" LOC = "c11" | IOSTANDARD = LVTTL ;
NET "led<5>" LOC = "d11" | IOSTANDARD = LVTTL ;
# RESET - use BTN_SOUTH
NET "resetSwitch" LOC = "k17" | IOSTANDARD = LVTTL | PULLDOWN ;
# SWITCH - use SW0 and SW1
NET "switch<0>" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;
NET "switch<1>" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ;
## RS232 - use DCE port
NET "rx" LOC = "r7" | IOSTANDARD = LVTTL ;
NET "tx" LOC = "m14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
NET "xtalClock" TNM_NET = "xtalClock";

TIMESPEC "TS_xtalClock" = PERIOD "xtalClock" 20 ns HIGH 50 %;
# ignore paths resulting from flags as those will
# not change during time critical operations
NET "Inst_core/Inst_flags/demux" TIG;
NET "Inst_core/Inst_flags/filter" TIG;
NET "Inst_core/Inst_flags/inverted" TIG;
NET "Inst_core/Inst_flags/external" TIG;
#INST "Inst_sync/*" AREA_GROUP = "in";
#AREA_GROUP "in" COMPRESSION = 1;
***********************************************
--------------------------------------------------------------------------------
--
-- la.vhd
--
--
--
--
--
--------------------------------------------------------------------------------
--
--
--
-- Logic Analyzer top level module. It connects the core with the hardware
-- dependend IO modules and defines all inputs and outputs that represent
-- phyisical pins of the fpga.
--
-- It defines two constants FREQ and RATE. The first is the clock frequency
-- used for receiver and transmitter for generating the proper baud rate.
-- The second defines the speed at which to operate the serial port.
--
--------------------------------------------------------------------------------
--
library IEEE;
library UNISIM;
entity la is
Port(
resetSwitch : in std_logic;
xtalClock : in std_logic;
rx : in std_logic;
tx : inout std_logic;
led : OUT std_logic_vector(7 downto 0);
switch : in std_logic_vector(1 downto 0)
);
end la;
architecture Behavioral of la is
COMPONENT clockman
PORT(
clkin : in STD_LOGIC;
clk0 : out std_logic
);
END COMPONENT;
COMPONENT eia232
generic (
FREQ : integer;
SCALE : integer;
RATE : integer
);
PORT(
speed : IN std_logic_vector(1 downto 0);
rx : IN std_logic;
send : IN std_logic;
tx : OUT std_logic;
cmd : OUT std_logic_vector(39 downto 0);
execute : OUT std_logic;
busy : OUT std_logic
);
END COMPONENT;
COMPONENT core
PORT(
);
END COMPONENT;
COMPONENT sram_bram
PORT(
read : IN std_logic;
write : IN std_logic
);
END COMPONENT;
signal cmd : std_logic_vector (39 downto 0);

signal memoryIn, memoryOut : std_logic_vector (31 downto 0);
signal probeInput : std_logic_vector (31 downto 0);
signal output : std_logic_vector (31 downto 0);
signal clock : std_logic;
signal read, write, execute, send, busy : std_logic;
signal test_counter : std_logic_vector (40 downto 0);
constant FREQ : integer := 100000000; -- limited to 10
0M by onboard SRAM
constant TRXSCALE : integer := 28; -- 100M
/ 28 / 115200 = 31 (5bit)
constant RATE : integer := 115200; -- maxim
um & base rate
begin
led(7 downto 0) <= exClock & resetSwitch & "0" & switch & "0" & rx & tx;
--& "000";
-- test counter
process(clock)
begin
test_counter <= test_counter + 1;
end if;
end process;
probeInput <= input;
-- probeInput <= test_counter(40 downto 9); -- use this to connect a cou
nter to the inputs
Inst_clockman: clockman PORT MAP(
clkin => xtalClock,
clk0 => clock
);
Inst_eia232: eia232
generic map (
FREQ => FREQ,
SCALE => TRXSCALE,
RATE => RATE
)
PORT MAP(
clock => clock,
reset => resetSwitch,
speed => switch,
rx => rx,
tx => tx,
cmd => cmd,
execute => execute,
data => output,
send => send,
busy => busy
);
Inst_core: core PORT MAP(
clock => clock,
extReset => resetSwitch,
cmd => cmd,
execute => execute,
input => probeInput,
inputClock => exClock,
--sampleReady50 => ready50,
output => output,
outputSend => send,
outputBusy => busy,
memoryRead => read,
memoryWrite => write
);
Inst_sram: sram_bram PORT MAP(
clock => clock,
input => memoryOut,
output => memoryIn,
read => read,
write => write
);
end Behavioral;
*****************************
--------------------------------------------------------------------------------
--
-- prescaler.vhd
--
--
--
--
--
--------------------------------------------------------------------------------
--
--
--
-- Shared prescaler for transmitter and receiver timings.
-- Used to control the transfer speed.
--
--------------------------------------------------------------------------------
--
library IEEE;
entity prescaler is
generic (
SCALE : integer
);
div : in std_logic_vector(1 downto 0);
scaled : out std_logic
);
end prescaler;
architecture Behavioral of prescaler is
signal counter : integer range 0 to (6 * SCALE) - 1;
begin
process(clock, reset)
begin
if reset = '1' then
counter <= 0;
if
(counter = SCALE - 1 and div = "00")
-- 115200
or (counter = 2 * SCALE - 1 and div = "01")
-- 57600
-- 38400
-- 19200
then
counter <= 0;
scaled <= '1';
else
scaled <= '0';
end if;
end if;
end process;
end Behavioral;
*******************************
--------------------------------------------------------------------------------
--
-- receiver.vhd
--
--
--
--
--
--------------------------------------------------------------------------------
--
--
--
-- Receives commands from the serial port. The first byte is the commands
-- opcode, the following (optional) four byte are the command data.
-- Commands that do not have the highest bit in their opcode set are
-- considered short commands without data (1 byte long). All other commands are
-- long commands which are 5 bytes long.
--
-- After a full command has been received it will be kept available for 10 cycle
s
-- on the op and data outputs. A valid command can be detected by checking if th
e
-- execute output is set. After 10 cycles the registers will be cleared
-- automatically and the receiver waits for new data from the serial port.
--
--------------------------------------------------------------------------------
--
library IEEE;
entity receiver is
generic (
FREQ : integer;
RATE : integer
);
Port ( rx : in STD_LOGIC;
op : out STD_LOGIC_VECTOR (7 downto 0);
data : out STD_LOGIC_VECTOR (31 downto 0);
execute : out STD_LOGIC
);
end receiver;
architecture Behavioral of receiver is
type UART_STATES is (INIT, WAITSTOP, WAITSTART, WAITBEGIN, READBYTE, ANA
LYZE, READY);
constant BITLENGTH : integer := FREQ / RATE;
signal counter, ncounter : integer range 0 to BITLENGTH; -- clock
prescaling counter
signal bitcount, nbitcount : integer range 0 to 8; -- count
rxed bits of current byte
signal bytecount, nbytecount : integer range 0 to 5; -- count
rxed bytes of current command
signal state, nstate : UART_STATES;
-- receiver state
signal opcode, nopcode : std_logic_vector (7 downto 0); -- opcode byte
signal dataBuf, ndataBuf : std_logic_vector (31 downto 0); -- data dword
begin
op <= opcode;
data <= dataBuf;
begin
if reset = '1' then
state <= INIT;
counter <= ncounter;
bitcount <= nbitcount;
bytecount <= nbytecount;
dataBuf <= ndataBuf;
opcode <= nopcode;
state <= nstate;
end if;
end process;
process(trxClock, state, counter, bitcount, bytecount, dataBuf, opcode,
rx)
begin
case state is
-- reset uart
when INIT =>
ncounter <= 0;
nbitcount <= 0;
nbytecount <= 0;
nopcode <= (others => '0');
ndataBuf <= (others => '0');
nstate <= WAITSTOP;
-- wait for stop bit
when WAITSTOP =>
ncounter <= 0;
nbitcount <= 0;
nbytecount <= bytecount;
nopcode <= opcode;
ndataBuf <= dataBuf;
if rx = '1' then
nstate <= WAITSTART;
else
nstate <= state;
end if;
-- wait for start bit
when WAITSTART =>
ncounter <= 0;
nbitcount <= 0;
nopcode <= opcode;
if rx = '0' then
nstate <= WAITBEGIN;
else
nstate <= state;
end if;
-- wait for first half of start bit
when WAITBEGIN =>
nbitcount <= 0;
nopcode <= opcode;
if counter = BITLENGTH / 2 then
ncounter <= 0;
nstate <= READBYTE;
else
if trxClock = '1' then
else
end if;
nstate <= state;
end if;
-- receive byte
when READBYTE =>
if counter = BITLENGTH then
ncounter <= 0;
nbitcount <= bitcount + 1;
if bitcount = 8 then
nbytecount <= bytecount + 1;
nstate <= ANALYZE;
nopcode <= opcode;
else
if bytecount = 0 then
nopcode <= rx & opcode(7
downto 1);
else
nopcode <= opcode;
ndataBuf <= rx & dataBuf
(31 downto 1);
end if;
nstate <= state;
end if;
else
if trxClock = '1' then
else
end if;
nbitcount <= bitcount;
nopcode <= opcode;
nstate <= state;
end if;
-- check if long or short command has been fully receive
d
when ANALYZE =>
ncounter <= 0;
nbitcount <= 0;
nopcode <= opcode;
-- long command when 5 bytes have been received
if bytecount = 5 then
nstate <= READY;
-- short command when set flag not set
elsif opcode(7) = '0' then
nstate <= READY;
-- otherwise continue receiving
else
nstate <= WAITSTOP;
end if;
-- done, give 10 cycles for processing
when READY =>
nbitcount <= 0;
nbytecount <= 0;
nopcode <= opcode;
if counter = 10 then
nstate <= INIT;
else
nstate <= state;
end if;
end case;
end process;
-- set execute flag properly
process(state)
begin
if state = READY then
execute <= '1';
else
execute <= '0';
end if;
end process;
end Behavioral;
************************************
--------------------------------------------------------------------------------
--
-- rle_enc.vhd
--
--
--
--
--
--------------------------------------------------------------------------------
--
--
--
-- Run Length Encoder
--
-- If enabled, encode the incoming data with the following scheme:
-- The MSB (bit 31) is used as a flag for the encoding.
-- If the MSB is clear, the datum represents "regular" data
-- if set, the datum represents the number of repetitions of the previous data
--
--------------------------------------------------------------------------------
--
library IEEE;
entity rle_enc is
dataIn : in STD_LOGIC_VECTOR (31 downto 0);
validIn : in STD_LOGIC;
enable : in STD_LOGIC;
dataOut : out STD_LOGIC_VECTOR (31 downto 0);
validOut : out STD_LOGIC);
end rle_enc;
architecture Behavioral of rle_enc is
signal old: std_logic_vector(30 downto 0);
signal dout: std_logic_vector(31 downto 0);
signal ctr: std_logic_vector(30 downto 0);
signal valid, valout: std_logic;
begin
dataOut <= dataIn when (enable = '0') else dout;
validOut <= validIn when (enable = '0') else valout;
-- shift register
begin
if (reset = '1') then
valid <= '0';
if (validIn = '1') then
old <= dataIn(30 downto 0);
valid <= '1';
end if;
end if;
end process;
-- RLE encoder
begin
if (reset = '1') then
ctr <= (others => '0');
valout <= '0'; --default
if (enable = '0') then
ctr <= (others => '0');
elsif (valid = '1') AND (validIn = '1') then
if (old = dataIn(30 downto 0)) then
if (ctr = 0) then -- write first datum o
f series
dout <= '0' & dataIn(30 downto 0
); -- discard MSB, which is used for encoding a count
valout <= '1';
elsif (ctr = "11111111111111111111111111
1111") then -- ctr overflow
dout <= '1' & ctr; -- write
count
valout <= '1';
ctr <= (others => '0'); -- reset
count, so "series" starts again.
end if;
ctr <= ctr + 1;
else -- series complete, write count (or data, i
f series was 0 or 1 long)
valout <= '1';
ctr <= (others => '0');
if (ctr > 1) then -- TODO: try if /=0 AN
D /=1 is faster than >1
dout <= '1' & ctr;
else
dout <= '0' & old;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
******************************************
--------------------------------------------------------------------------------
--
-- sampler.vhd
--
--
--
--
--
--------------------------------------------------------------------------------
--
--
--
-- Produces samples from input applying a programmable divider to the clock.
-- Sampling rate can be calculated by:
--
-- r = f / (d + 1)
--
-- Where r is the sampling rate, f is the clock frequency and d is the value
-- programmed into the divider register.
--
-- As of version 0.6 sampling on an external clock is also supported. If externa
l
-- is set '1', the external clock will be used to sample data. (Divider is
-- ignored for this.)
--
--------------------------------------------------------------------------------
--
library IEEE;
entity sampler is
Port ( input : in STD_LOGIC_VECTOR (31 downto 0); -- 32 input channels
-- internal clock
-- external clock
external : in std_logic;
-- clock selection
data : in STD_LOGIC_VECTOR (23 downto 0); -- configuration
data
wrDivider : in STD_LOGIC;
-- write divider register
sample : out STD_LOGIC_VECTOR (31 downto 0); -- sampled data
ready : out STD_LOGIC;
-- new sample ready
ready50 : out std_logic);
-- low rate sample signal with 50% duty cycle
end sampler;
architecture Behavioral of sampler is
signal divider, counter : std_logic_vector (23 downto 0);
signal lastExClock, syncExClock : std_logic;
begin
-- sample data
process(clock)
begin
syncExClock <= exClock;
if wrDivider = '1' then
divider <= data(23 downto 0);
counter <= (others => '0');
ready <= '0';
elsif external = '1' then
if syncExClock = '0' and lastExClock = '1' then
-- sample <= input(31 downto 10) & exClock
& lastExClock & input(7 downto 0);
ready <= '1';
else
sample <= input;
ready <= '0';
end if;
lastExClock <= syncExClock;
elsif counter = divider then
sample <= input;
counter <= (others => '0');
ready <= '1';
else
ready <= '0';
end if;
end if;
end process;
-- generate ready50 50% duty cycle sample signal
process(clock)
begin
if counter = divider then
ready50 <= '1';
elsif counter(22 downto 0) = divider(23 downto 1) then
ready50 <= '0';
end if;
end if;
end process;
end Behavioral;
**********************************
--------------------------------------------------------------------------------
--
-- sram.vhd
--
--
--
--
--
--------------------------------------------------------------------------------
--
--
--
-- Simple SRAM interface.
--
--------------------------------------------------------------------------------
--
library IEEE;
entity sram is
Port (
read : in std_logic;
write : in std_logic;
);
end sram;
architecture Behavioral of sram is
signal address : std_logic_vector (17 downto 0);
begin
-- static memory configuration
ramCE1 <= not '1';
ramUB1 <= not '1';
ramLB1 <= not '1';
ramCE2 <= not '1';
ramUB2 <= not '1';
ramLB2 <= not '1';
-- assign signals
ramA <= address;
ramWE <= not write;
ramOE <= not (not write);
output <= ramIO2 & ramIO1;
-- memory io interface state controller
process(write, input)
begin
if write = '1' then
ramIO1 <= input(15 downto 0);
ramIO2 <= input(31 downto 16);
else
ramIO1 <= (others => 'Z');
ramIO2 <= (others => 'Z');
end if;
end process;
-- memory address controller
process(clock)
begin
if write = '1' then
address <= address + 1;
elsif read = '1' then
address <= address - 1;
end if;
end if;
end process;
end Behavioral;
*******************************
--------------------------------------------------------------------------------
--
-- sram_bram.vhd
--
--
--
--
--
--------------------------------------------------------------------------------
--
--
--
-- Simple BlockRAM interface.
--
-- This module should be used instead of sram.vhd if no external SRAM is present
.
-- Instead, it will use internal BlockRAM (16 Blocks).
--
--------------------------------------------------------------------------------
--
library IEEE;
entity sram_bram is
GENERIC
(
ADDRESS_WIDTH : integer := 13
);
Port (
read : in std_logic;
write : in std_logic
);
end sram_bram;
architecture Behavioral of sram_bram is
signal address : std_logic_vector (ADDRESS_WIDTH - 1 downto 0);
signal bramIn, bramOut : std_logic_vector (31 downto 0);
COMPONENT BRAM8k32bit--SampleRAM
PORT(
WE : IN std_logic;
DIN : IN std_logic_vector(31 downto 0);
ADDR : IN std_logic_vector(ADDRESS_WIDTH - 1 downto 0);
DOUT : OUT std_logic_vector(31 downto 0);
CLK : IN std_logic
);
END COMPONENT;
begin
-- assign signals
output <= bramOut;
-- memory io interface state controller
bramIn <= input;
-- memory address controller
process(clock)
begin
if write = '1' then
address <= address + 1;
elsif read = '1' then
address <= address - 1;
end if;
end if;
end process;
-- sample block ram
Inst_SampleRAM: BRAM8k32bit PORT MAP(
ADDR => address,
DIN => bramIn,
WE => write,
CLK => clock,
DOUT => bramOut
);
end Behavioral;
**********************************
--------------------------------------------------------------------------------
--
-- stage.vhd
--
--
--
--
--
--------------------------------------------------------------------------------
--
--
--
-- Programmable 32 channel trigger stage. It can operate in serial
-- and parallel mode. In serial mode any of the input channels
-- can be used as input for the 32bit shift register. Comparison
-- is done using the value and mask registers on the input in
-- parallel mode and on the shift register in serial mode.
-- If armed and 'level' has reached the configured minimum value,
-- the stage will start to check for a match.
-- The match and run output signal delay can be configured.
-- The stage will disarm itself after a match occured or when reset is set.
--
-- The stage supports "high speed demux" operation in serial and parallel
-- mode. (Lower and upper 16 channels contain a 16bit sample each.)
--
-- Matching is done using a pipeline. This should not increase the minimum
-- time needed between two dependend trigger stage matches, because the
-- dependence is evaluated in the last pipeline step.
-- It does however increase the delay for the capturing process, but this
-- can easily be software compensated. (By adjusting the before/after ratio.)
--------------------------------------------------------------------------------
--
library IEEE;
entity stage is
wrMask : in STD_LOGIC;
wrValue : in STD_LOGIC;
wrConfig : in STD_LOGIC;
arm : in std_logic;
level : in STD_LOGIC_VECTOR (1 downto 0);
run : out STD_LOGIC;
match : out STD_LOGIC
);
end stage;
architecture Behavioral of stage is
type STATES is (OFF, ARMED, MATCHED);
signal maskRegister, valueRegister, configRegister : STD_LOGIC_VECTOR (31 downt
o 0);
signal intermediateRegister, shiftRegister : STD_LOGIC_VECTOR (31 downto 0);
signal testValue: STD_LOGIC_VECTOR (31 downto 0);
signal cfgStart, cfgSerial : std_logic;
signal cfgChannel : std_logic_vector(4 downto 0);
signal cfgLevel : std_logic_vector(1 downto 0);
signal counter, cfgDelay : std_logic_vector(15 downto 0);
signal matchL16, matchH16, match32Register : STD_LOGIC;
signal state : STATES;
signal serialChannelL16, serialChannelH16 : std_logic;
begin
-- assign configuration bits to more meaningful signal names
cfgStart <= configRegister(27);
cfgSerial <= configRegister(26);
cfgChannel <= configRegister(24 downto 20);
cfgLevel <= configRegister(17 downto 16);
cfgDelay <= configRegister(15 downto 0);
-- use shift register or input depending on configuration
testValue <= shiftRegister when cfgSerial = '1' else input;
-- apply mask and value and create a additional pipeline step
process(clock)
begin
intermediateRegister <= (testValue xor valueRegister) an
d maskRegister;
end if;
end process;
-- match upper and lower word separately
matchL16 <= '1' when intermediateRegister(15 downto 0) = "00000000000000
00" else '0';
matchH16 <= '1' when intermediateRegister(31 downto 16) = "0000000000000
000" else '0';
-- in demux mode only one half must match, in normal mode both words mus
t match
process(clock)
begin
if demuxed = '1' then
match32Register <= matchL16 or matchH16;
else
match32Register <= matchL16 and matchH16;
end if;
end if;
end process;
-- select serial channel based on cfgChannel
process(input, cfgChannel)
begin
for i in 0 to 15 loop
if conv_integer(cfgChannel(3 downto 0)) = i then
serialChannelL16 <= input(i);
serialChannelH16 <= input(i + 16);
end if;
end loop;
end process;
-- shift in bit from selected channel whenever input is ready
process(clock)
begin
if demuxed = '1' then -- in demux mode two bits
come in per sample
shiftRegister <= shiftRegister(29 downto
0) & serialChannelH16 & serialChannelL16;
elsif cfgChannel(4) = '1' then
0) & serialChannelH16;
else
0) & serialChannelL16;
end if;
end if;
end if;
end process;
-- trigger state machine
begin
if reset = '1' then
state <= OFF;
run <= '0';
match <= '0';
case state is
when OFF =>
if arm = '1' then
state <= ARMED;
end if;
when ARMED =>
if match32Register = '1' and level >= cf
gLevel then
counter <= cfgDelay;
state <= MATCHED;
end if;
when MATCHED =>
if counter = "0000000000000000"
then
run <= cfgStart;
match <= not cfgStart;
state <= OFF;
else
counter <= counter - 1;
end if;
end if;
end case;
end if;
end process;
-- handle mask, value & config register write requests
process(clock)
begin
if wrMask = '1' then
maskRegister <= data;
end if;
if wrValue = '1' then
valueRegister <= data;
end if;
if wrConfig = '1' then
configRegister <= data;
end if;
end if;
end process;
end Behavioral;
***********************************
--------------------------------------------------------------------------------
--
-- sync.vhd
--
--
--
--
--
--------------------------------------------------------------------------------
--
--
--
-- Synchronizes input with clock on rising or falling edge and does some
-- optional preprocessing. (Noise filter and demux.)
--
--------------------------------------------------------------------------------
--
library IEEE;
entity sync is
enableFilter : in STD_LOGIC;
enableDemux : in STD_LOGIC;
falling : in STD_LOGIC;
end sync;
architecture Behavioral of sync is
COMPONENT demux
PORT(
input180 : IN std_logic_vector(15 downto 0);
output : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT filter
PORT(
input180 : IN std_logic_vector(31 downto 0);
output : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
signal filteredInput, demuxedInput, synchronizedInput, synchronizedInput180: std
_logic_vector (31 downto 0);
begin
Inst_demux: demux PORT MAP(
input => synchronizedInput(15 downto 0),
input180 => synchronizedInput180(15 downto 0),
clock => clock,
output => demuxedInput
);
Inst_filter: filter PORT MAP(
input => synchronizedInput,
input180 => synchronizedInput180,
clock => clock,
output => filteredInput
);
-- synch input guarantees use of iob ff on spartan 3 (as filter and demu
x do)
process (clock)
begin
synchronizedInput <= input;
end if;
if falling_edge(clock) then
synchronizedInput180 <= input;
end if;
end process;
-- add another pipeline step for input selector to not decrease maximum
clock rate
process (clock)
begin
if enableDemux = '1' then
output <= demuxedInput;
else
if enableFilter = '1' then
output <= filteredInput;
else
if falling = '1' then
output <= synchronizedInput180;
else
output <= synchronizedInput;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
****************************************
--------------------------------------------------------------------------------
--
-- test_core_simple.vhd
--
--
--
--
--
--------------------------------------------------------------------------------
--
--
-- Details: http://sump.org/projects/analyzer/
--
-- Test bench for core.
-- Checks sampling with simple trigger.
--
--------------------------------------------------------------------------------
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY test_core_simple_vhd IS
END test_core_simple_vhd;
ARCHITECTURE behavior OF test_core_simple_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT core
PORT(
outputBusy : IN std_logic;
outputSend : OUT std_logic;
);
END COMPONENT;
--Inputs
SIGNAL clock : std_logic := '0';
SIGNAL extReset : std_logic := '0';
SIGNAL execute : std_logic := '0';
SIGNAL inputClock : std_logic := '0';
SIGNAL outputBusy : std_logic := '0';
SIGNAL cmd : std_logic_vector(39 downto 0) := (others=>'0');
SIGNAL input : std_logic_vector(31 downto 0) := (others=>'0');
SIGNAL memoryIn : std_logic_vector(31 downto 0) := (others=>'0');
--Outputs
SIGNAL sampleReady50 : std_logic;
SIGNAL output : std_logic_vector(31 downto 0);
SIGNAL outputSend : std_logic;
SIGNAL memoryOut : std_logic_vector(31 downto 0);
SIGNAL memoryRead : std_logic;
SIGNAL memoryWrite : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: core PORT MAP(
clock => clock,
extReset => extReset,
cmd => cmd,
execute => execute,
input => input,
inputClock => inputClock,
sampleReady50 => sampleReady50,
output => output,
outputSend => outputSend,
outputBusy => outputBusy,
memoryRead => memoryRead,
memoryWrite => memoryWrite
);
-- generate 100MHz clock
process
begin
clock <= not clock;
wait for 5 ns;
end process;
-- generate test pattern (counter) on input
process(clock)
begin
input <= input + 1;
end if;
end process;
-- simulate read out (one cycle busy after send)
process(clock)
begin
outputBusy <= outputSend;
end if;
end process;
-- perform test
process(clock)
variable state : integer := 0;
begin
execute <= '0';
state := state + 1;
case state is
when 4 => cmd <= x"0000000000"; execute <= '1';
-- reset
when 8 => cmd <= x"000000FFC0"; execute <= '1';
-- set trigger mask FF
when 12 => cmd <= x"00000052C1"; execute <= '1';
-- set trigger value 42
-- set trigger config (par, 0 delay)
when 34 => cmd <= x"0000005EC9"; execute <= '1';
when 38 => cmd <= x"00020000CA"; execute <= '1';
when 42 => cmd <= x"0000FFFFCC"; execute <= '1';
when 46 => cmd <= x"00000FF0CD"; execute <= '1';
when 50 => cmd <= x"0C330000CE"; execute <= '1';
-- set trigger config (ser, 0 delay)
-- set divider 0
-- issue set read & delay 2*4 & 1*4
-- set flags (default mode)
-- run
when others =>
end case;
end if;
end process;
END;
**********************************
--------------------------------------------------------------------------------
--
-- transmitter.vhd
--
--
--
--
--
--------------------------------------------------------------------------------
--
--
--
-- Takes 32bit (one sample) and sends it out on the serial port.
-- End of transmission is signalled by taking back the busy flag.
-- Supports xon/xoff flow control.
--
--------------------------------------------------------------------------------
--
library IEEE;
entity transmitter is
generic (
FREQ : integer;
RATE : integer
);
Port (
disabledGroups : in std_logic_vector (3 downto 0);
write : in std_logic;
id : in std_logic;
xon : in std_logic;
xoff : in std_logic;
tx : out STD_LOGIC;
busy: out std_logic
-- pause: out std_logic
);
end transmitter;
architecture Behavioral of transmitter is
type TX_STATES is (IDLE, SEND, POLL);
constant BITLENGTH : integer := FREQ / RATE;
signal dataBuffer : STD_LOGIC_VECTOR (31 downto 0);
signal disabledBuffer : std_logic_vector (3 downto 0);
signal txBuffer : std_logic_vector (9 downto 0) := "1000000000";
signal byte : std_logic_vector (7 downto 0);
signal counter : integer range 0 to BITLENGTH;
signal bits : integer range 0 to 10;
signal bytes : integer range 0 to 4;
signal state : TX_STATES;
signal paused, writeByte, byteDone, disabled : std_logic;
begin
-- pause <= paused;
tx <= txBuffer(0);
-- sends one byte
process(clock)
begin
if writeByte = '1' then
counter <= 0;
bits <= 0;
byteDone <= disabled;
txBuffer <= '1' & byte & "0";
elsif counter = BITLENGTH then
counter <= 0;
txBuffer <= '1' & txBuffer(9 downto 1);
if bits = 10 then
byteDone <= '1';
else
bits <= bits + 1;
end if;
elsif trxClock = '1' then
end if;
end if;
end process;
-- control mechanism for sending a 32 bit word
begin
if reset = '1' then
writeByte <= '0';
state <= IDLE;
dataBuffer <= (others => '0');
disabledBuffer <= (others => '0');
if (state /= IDLE) or (write = '1') or (paused = '1') th
en
busy <= '1';
else
busy <= '0';
end if;
case state is
-- when write is '1', data will be available wit
h next cycle
when IDLE =>
if write = '1' then
dataBuffer <= data;
disabledBuffer <= disabledGroups
;
state <= SEND;
bytes <= 0;
elsif id = '1' then
dataBuffer <= x"534c4131";
disabledBuffer <= "0000";
state <= SEND;
bytes <= 0;
end if;
when SEND =>
if bytes = 4 then
state <= IDLE;
else
bytes <= bytes + 1;
case bytes is
when 0 =>
byte <= dataBuff
er(7 downto 0);
disabled <= disa
bledBuffer(0);
when 1 =>
byte <= dataBuff
er(15 downto 8);
disabled <= disa
bledBuffer(1);
when 2 =>
byte <= dataBuff
er(23 downto 16);
disabled <= disa
bledBuffer(2);
when others =>
byte <= dataBuff
er(31 downto 24);
disabled <= disa
bledBuffer(3);
end case;
writeByte <= '1';
state <= POLL;
end if;
when POLL =>
writeByte <= '0';
if byteDone = '1' and writeByte = '0' an
d paused = '0' then
state <= SEND;
end if;
end case;
end if;
end process;
-- set paused mode according to xon/xoff commands
begin
if reset = '1' then
paused <= '0';
if xon = '1' then
paused <= '0';
elsif xoff = '1' then
paused <= '1';
end if;
end if;
end process;
end Behavioral;
***************************************
--------------------------------------------------------------------------------
--
-- trigger.vhd
--
--
--
--
--
--------------------------------------------------------------------------------
--
--
--
-- Complex 4 stage 32 channel trigger.
--
-- All commands are passed on to the stages. This file only maintains
-- the global trigger level and it outputs the run condition if it is set
-- by any of the stages.
--
--------------------------------------------------------------------------------
--
library IEEE;
entity trigger is
wrMask : in STD_LOGIC_VECTOR (3 downto 0);
wrValue : in STD_LOGIC_VECTOR (3 downto 0);
wrConfig : in STD_LOGIC_VECTOR (3 downto 0);
arm : in STD_LOGIC;
run : out STD_LOGIC
);
end trigger;
architecture Behavioral of trigger is
COMPONENT stage
PORT(
inputReady : IN std_logic;
wrMask : IN std_logic;
wrValue : IN std_logic;
wrConfig : IN std_logic;
arm : IN std_logic;
level : in std_logic_vector(1 downto 0);
demuxed : IN std_logic;
run : OUT std_logic;
match : OUT std_logic
);
END COMPONENT;
signal stageRun, stageMatch: std_logic_vector(3 downto 0);
signal levelReg : std_logic_vector(1 downto 0);
begin
-- create stages
stages: for i in 0 to 3 generate
Inst_stage: stage PORT MAP(
input => input,
inputReady => inputReady,
data => data,
clock => clock,
reset => reset,
wrMask => wrMask(i),
wrValue => wrValue(i),
wrConfig => wrConfig(i),
arm => arm,
level => levelReg,
demuxed => demuxed,
run => stageRun(i),
match => stageMatch(i)
);
end generate;
-- increase level on match
process(clock, arm)
variable tmp : std_logic;
begin
if arm = '1' then
levelReg <= "00";
tmp := stageMatch(0);
tmp := tmp or stageMatch(i);
end loop;
if tmp = '1' then
levelReg <= levelReg + 1;
end if;
end if;
end process;
-- if any of the stages set run, capturing starts
process(stageRun)
variable tmp : std_logic;
begin
tmp := stageRun(0);
tmp := tmp or stageRun(i);
end loop;
run <= tmp;
end process;
end Behavioral;

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--------------------------------------------------------------------------------

BlockRAMS: for i in 0 to 15 generate

NET "xtalClock" TNM_NET = "xtalClock";

NET "xtalClock" TNM_NET = "xtalClock";

signal cmd : std_logic_vector (39 downto 0);

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