Intro to System Generator

This material exempt per Department of Commerce license exception TSU © 2007 Xilinx, Inc. All Rights Reserved

Objectives
After completing this module, you will be able to:
• Explain why there is a need for an integrated flow from system design
to implementation
• Describe System Generator and the tools with which it interfaces

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 Outline
• Introduction
• System Generator Design Flow
• Summary

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MATLAB
• The MathWorks MATLAB provides a
technical computing environment that
facilitates rapid exploration of mathematical
solutions to systems problems
– Extensive libraries for math functions, signal
processing, DSP, communications, and
much more
– Visualization: Large array of functions to
plot and visualize your data and system and
design

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 Simulink
Visual data flow tool

• The MathWorks Simulink provides a model-

based design environment for the
development of executable specs of dynamic
systems
– Fully integrated with the MATLAB engine
– Graphical block editor
– Event-driven simulator
– Models parallelism
– Extensive library of parameterizable functions
• Simulink blockset: math, sinks, and sources
• DSP blockset: filters or transforms, for
example
• Communications blockset: modulation or
DPCM, for example

Intro to System Generator - 02 - 6 © 2006 Xilinx, Inc. All Rights Reserved

Overview of System
Generator for DSP
• The industry’s system-level design environment (IDE) for FPGAs
– Integrated design flow from the Simulink software to the BIT file
– Leverages existing technologies
• MATLAB , Simulink
• HDL synthesis
• IP Core libraries
• FPGA implementation tools
• Simulink library of arithmetic, logic operators, and DSP functions (Xilinx
blockset)
– BIT and cycle-true to FPGA implementation
• Arithmetic abstraction
– Arbitrary precision fixed-point, including quantization and overflow
– Simulation of double precision as well as fixed point

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 Overview of System
Generator for DSP
• VHDL and Verilog code generation for Virtex™- 5, Virtex-4, Virtex-II Pro,
Virtex-II, Virtex-E, Virtex, Spartan™-3E, Spartan-3, Spartan-IIE, and
Spartan-II devices
– Hardware expansion and mapping
– Synthesizable VHDL and Verilog with model hierarchy preservation
– Mixed-language support for VHDL/Verilog
– Automatic invocation of the CORE Generator software to utilize IP cores
– ISE project generation to simplify the design flow
– HDL testbench and test vector generation
– Constraint file (XCF), simulation DO file generation
– HDL co-simulation via HDL C-simulation
• Verification acceleration by using hardware-in-the-loop through Parallel
Cable IV, Platform Cable USB, and Network-based as well as Point-to-
Point Ethernet connections
Intro to System Generator - 02 - 8 © 2006 Xilinx, Inc. All Rights Reserved

System Generator for DSP

Platform Designs

ISIM

Intro to System Generator - 02 - 9 © 2006 Xilinx, Inc. All Rights Reserved

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 Outline
• Introduction
• System Generator Design Flow
• Summary

Intro to System Generator - 02 - 10 © 2006 Xilinx, Inc. All Rights Reserved

Model Based Design using

System Generator
• Develop an executable spec
using Simulink

• Refine the hardware

algorithm using System
generator
– Verify hardware against
executable spec

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 The SysGen Design Flow
Develop
Executable Spec
in Simulink

System
Generator
Develop System
Generator
Xilinx DSP representation
Blockset

Automatic RTL Testbench

generation Generation
Xilinx CoreGen

RTL
RTL Verification
Xilinx with ModelSim
Implementation
Flow
Bitstream

Download to
FPGA

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SysGen-Based Design Flow

Simulink Verification
MATLAB/Simulink
HDL
System Generator System Verification

Synthesis Functional Simulation

Implementation Timing Simulation

Download In-Circuit Verification

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 SysGen-Based Design Flow
HDL-CoSim Verification
MATLAB/Simulink
Files Used
HDL
System Generator System Verification • Configuration file
• HDL
• IP
• Constraints File
Synthesis Functional Simulation

HDL Co-Simulation*
Implementation Timing Simulation

Download In-Circuit Verification

* ModelSim helper block not needed when ISIM simulator is used

Intro to System Generator - 02 - 14 © 2006 Xilinx, Inc. All Rights Reserved

SysGen-Based Design Flow

HWIL Verification
MATLAB/Simulink
Files Used
HDL • Configuration file
System Generator System Verification
• HDL
• IP
• Constraints File
Synthesis Functional Simulation
HWIL Co-Simulation

Implementation Timing Simulation

Download In-Circuit Verification

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 Outline
• Introduction
• System Generator Design
Flow
• Summary

Intro to System Generator - 02 - 16 © 2006 Xilinx, Inc. All Rights Reserved

Knowledge Check

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 Knowledge Check
• Describe System Generator and the tools with which it interfaces

• Describe how System Generator helps in DSP System Design

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Answers
• Describe System Generator and the tools with which it interfaces
– System Generator is a toolbox running under the Simulink environment.
This toolbox provides an integrated design flow by leveraging existing
technologies, such as HDL synthesis, IP Core libraries, and FPGA
implementation tools

• Describe how System Generator helps in DSP System Design

– It provides a simple push-button flow for design and development under
Simulink environment and provides HDL co-simulation and hardware-in-the-
loop acceleration verification capability

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 Summary
• Traditional system design using Simulink left gap between system
designer and FPGA designer
• System Generator toolbox fills that gap so a system designer can design
a DSP system in FPGA
• System Generator uses Simulink toolbox, Xilinx HDL synthesis, IP Core
libraries, and FPGA implementation tools

Intro to System Generator - 02 - 20 © 2006 Xilinx, Inc. All Rights Reserved

Where Can I Learn More?

• Software documentation
– Simulink Browser → Help → Simulink Help → Xilinx System Generator
• Hardware Design Using System Generator → Design Flows Using System
Generator
• Hardware Design Using System Generator → System Level Modeling
• Hardware Design Using System Generator → Automatic Code Generation
• Support Website
– DSP Website: http://www.xilinx.com/dsp

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 Where Can I Learn More?
• Answer Record database: Search by FPGA family or software tool
– www.xilinx.com/support → Answer Browser (under Support Quicklinks)
• www.xilinx.com/xlnx/xil_ans_browser.jsp

Note for instructor: Take a moment to click the link above and browse through the
Records.

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