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11. Design a fully complementary single bit full adder using minimum
number of transistors. Using this adder , explain how do you
construct an adder/ subtractor circuit.
12. Design a CMOS single bit full adder. Using this adder ,explain how
do you construct a magnitude comparator circuit.
16. What are the 3 types of switch –level RC delay models developed to
estimate the delays of logic gates? Explain riefly with example.
18. Design a CMOS inverter for which the inverter threshold is half the
Vdd and have equal rise time(tr) and fall time(tf).
22. How do you automate the complex logic gates layout? Explain this
algorithm, with examples, which uses Euler path.
23. a) Explain with an example, dynamic CMOS logic. What are the
advantages and drawbacks of a simple dynamic CMOS logic?