SRAM Cell & Array

Spring 2007

Semiconductor Memories
 Outline
„ Basic SRAM Cell and Operation
„ Type of SRAM Cells
„ Scaling in SRAM Technology
„ Advanced SRAM Technology
„ Race between 4T and 6T

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 Read-Write Memories (RAM)
‰ STATIC (SRAM)
Data stored as long as supply is applied
Large (6 transistors/cell)
Fast
Differential
‰ DYNAMIC (DRAM)
Periodic refresh required
Small (1-3 transistors/cell)
Slower
Single Ended

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 Introduction
„ A SRAM is a matrix of static, volatile memory cells
and address decoding functions to allow access to
each cell for read and write operations
„ Use positive feedback in form of cross-coupled
inverters to store logic data in “one” or ‘zero” state.
„ The active elements in a memory cell require a
constant power source to remain latched in the
desired state.
„ The basic SRAM Cell made up of cross-coupled
inverter has several variations with tradeoffs between
cell size, noise immunity and standby power.
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 6-transistor CMOS SRAM Cell

WL

V DD
M2 M4
Q
M5 Q M6

M1 M3

BL BL

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 CMOS SRAM Analysis (Read)
WL

V DD
BL M4
BL
Q= 0
Q= 1 M6
M5

V DD M1 V DD V DD

Cbit Cbit

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 CMOS SRAM Analysis (Read)
1.2
1
Voltage Rise (V)

0.8
0.6
0.4
0.2
V o l t a g e r i s e [ V ]

0
0 0.5 1 1.2 1.5 2 2.5 3
Cell Ratio (CR)

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 CMOS SRAM Analysis (Write)
WL
V DD
M4

Q= 0 M6
M5 Q= 1

M1
V DD
BL = 1 BL = 0

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 CMOS SRAM Analysis (Write)

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 6T-SRAM — Layout
VDD
M2 M4

Q Q
M1 M3

GND
M5 M6 WL

BL BL

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 Resistance-load SRAM Cell
WL
V DD
RL RL

Q Q
M3 M4

BL M1 M2 BL

Static power dissipation -- Want R L large

Bit lines precharged to V DD to address t p problem

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 SRAM Characteristics

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 General SRAM Schematic
„ The load devices can be depletion mode transistors or
PMOS transistor or resistors.

Write Sequence

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 Data Storage in SRAM Storage
„ Basic six-transistor SRAM
cell and its layout
„ Logic “1” when T1 is off and
T2 is on, C5 is at Vdd,C6 is at
Vss
„ Logic “0” when T3 is off and
T4 is on, C5 is at Vss ,C6 is at
Vdd
„ When the wordline is
selected, T5 and T6 is on and
the level stored in C5 and C6
are passed to the bitlines

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 6-T SRAM Operation Scheme
„ Read operation:
… B and B-bar are set to high
… At state “1, T1 is off and T2 is on
… When wordline is selected, T5 and T6 is
on, C2 is then pull down by discharging
through T6 and T2.
… B-bar is then lower then B, the
differential signal between the two
bitlines is detected by the sense
amplifier.
„ Write Operation:
… Data are place in B and B-bar lines
… When the wordline is raised, causing
the cell to flip into the desired state

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 CMOS SRAM Cell
„ CMOS 6-T Cell
… Larger cell size
… Lower standby leakage current ~ nA
… Better Static Noise Margin

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 N-SRAM with Depletion-Load
‰ Smaller cell size, no n-well needed
‰ Higher standby leakage current ~ µA Depletion-mode NMOS

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 Resistor-Load SRAM Cell
„ Smaller Cell area Cell Schematics
… No n-well and pMOSFET
… Poly resistors lay on top of other
transistors
… No contact to join n+, p+ diffusion
„ Issues
… High resistance needed for low
static current
… Typical RL=1GΩ
Write Sequence
… Current in 1MB SRAM @ 3V
„ I=1M*3V/1GΩ=3mA

… Cell high node time constant

„ T=RL*C=1G*10fF=10µsec

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 Poly PMOS Load Cell
„ Features
… Standby leakage < pA
… R~80MΩ
… Cell high node time
constant ~0.8µsec

p+ poly / n+ poly diode

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 Comparison of Various Cells
„ In CMOS SRAM cell,
there is essentially no
current flow through the
cell except during
switching
„ The depletion load and
resistive load have a non-
zero static current, hence
the standby power
dissipation is always
higher than that of a
CMOS cell
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„ R-load cell with poly-silicon
resistors allows up at a 30%
reduction in cell size in double
poly-silicon technology using
buried contacts.
„ R-load NMOS SRAM cell
combined with CMOS
peripheral circuits allowed the
benefit of lower standby
power consumption while
retaining a smaller chip area
of NMOS SRAMs.
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 Memory Scaling Trend

Density increase as a result of line width reduction, novel cell size,

enhance process technology and circuit innovations
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 SRAM Technology Evolution

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 1st Gen. 1Mb SRAM Technology

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 Scaling Parameters in SRAM

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 Cell Design Considerations
„ Cell ratio = driver transistor current/ access transistor
current
„ Cell ratio↑⇒ Static Noise Margin↓
„ Access transistor current↓ ⇒ Static Noise Margin↑ ⇒
read time↓
„ At same cell ratio
… Access transistor current ↑ ⇒ read speed ↑ ⇒
driver transistor size ↑ ⇒ cell size ↑
„ Storage node capacitance design
… As technology scales, VDD ↓, CS ↓, QS ↓, more
vulnerable to soft error induced by alpha particles
… Increased CS can be improve SER

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 Scaling of R-load SRAM
„ Polysilicon load resistors are commonly used in
< 1Mb SRAM designs
„ R-load cell are hard to design to achieve both
high density and low power
„ Small cell size limit the sized of the polyresistors
„ The standby power on the other hand set a
minimum value of the load resistor
Density↑⇒ Cell size ↓ ⇒ Resistor size ↓ ⇒ Standby leakage ↑

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 Noise Margins for Full CMOS and
R-load Cells

Bitline Voltage (V) Supply Voltage (V)

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1MB Poly-load SRAM Cell Layout

Features
2P2M Process
Cell size 6x11µm2
Poly1: Vss, gates
Poly2: R-load and Vdd
M1: bitlines
M2: wordlines

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 High-Valued Poly-Si Load
Resistor
„ To minimize power consumption and maintain an
optimum soft-rate, load current is set at about 30pA
„ R ↑ ⇒ Standby Power ↓ ⇒ SER ↑
Memory Feature VDD Load Standby RL L/W of R† Tpoly
size size (V) current current (GΩ) RL (GΩ/†) (nm)
(µm) (pA) (µA)
256k 1.2 5 30 8 164 4/1.2 47 70

1M 0.8 3 30 33 97 3/0.8 26 50

4M 0.5 3 30 130 97 2/0.5 24 30

16M 0.25 1.5 30 520 48 1/0.25 12 30

Silicon Processing For The VLSI ERA – Vol II

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 Poly-Resistor Engineering
„ To maintain small cell size, high sheet resistance poly-
film must be used.
„ The resistor are normally formed by poly2 layer.
„ The remainder of the layer ( not for high resistive poly ) is
implanted with a much higher dose so form ohmic
contact or served as interconnect path.

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 Poly-Resistor Engineering
„ Undoped polysilicon film with implant doses from 1x1013 to 1x1015/cm2 can
from 104Ω/† to 1012Ω/†
„ Adjacent higher-doped regions can significantly alter the resistance value
if lateral diffusion take place over a large enough fraction of the resistor

Oxygen implant to reduce lateral diffusion

Tpoly ↓ & Memories

Semiconductor Implant dose↓⇒ R ↑
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 Cell Layout Comparison

Depletion-Mode Load Single Poly Memory Double Poly Memory

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 Layout of Full CMOS Cells

Single Aluminum Interconnect Double Aluminum Interconnect

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 Buried Contact Schemes

Layout Rules

Cross-sectional View : Connection of Diffusion and Poly-layer

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 Butting
Contact

metal

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 Shared Contact Using Poly2
Allows Further Reduction of SRAM Cell Size

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 Area Reduction by Local TiN
Interconnect

TiN

Conventional TiN Interconnect

Cell Size : 160F2 Cell Size : 120F2
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 TiN Local Interconnect in SRAM

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 Titanium Silicide Process

„ Titanium Deposition
„ Ti/Si Reaction &
Nitridation of Ti
„ Interconnect
Patterning
„ Etch TiN
„ TiN/TiSi2 Annealing

Advantage: Better compatibility with CMOS process

Problem: TiN has lower conductivity
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 Advanced CMOS Cell Layout
‡ Reduce Contact Number by location interconnects
‡ Silicide straps to connect poly-line and diffused region
‡ 1P2M Process; Cell size 5x12µm2

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 The Race Between 4T and 6T
„ Major tradeoffs in SRAM
design: size & process
complexity
„ 4T cells dominates the
stand-alone SRAM market
due to its small size
„ 6T cells are typically used in
on-chip storage is MPUs
„ 4T cells
… Smaller
… Complex process
… Poor stability at low VDD Simple 6T: basic logic process
Advanced 6T: self-aligned contact,
local interconnect

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Ref: IEDM 1996 – p.271 2007/4/29
 Estimated Processing Cost
Comparison
„ A more complex process
can still produce a
cheaper product when
the increase number of
die can compensate for
the increase wafer cost
„ The reason why all
manufacturers are
pushing for smaller cell
size

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 SRAM Cell Comparison
„ SAC : self-aligned contact are used in both 4T and 6T
cells to reduce cell size

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 SNM Comparison
„ 6T cells have much better stability, especially at low supply
voltage
„ Better SNM in 6T allows for low cell ratio, β, allows for
smaller size

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 Enhanced 4T
Designs
„ Resistor using LDD region
increase SNR without increase
cell ratio
„ Boosted WL improves read
current and and SNM
„ TFT load improve cell stability
and reduce SER
„ Diode inherited in the cell need to
be optimized to improved on
current
„ Supply voltage > 1.8 can still
provide reasonable SNM
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 Summary
„ 4T SRAM enjoys smaller size but the supply
voltage cannot be scaled too low
„ 6T SRAM allows for low supply voltage and
provide better SNR
„ Further enhancement in process and device
structure can further scaled the SRAM cell for
high density memories

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