One Cycle Control Design for High Performance Two-Level Power Inverters

Carlos Ferreira134, Beatriz Borges24, Luís de Sá34

1
Instituto Politécnico de Tomar, Estrada da Serra, Quinta do Contador, 2300-313 Tomar, Portugal
Phone: +351- 249328100, Fax: +351- 249 328 186, e-mail: cferreira@ipt.pt
2 3 4
Instituto Superior Técnico, Universidade de Coimbra, Instituto de Telecomunicações

Abstract — Constant frequency One Cycle Control (OCC), as The input voltage is a DC voltage, vG, the converter is
proposed by Smedley [1], is a powerful method for controlling formed by the switch, S and the diode, D. The inductor, L,
switching power converters. The dimensioning of this control composes an LC low pass filter in conjunction with capacitor
method is not of common knowledge and as far as the authors C. Let us consider that the converter operates with a constant
know, has not yet been published for two level AC output PWM frequency, in continuous conduction mode and with an
converters. This paper describes OCC for two level switched output voltage vO. 1
power converters. Its instability problems and solutions are The output voltage is the sum of the switched voltage
analysed and dimensioning equations are deducted. This average and the ripple voltage at the switching frequency, fs.
technique allows the construction of stable high bandwidth Considering the duty-cycle δ as the relation between the on
power converters with low output THD and high PSRR. The time of the switch, ton, and Ts, the switched voltage average in
obtained analytical expressions are compared with experimental a switched cycle is:
results, showing good correlation. T δTs
1 s 1
I. INTRODUCTION
vS Ts
= ∫
Ts 0
v S dt =
Ts ∫v
0
G dt. (1)

Pulse Width Modulation (PWM) is traditionally used in To achieve the desired average output voltage, a circuit to
constant frequency power supply’s converters. The typical control ton is needed.
switched AC output converter consists in a modulator that Considering that at the start of the analysis the switch is
converts the input signal into a PWM signal (by comparison turned on, then the control system only has to provide the
to a saw tooth or triangular wave), a bridge or half bridge instant when the switch has to be turned off (ton). The
power converter configuration and a low pass filter to objective is to attain an average value proportional to the
“demodulate” the output signal. reference vREF, as expressed in equation (2):
To achieve sufficient PSRR and low THD of the output t on
1
signal a linear negative feedback loop is often used. In order
to assure system stability, linearised models have to be Ts ∫v
0
G dt = v REF . (2)

studied and the system “tuned”. This limits the improvements

achieved on PSRR, output impedance, THD, gain flatness,
bandwidth, etc. So it is highly desirable to have a general
control method, like OCC, that allows the construction of
stable high bandwidth power converters with low output THD
and high PSRR [2].
II. ONE CYCLE CONTROL
The OCC basic concept is to “force” the average value of vS
to be exactly equal to the reference value in each switching
cycle; it does that by integrating the output voltage and
comparing it to the reference voltage. Fig. 2 presents the OCC
concept applied to a real implementation of the Fig. 1
converter (considering an integrator with unitary time
constant) [1].

A. Unipolar OCC
OCC principle is very simple. The aim of the control system
is to attain an average output level proportional to the
reference signal, OCC performs this control action in each
switching period, Ts.
Let us consider the buck converter represented in Fig. 1.

Fig. 2. Buck converter with OCC control.

1
Acknowledgement: the present work is partially supported by the
FCT (Fundação para a Ciência e Tecnologia) by the
Fig. 1. Buck converter. SFRH/BD/40330/2007 contract.
 Fig. 3. OCC signals. Fig. 4. OCC signals in a Fig. 5. OCC applied to a half-
non-ideal system. bridge converter.

The OCC signals are represented in Fig. 3. In order to Table I

assure constant frequency operation an external clock is
needed. The leading edge of the clock signal initiates the
Interval
system by setting (S) a Set-Reset Flip-Flop (FF) which forces
the transistor to turn on. [t0, t1]
The vS voltage equals the vG value and the integrator output
voltage starts growing. When it reaches the reference voltage,
the comparator (CMP) resets (R) the FF, turning off the
switching transistor and resetting the integrator.
Turning off the transistor forces the diode to conduct, and [t1, t2]
vS becomes zero (ideally) until a new clock pulse reinitiates
the system. This type of control assures the law expressed in
equation (2).
In practical non-ideal systems, voltage drops in the
transistor and diode or vG voltage variations are compensated
by adjusting transistor’s ton, as represented in 4. This
compensation is also valid for any other perturbations in the
converter, namely switching times delays or transients.
An important characteristic of OCC derives from the fact [t2, t3]
that the integrator reset’s at the beginning of each control
cycle, preventing the transmission of information between
consecutive cycles and leading to an inherently stable system
[3]. In traditional linear negative feedback, information
transmission between successive cycles provokes delays in
the feedback path, leaving to possible oscillation which does
not happen with OCC (when the output filter is not
considered) [2].
Bipolar OCC event sequence
Description
At the leading edge of the clock signal the FF is set.
The FF output actuates the driver input, provoking Q2
actuation (on) and Q1 cut (off).
vS voltage is -vG2, the output’s integrator voltage
starts growing.
Output’s integrator voltage reaches -vREF, provoking
comparator’s output transition to high logic level:
“1”.
The comparator’s output transition causes the FF to
reset, making the driver to turn Q1 on and Q2 off.
Simultaneously the integrator’s output voltage is
resetted.
vS voltage is vG1, the output’s integrator voltage starts
decreasing.
In the leading edge of the clock the FF is set and the
cycle continues…

B. Bipolar One Cycle Control

In the aforementioned circuit the output voltage is unipolar
and could only take values between 0 and vG.
The circuit represented in Fig. 5 is an extension of the OCC
circuit to a half-bridge converter that allows bipolar output
voltage swing [4]. The integrator with reset is made with an
Operational Amplifier and a reset switch. The driver block
commands the transistor’s state based on the FF output. Table
I describes the operating sequence of events and Fig. 6 the Fig. 6. Typical waveforms of the bipolar OCC circuit.
typical produced waveforms.
 Fig.7. Integrator’s error propagation. Fig. 8. Compensated waveforms. Fig. 9. Compensated OCC circuit.

The control law could be represented as: In the general half-bridge or full-bridge inverters vG1 and
t3 vG2 are equal, implying that m1=m2. Like this, the perturbation
vS ∆vn will not disappear and there will be an oscillation at half
∫ R C dt = v
t1 i i
REF . (3)
the switching frequency.
If an offset voltage, vOS, is added to the integrator’s input to
If fs is much higher than the maximum frequency of the null m2, the error propagation ends. To achieve this condition
signal to reproduce, vREF, it could be concluded that between the added voltage has to be -vG1. Fig 8 illustrates the obtained
two successive switching periods the reference signal is waveforms, showing that in this situation the ∆v1 perturbation
almost constant, being similar in the intervals [t0, t1] and [t2, disappears in one switching cycle [4].
t3], and also in [t1, t2] and [t3, t4]. The control law is now:
vS
 vS 
t3
The vS average in Ts, Ts , could be represented by: vOS
1
t2
1
Ts ∫  R C −
Ros1C i
dt = v REF .

(7)
= ∫ v S dt =
Ts ∫0
t1 i i
vS Ts
v S dt. (4)
Ts t 0 In order to obtain an output switching average voltage
vS proportional to vREF a parcel has to be added to vREF to null
The circuit gain, G, is the relation between Ts and the vOS contribution. Fig. 9 shows a way to do that by using a
vREF , accordingly to equations (3) and (4) it will be: resistance network. We must now design the system such that
T vOS disappears in equation (7).
1 s
Ts ∫0
v S dt C. Design
vS
= = Ri C i f s = G.
Ts
T
(5) We consider the circuit represented in Fig. 9, where the
v REF 1 s voltages vG1 and vG2 are equal (being represented by vG) and
Ri C i ∫0
v S dt
for the sake of simplicity, vG=–vOS. To avoid error
transmission between successive cycles, Ri and Ros1 values
Although the OCC controlled unipolar circuit have to be equal.
aforementioned in section A is inherently stable, the bipolar By using the superposition theorem, the voltage at the input
circuit has some stability issues. of the comparator, vCMP, due to vINTt, vREF and vOS can be
Fig. 7 shows the time evolution of the integrator’s voltage calculated by summing its several contributions:
when it is exposed to a disturbing signal, ∆v1 [4]. Two vINT contribution:
distinct situations are analysed: in the first case vG1 e vG2 are Rref Ros 2
equal, meaning that the integrators output voltage slope (m1 vINT
Rref + Ros 2
and m2) are equal (disregarding its signal); if vG1>vG2, then vCMP1 = ⇔ vCOMP1 = β1vINT ; (8)
Rref Ros 2
m1>m2. + Rint
By analysing Fig. 7 it could be seen that the error Rref + Ros 2
propagation depends on the integrator’s voltage slope: m1 and vREF contribution:
m2 [4]. For t=nTs, the propagated error due to ∆v1, ∆vn, is:
Rint Ros 2
vREF
m Rint + Ros 2
∆v n = (− 2 ) n −1 ∆v1 . (6) vCMP 2 =
Rint Ros 2
⇔ vCOMP 2 = β 2 vREF ; (9)
m1 + Rref
Rint + Ros 2
 vOS contribution:
III. EXPERIMENTAL RESULTS
Rint Rref
vOS A switching converter in half bridge configuration was built
Rint + Rref
vCMP 3 = ⇔ vCOMP 3 = β 3vOS ; (10) using an IR2110 driver and IRFB41N15D transistors, ±vG
Rint Rref
+ Ros 2 =±32V, fs=333kHz and a low pass filter at the output. The
Rint + Rref
OCC components were designed by means of the deducted
The sum of the three contributions gives: equations, giving a theoretical gain of 18.79 (due to the
vCMP = β 1v INT + β 2 v REF + β 3 vOS . (11)
available component values).
Fig. 10 a) shows the measured experimental OCC signals.
The OCC analysis is initiated at t=0. We designate toff as the The experimental diagrams are referred (from top) to: clock
instant when vS switches from vG to -vG, which coincides with signal, vS, vINT and vO. Fig. 10 b) shows vREF and vO at 10kHz
time when the input voltage of the comparator reaches zero. input frequency and allows us to calculate a practical gain of
Also, as referred before, vG=–vOS and equation (7) becomes: 18.9, very close to the predicted value. The measured THD is
0 = β 1v INT + β 2 v REF − β 3 vG . (12)
always lower then 0.5% (1W, 20-20kHz, 8Ω load).

Considering that vG2 is constant (with vG2=vG1=vG) and

disregarding the voltage drops in the transistor, the vINT
voltage at the toff will be:
t off
1 2v G 2v
v INT =
Ci ∫
0
Ri
dt = G t off .
Ri C i
(13)

Representing toff as a function of δ:

toff = Ts − ton a) b)

 ton ⇔ toff = Ts − δTs = Ts (1 − δ ). (14) Fig. 10 a) OCC signals, b) Filtered output signal.
δ = T
 s
IV. CONCLUSIONS
Equation (13) then becomes:
This paper introduces the OCC control target at converters
2vG
v INT = (1 − δ ). (15) capable of producing unipolar and bipolar output voltages,
Ri C i f s operating with two level switching output. The design
By substitution of this value in equation (12), we obtain: equations, for the bipolar case, have been deducted based on
the superposition theorem applied to the OCC circuit. A
β1vG
0= (1 + 1 − 2δ ) + β 2 v REF − β 3 v G . (16) prototype has been built using the design method developed
Ri C i f s in this paper. Experimental data is in accordance with the
For an half-bridge the relation between vO and vG is: design, showing that this technique allows the construction of
stable high performance converters. Also, the design
vO=(2δ-1)vG. Substituting this value in equation (16) gives:
procedure proved to be simpler then the linear feedback case.
 βv βv 
0 =  1 G − 1 O  + β 2 v REF − β 3 v G . (17)
 R i C i f s Ri C i f s  REFERENCES
To avoid a DC component in the output due to vG, the [1] Keyue M. Smedley, Slobodan Cuk, “One-Cycle Control
following two solutions are possible: of Switching Converters”, IEEE Transactions on Power
Electronics, vol. 10, no. 6, pp. 625-633, Nov. 1995.
vG = 0 ∨ β 1 = β 3 Ri C i f s . (18)
[2] C. C. Chan, Zheng Ming Zhao, C. Qian, S. Meng,
The vG=0 solution is not relevant. The other solution is a “Comparisons of PWM and One-Cycle Control for
circuit dimensioning equation. Power Amplifier With Multilevel Converter”, IEEE
Using (18) equation (17) becomes: Trans. on Industrial Electronics, vol. 49, no. 6, pp. 1342–
β 1vO 1344, Dec. 2002.
0 = β 2 v REF − . (19)
Ri C i f s [3] Zongbo Hu, Bo Zhang, Weihua Deng, “Feasibility Study
on One Cycle Control for PWM Switched Converters”,
This conduces to another design equation, corresponding to
IEEE Power Electronics Specialists Conference, vol. 5,
the circuit gain, G:
pp. 3359–3365, Jun. 2004.
vO β RC f
= 2 i i s = G. (20) [4] Zheren Lai, Keyue M. Smedley, “A New Extension of
v REF β1 One-Cycle Control and Its Application to Switching
Power Amplifiers”, IEEE APEC, pp. 826-831, 1995.