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WS Wong
System Engineer
SSTL interface
The SSTL topology of DDR memo-
Figure 3: The power source of VTT needs both sink current and source current.
ry is shown in Figure 2. The inter-
face of SSTL_2 has the following
DRAM modules. These include tion, DDR3 uses 16 percent less them especially suitable for use in features:
handheld game consoles, smart power than DDR2. Both DDR2 notebook computers, servers and • DDR memory has a push-pull
phones, digital cameras and GPS and DDR3 devices have power- low-power mobile applications. output buffer, while the input
devices. In these applications, saving features such as smaller In summary, the main dif- receiver is a differential stage
power consumption needs to be page sizes and an active power ferences between SDRAM and requiring a reference bias
kept as low as possible to increase down mode. Furthermore, DDR DDR SDRAM are found in power midpoint, VREF. Therefore, it
battery runtime. memory interfaces use the stub supply voltage, interface and requires an input voltage ter-
series-termination-logic (SSTL) data transfer frequency. The DDR mination capable of sourcing
The difference topology, which improves noise SDRAM system requires three as well as sinking current.
The main differences between immunity, increases power-sup- power supply voltage sources: • Between any output buffer
DDR1, DDR2 and DDR3 standards ply rejection and reduces power VDDQ, VTT and VREF, as shown in from the driving chipset and
for SDRAM are shown in Table dissipation due to a lower-volt- Table 2. the corresponding input re-
1. Notice that DDR1, DDR2 and age rail. One more point worth These three types of power ceiver on the memory module,
DDR3 are powered up with sup- noting is that DDR3 and DDR2 supply voltage are needed be- we must terminate a routing
ply voltages of 2.5-, 1.8- and 1.5V SDRAM support On-Die Termina- cause while DDR technology trace or stub with resistors.
respectively. This is less than the tion, which is not supported by doubles the data-transfer rate
supply voltage of 3.3V required DDR1. These features and power without doubling the clock rate The current flow direction of
by SDRAM chipsets. In addi- consumption advantages make and while avoiding PCB design the VTT power source changes
5V or 3.3V
VDDQ
VREF
MC34716
VTT
Terminal
Terminal resistance for the resistance
address bus control signal is … built-in for data
needed basically even bus (ODT)
with DDR2
ODT
…
Figure 4: VTT for the data bus is generated within the memory via ODT (on-die termination) by VDDQ.