PDCLab Manual

Pulse and Digital Circuits Lab MANUAL ONLY FOR REFERENCE
Experiment No:1
LINEAR WAVE SHAPING
AIM : a) To observe the response of RC Low pass circuit for a square wave input for
different time constants
i) RC>>T ii) RC = T iii) RC<<T
and to determine rise time for RC<<T.
b) To observe the response of RC High pass circuit for a square input for
different time constants
i) RC>>T ii) RC = T iii) RC<<T
and to determine percentage tilt for RC = T .
Components Required :
1. Resistors - 10k? , 100 k? , 1M?
2. Capacitor - 0.01? F
Apparatus Required :
1. Bread Board.
2. CRO (1Hz- 20MHz)
3. Function Generator(1Hz-1MHz)
4. Connecting Wires.
THEORY:
LINEAR WAVE SHAPING
The process where by the form of a non-sinusoidal signal is altered by
transmission through a linear network is called “LINEAR WAVE SHAPING”.
a) RC Low Pass Circuit :

The resistor in series arm and capacitor in the shunt arm, The resulting circuit is
called Low pass circuit
R
Vi C V0
Figure 1: RC Low Pass Circuit.
The circuit passes low frequencies readily but attenuates high frequencies because the
reactance of the capacitor decreases with increasing frequency. At very high frequencies the
capacitor acts as a virtual short circuit and the output falls to zero. This circuit also works as
integrating circuit. A circuit in which the output voltage is proportional to the integral of the
input voltage is known as integrating circuit. The condition for integrating circuit is RC value
must be much greater than the time period of the input wave (RC>>T)
Let Vi = alternating input voltage.

1
i = resulting current
Applying Kirchoff’s Voltage Law to RC low pass circuit (fig.1).
T
1
C ?o
Vi ? iR ? i.dt
Multiplying throughout by C, we get
T
CVi ? iRC ? ?i.dt
o
T
As RC >> T, the term ?i.dt may be neglected
o
? CVi ? iRC
Integrating with respect to T on both sides, we get

T T
?CVi .dt ? RC ?i.dt

0 0
T t
1 1
C0?i.dt ?
RC ?0
Vi .dt
T
1
C ?0
V0 ? i.dt
t
1
RC ?0
? V0 ? Vi .dt
The output voltage is proportional to the integral of the input voltage.
EXPECTED GRAPH:
Vi
(0.9)V0
(0.1)V0 RC<T
t
tr
RC>>T
V0
t
V0
RC=T
0
2
3
b) High Pass Circuit.

The Capacitor in series arm and resistor in the shunt arm, the resulting circuit is called
High pass circuit
C
Vi R V0
Figure: 2. RC High Pass Circuit.
The higher frequency components in the input signal appears at the output with less
attenuation than the lower frequency components because the reactance of the capacitor
decreases with increase in frequency. This circuit works as a differential circuit. A circuit in
which the output voltage is proportional to the derivative of the input voltage is known as
differential circuit. The condition for differential circuit is RC value must be much smaller then
the time period of the input wave (RC<<T).
Applying Kirchoff’s Voltage Law to RC high pass circuit (fig.2)
T
1
C ?o
Vi ? i.dt ? iR .
Divide throughout by R
T
Vi 1
R RC ?o
? i.dt ? i .
As RC << T, the above equation is modified as
T
Vi 1
R RC ?o
? i.dt
Differentiating above equation with respect to T.
1 d 1
Vi ? .i
R dt RC
d
RC Vi ? iR
dt
V0 ? iR
4
d d
Therefore V0 ? RC Vi . V0 ? Vi
dt dt
EXPECTED GRAPHS:
Vi
V0 V1
V11
V RC=T
t
V0
RC<<T
t
V00
V
V1 RC>>T
DESIGN:
1. Choose T = 1msec.
2. Select C = 0.01 ? F.
3. For RC = T; select R.
4. For RC >> T; select R.
5. For RC << T; select R.
6. If RC << T, the High pass circuit works as a differentiator.
7. If RC >> T, the Low pass circuit works as an integrator.
PROCEDURE:
1. Connect the circuit as shown in the figure1 &2.

2. Connect the function generator at the input terminals and CRO at the output
terminals of the circuit.
3. Apply a square wave signal of frequency 1KHz at the input. (T = 1 msec.)
4. Observe the output waveform of the circuit for different time constants.
5. Calculate the rise time for low pass filter and tilt for high pass filter and compare
with the theoretical values.
6. For low pass filter select rise time (tr) = 2.2 RC (theoretical). The rise time is
defined as the time taken by the output voltage to rise from 0.1 to 0.9 of its final
value.
7. % tilt = ( T/2RC ) ? 100 ( theoretical)
% tilt = [ ( V1 – V1? ) / ( V / 2 ) ] ? 100 ( practical)
5
QUESTIONS:
1. What is meant by linear wave shaping?
2. Derive the expression for the generalized single time constant transient of a series RC circuit?
3. Derive the expression for the Rise time and % of tilt?
CONCLUSION:
Low pass filter:
Conclusions can be made on theoretical and practical values of rise time and output
waveforms of the Linear wave shaping circuits are identical or not when compared with
the theoretical wave forms.
High pass filter:

Conclusions can be made on theoretical and practical values of % tilt and output
waveforms of the Linear wave shaping circuits are identical or not when compared with
the theoretical wave forms.
6
Experiment No:2
NON LINEAR WAVE SHAPING - CLIPPERS
AIM : To study the clipping circuits for different reference voltages and
to verify the responses.
Components Required:
1. Resistors - 1K?
2. IN4007 Diode – 2No.
1. Bread board.
2. CRO (1Hz- 20MHz)
3. Function Generator(1Hz-1MHz)
4. Power supply(0-30V)
5. Connecting wires.
THEORY:
The non-linear semiconductor diode in combination with resistor can function as clipper
circuit. Energy storage circuit components are not required in the basic process of clipping.
These circuits will select part of an arbitrary waveform which lies above or below some
particular reference voltage level and that selected part of the waveform is used for transmission.
So they are referred as voltage limiters, current limiters, amplitude selectors or slicers.
There are three different types of clipping circuits.

1) Positive Clipping circuit.
2) Negative Clipping.
3) Positive and Negative Clipping ( slicer ).
In positive clipping circuit positive cycle of Sinusoidal signal is clipped and negative
portion of sinusoidal signal is obtained in the output of reference voltage is added, instead of
complete positive cycle that portion of the positive cycle which is above the reference voltage
value is clipped.
In negative clipping circuit instead of positive portion of sinusoidal signal, negative

portion is clipped.
In slicer both positive and negative portions of the sinusoidal signal are clipped.
7
I. Positive Clipping 1 KO
Vi IN 4007 V0
Figure:1
Vi
V0
t V?
t
Figure: 2(a). Input waveform Figure: 2(b)Output waveform.
Vi is a input sinusoidal signal as shown in the figure 2(a) . For positive portion of the
sinusoidal the diode IN4007 gets forward biased. The output voltages in the voltage across the
diode under forward biased which is cut-in-voltage of the diode. Therefore the positive portion
above the cut-in-voltage is clipped or not observed in the output (V0) as shown in figure 2(b).
II. Positive Clipping with Positive Reference Voltage

1 KO
IN 4007
Vi V0
VR
Figure:3.
Vi V0
VR+ V?
t t
Figure:4(a). Input waveform Figure:4(b). Output waveform.
The input sinusoidal signal (Vi ) in figure 4(a) can make the diode to conduct when its
instantaneous value is greater than VR. Up to that voltage (VR) the diode is open circuited and the
output voltage is same as the input voltage. After that voltage (VR) the output voltage is VR plus
the cut-in-voltage (V? ) of the diode as shown in figure 4(b).
8
III. Positive Clipping with Negative Reference Voltage

1 KO
IN 4007
Vi V0
VR
Figure: 5.
V0
Vi t
V? -VR
t
Figure:6(a). Input waveform Figure:6(b) Output waveform.
In this circuit the diode conducts the output voltage is same as input voltage. The diode
conducts at a voltage less by VR from cut-in-voltage called as V? . For voltage less than V? , the
diode is open circuited and output is same as input voltage.
IV Negative Clipping Circuit

1 KO
Vi IN 4007 V0
Figure:7.
Vi
V0
t t
-V?
Figure:8 (a). Input waveform Figure:8 (b). Output waveform.
9
For this portion of the input sinusoidal signal (Vi) , the diode gets reverse biased and it is open.
Then the output voltage is same as input voltage. For the negative portion of the signal the diode
gets forward biased and the output voltage is the cut-in-voltage (-V? ) of the diode. Then the
input sinusoidal variation is not seen in the output. Therefore the negative portion of the input
sinusoidal signal (Vi) is clipped in the output signal ( V0 ).
V. Negative Clipping with Negative Reference Voltage
1 KO
IN 4007
Vi V0
VR
Figure:9
Vi V0
t t
-VR-V?
Figure:10(a). Input waveform. Figure:10(b) Output waveform.

In this circuit, the diode gets forward biased for the input sinusoidal voltage is less than
(–VR). For input voltage greater than (–VR), the diode is non-conducting and it is open. Then the
output voltage is same as input voltage.
VI. Negative Clipping with Positive Reference Voltage

1 KO
IN 4007
Vi V0
VR
Figure:11.
10
Vi V0
VR-V?
t
t
Figure:12(a) Input waveform Figure:12(b) Output waveform.
For input sinusoidal signal voltage less than VR, the diode is shorted and the output
voltage is fixed ar VR. For input sinusoidal voltage greater than VR the diode is reverse biased
and open circuited. Then the output voltage is same as input voltage.
VII. Slicer 1 KO
IN 4007 IN 4007
Vi V0
VR1 VR2
Figure:13.
V0
Vi
t V? +VR
t
V? -VR
Figure:14(a). Input waveform Figure14(b). Output waveform.
DESIGN:
1. For positive clipping at ‘V’volts reference select VR = V.
2. For negative clipping at ‘V’volts reference select VR = V.
3. For clipping at two independent levels at V1&V2 reference voltages select
VR1 = V1, VR2 = V2 and VR2 = VR1.
11
PROCEDURE:
1. Connect the circuit as shown in the figure 1.
3. Apply a sine wave signal of frequency 1KHz, Amplitude greater than the reference
voltage at the input and observe the output waveforms of the circuits.
4. Repeat the procedure for figure 3, 5, 7, 9, 11 and 13.
QUESTIONS:
1. What is a clipper? Describe (i) Positive clipper (ii) Biased clipper (iii) Combination
clipper.
2. Discuss the differences between shunt and series clipper.
CONCLUSION:
Conclusion can be made on theoretical and practical values of cut in voltage of diode and
also made on theoretical and practical output wave forms for different reference voltages
12
Experiment No:3
NON LINEAR WAVE SHAPING – CLAMPERS
AIM : To study the clampling circuits for different reference voltages and
to verify the responses.
1. Resistors - 1k?
2. IN4007 Diode
3. Capacitor -10? F
Apparatus Required:
1. Bread board
2. Function generator (1Hz – 1Mz)
3. CRO (1Hz- 20MHz)
4. Power supply (0-30V)
THEORY:
Clamping Circuit
“A clamping circuit is one that takes an input waveform and provides an output that is
a faithful replica of its shape but has one edge tightly clamped to the zero voltage reference
point”.
There are various types of Clamping circuits, which are mentioned below:
1. Positive Clamping Circuit.

2. Negative Clamping Circuit.
3. Positive Clamping with positive reference voltage.
4. Negative Clamping with positive reference voltage.
5. Positive Clamping with negative reference voltage.
6. Negative Clamping with negative reference voltage.
13
Negative Clamping Circuit

VA
+
+ -
C
Vi D V0
-
Figure:1
The input signal is a sinusoidal which begins at t=0. The capacitor C is charged at t = 0.
The waveform across the diode at various instant is studied.
During the first quarter cycle the input signal rises from zero to the maximum value Vm.
The diode being ideal, no forward voltage may appear across it. During this first quarter cycle
the capacitor voltage VA = Vi . The voltage across C rises sinusoidally, the capacitor is charged
through the series combination of the signal source and the diode. Throughout this first quarter
cycle the output V0 has remained zero. At the end of this quarter cycle there exists across the
capacitor a voltage VA = Vm.
After the first quarter cycle, the peak has been passed and the input signal begins to fall,
the voltage VA across the capacitor is no longer able to follow the input voltage. For in order to
do so, it would be required that the capacitor discharge, and because of the diode, such a
discharge is not possible. The capacitor remains charged to the voltage VA = Vm, and, after the
first quarter cycle the output is V0 = Vi – Vm. During succeeding cycles the positive excursion of
the signal just barely reaches zero. The diode need never again conduct, and the positive
extremity of the signal has been clamped to zero. The average value of the signal is –Vm.
Positive Clamping Circuit:

Vm
+ +
+ -
C
Vi D V0
- -
Figure:2
It is also called as negative peak clamper, because this circuit clamps at the negative
peaks of a signal.
Let the input signal be Vi = Vm sin? t. When Vi goes negative, diode gets forward biased
and conducts. The capacitor charges to voltage Vm, with polarity as shown. Under steady state
condition, the positive clamping circuit is given as,
14
V0 ? Vi ? (? V m )
V0 ? Vi ? V m Eq.1
During the negative half cycle of Vi, the diode conducts and C charges to –Vm volts, i.e.,
the negative peak value. The capacitor cannot discharge since the diode cannot conduct in the
reverse direction. Thus the capacitor acts as a battery of –Vm volts and the output voltage is given
by equation.1 above. It is seen for figure 2, that the negative peaks of the input signal are
clamped to zero level. Peak-to-peak amplitude of output voltage 2Vm, which is the same as that
of the input signal.
Negative Clamping with Positive Reference Voltage
C
D
Vi V0
VR
Figure:2
Since VR is in series with the output of negative clamping circuit, now the average value of the
output becomes (-Vm + VR ).
Similarly, the average of

i) Negative clamping with negative reference voltage is (-Vm + VR ).
ii) Positive clamping is +Vm.
iii) Positive clamping with positive reference voltage is V m + VR.
iv) Positive clamping with negative reference voltage is Vm - VR.
Clamping Circuit Theorem:
It states that for any input waveform the ratio of the areas under the output voltage curve
in forward direction to that in the reverse direction is equal to the ratio (Rf / R).
Af R f
? .
Ar R
Where Af = area of the output wave in forward direction.
Ar = area of the output wave in reverse direction.
Rf and R are forward and reverse resistances of the diode.
15
I. Negative Clamping
10? F
C
1 KO
Vi D R V0
IN 4007
Figure:3
Vi V0
Vm
t t
-Vm
-2Vm
Figure:4 (a).Input waveform Figure:4 (b) Output waveform.
II. Negative Clamping with Positive Reference Voltage.

10? F
C
D
Vi IN 4007 R V0
1 KO
VR
Figure:5
Vi V0
VR
t t
16
III. Negative Clamping with Negative Reference Voltage.

10? F
C
D
Vi IN 4007 R V0
1 KO
VR
Figure:7
Vi V0
t t
-VR
IV. Positive Clamping.

10? F
C
1 KO
Vi D R V0
IN 4007
figure:9
2Vm
Vi
Vm V0
t t
-Vm
17
18
V. Positive Clamping with Negative Reference Voltage.

10? F
C
D
Vi IN 4007 R V0
1 KO
VR
Figure: 11
-VR
Vi V0
t t
VI. Positive Clamping with Positive reference Voltage.

10? F
C
D
Vi IN 4007 R V0
1 KO
VR
Figure: 13
Vi
t V0
VR
t
19
PROCEDURE:
3. Apply a sine wave greater than the reference voltage, and signal of frequency 1kHz at
the input and observe the output waveforms of the circuits in CRO.
4. Repeat the above procedure for the different circuit diagram as shown inf figure 5, 7,
9, 11 and 13.
QUESTIONS:
1. Explain the operation of a clamping circuit for a square wave input.
2. Differentiate the clippers with clampers.
3. Give the applications of clampers.
CONCLUSION:
Conclusion can be made on theoretical and practical values of cutin voltages of diode
and also conclude on theoretical and practical output wave forms for different reference
voltages
20
21
22
Experiment No:4
TRANSISTOR AS A SWITCH
AIM : To design and observe the performance of a transistor as a switch.
1. Resistors
2. LED
3. 2N2369 Transistor
1. Bread board
2. Function generator 1Hz- 1MHz 1No.
3. CRO 1Hz -20MHz 1No.
4. Power supply 0-30V 1No.
THEORY:
C
IB IC
Q RL
RB
B
VBB
IE VCC
E
Figure:1 Figure:2
I
VCC Saturation
IB > IB(sat)
RL
IB = IB(sat)
Cut-off
IB =0
0 VC VCE
Figure:3
Fig.1. Transistor as a switch. Fig.2 Pin configuration of transistor 2N2369.

Fig.3 Output characteristics with load line(d.c)
The transistor Q can be used as a switch to connect and disconnect the load RL from the
source VCC. When a transistor is saturated , it is like a closed switch from the collector to the
emitter. When a transistor is cut-off, it is like an open switch.
23
VCC ? VCE
I C?
RL
VCE ? VCC
Cut-off and Saturation : The point at which the load line intersects the IB = 0 curve is known
as cut-off. At this point, base current is zero and collector current is negligible small i.e., only
leakage current ICEO exists. At cut-off, the emitter diode comes out of forward bias and normal
transistor action is lost.
VCE(sat) ˜ VCC
The intersection of the loadline and the IB = IB(sat) is called saturation. At this point base
current is IB(sat) and the collector current is maximum. At saturation, the collector diode comes
out of reverse bias, and normal transistor action is again lost.
VCC
I C ( sat ) ?
RL
In figure:3 IB(sat) represents the amount of base current that just produces saturation. If
base current is less than IB(sat), the transistor operates in the active region somewhere between
saturation and cut-off. If base current is greater than IB(sat), the collector current approximately
V
equals CC . The transistor appears like a closed switch.
RC
V BB ? V BE ? I B R B
V ? V BE
I B ? BB .
RB
If base current (IB) is zero, the transistor operates at the lower end of the loadline and the
transistor appears like an open switch.
CIRCUIT DIAGRAM: VCC +12V
RC
IC
RB 2N2369
IB
1KO
0 or 5 V LED
Pin Configuration 2N2369 Figure 4.
DESIGN :
24
Ic max = 5mA, VBE = 0.7V,VCE (sat) = 0.2V,Vcc = 12V.

Rc min= VCC / Ic max
ICS = (VCC – VCE (sat) ) / Rc
IB = ICS/ hfe=(Vi -VBE)/RB
RB = ( Vi – VBE ) / IB
PROCEDURE :

2. Connect 12V power supply to VCC and 0V to the input terminals.
3. Measure the voltage (1) across collector – to – emitter terminals, (2) across collector
– to – base terminals and (3) Base – to – emitter terminals.
4. Connect 5V to the input terminals.
5. Measure the voltage (1) across collector – to – emitter terminals, (2) across collector
– to – base terminals and (3) Base – to – emitter terminals.
6. Observe that the LED glows when the input terminals are supplied with 0 volts. The
LED will NOT glow when the input voltage is 5V.
7. Remove the load (1K? and LED ) and DC power supply(connected between RB and
Gnd.). Now connect a function generator to the input terminals.
8. Apply Square wave of 1Khz, V(p-p) is 10V
9. Observe the waveforms at the input terminals and across collector and ground.
10. Plot the waveform on a graph sheet. Note the inversion of the signal from input to
output.
EXPECTED WAVE FORMS:
Input
Vi > VBE
V0 V CC Output
V CE (SAT) t
OBSERVATIONS:
VBE VCE VCB

When transistor is ON
When transistor is OFF
25
QUESTIONS:
1. Discuss the advantages of an electronic switch over a mechanical or electro

mechanical switch.
2. What is a switching circuit?
3. Explain the terms collector leakage current and saturation collector current.
CONCLUSION:
Conclusions can made on what are the conditions required to operate the transistor as a
switch and also made on junction voltages of the transistor when it is ‘ON’and ‘OFF’
also conclude what happens if we apply high voltage to the transistor.
26
Experiment No:5
STUDY OF LOGIC GATES
AIM : To study the various logic gates by using discrete components.
Component Required :
1. Resistors - 1k? -1, 10 k? -2

2. IN4007 Diodes – 2 no
3. Transistor 2N2369
Apparatus Required:
1. Power supply 0-30V

2. Bread board
3. Connecting wires
4. Multimeter
THEORY:
TRUTH TABLE
A B Y
A 0 0 0
Y=A.B
B 0 1 0
SYMBOL 1 0 0
1 1 1
AND GATE:
The AND gate as a high output when all the inputs are high the figure 1 shows
one way to build the AND gate by using diodes.
Case 1: When both A and B are low then the diodes are in the saturation region then the supply
from VCC will flow to the diodes then the output is low.
Case 2: When A is low and B is high then diode D1 will be in the saturation region and D2 will
be in the Cut-off region, then the supply from VCC will flow through diode D1 then the
output will be low.
Case 3: When A is high, B is low the diode D1 will be in the Cut-off region and diode D2 will be
in saturation region then the supply from VCC will flow through the diode D2, therefore
the output will be low.
Case 4: When both the A and B are high then the two diodes will be in Cut-off region therefore
the supply from VCC will flow through Vout then Vout is high.
27
OR GATE:
TRUTH TABLE
A B Y
A 0 0 0
Y=A+B
B 0 1 1
SYMBOL 1 0 1
1 1 1
An OR gate has two or more inputs but only one output signal. It is called OR gate
because the output voltage is high if any or all the inputs are high.
The figure 2 shows one way to build OR gate (two inputs) by using diodes.
Case 1: When A and B are low then the two diodes D1 and D2 are in Cut-off region. Then the
Vout is low.
Case 2: When A is low and B is high then the diode D1 is in Cut-off region and diode D2 is in
saturation region, then the Vout is high.
Case 3: When A is high and B is low then the diode D2 is in saturation region and diode D1 is in
Cut-off region, then the Vout is high.
Case 4: When both A and B are high the diodes D1 and D2 are in saturation region then the
output Vout is high.
NOR GATE:
TRUTH TABLE
A B Y
A
Y=A+B Y ? A? B
0 0 1
B
0 1 0
1 0 0
A 1 1 0
Y ? A? B
B
Symbol
NOR gate is referred to a NOT OR gate because the output is Y ? A ? B . Read this as Y
= NOT A OR B or Y = compliment of the A OR B. the circuit is in an OR gate followed by a
NO gate OR inverter. The only to get high output is to have both inputs low.
28
NAND GATE:
TRUTH TABLE
A
Y = A.B Y ? A.B
A B Y
B
0 0 1
0 1 1
A 1 0 1
Y ? A.B
B 1 1 0
Symbol
NAND gate is referred to as NOT AND GATE because the output is Y ? A.B read this as Y =
NOT A AND B or Y = Compliment of A AND B. By this gate the output is low when all the
inputs are high.
NOT GATE:
TRUTH TABLE
A Y
A Y= A 0 1
Symbol 1 0
The Inverter or NOT gate is with only one input and only one output. It is called inverter
because the output is always opposite to the input.
The figure5 shows the one way to build inverter circuit by using transistor (CE mode)
when the Vin is low then the transistor will be in the Cut-off region. Then the supply from VCC
will flow to Vout. Then the Vout is high. When Vin is high then the transistor is in the saturation
region then the supply from VCC will flow through the transistor to the ground, then the Vout is
low.
CIRCUIT DIAGRAM :
D1 IN4007
D1 IN4007
A Y
A Y
10KO
B 10KO
B
D2 IN4007
D2 IN4007
AND GATE
Vcc+5v OR GATE
Figure 1 Figure 2
29
Vcc+5v
10KO
Y
D1 IN4007 1KO
A 2N2369
10KO
B
D2 IN4007
NOR GATE
Figure 3
VCC +5V
10KO
10KO
Y
D1 IN4007
A 2N2369
1KO
B
D2 IN4007
NAND GATE
Figure 4
Vcc+5v
10KO
Y
1KO
A 2N2369 NOT GATE
Figure 5
30
PROCEDURE:
1. Connect the circuit as shown in figure 1
2. Apply ‘0v’to logic ‘0’and 5V to logic ‘1’using power supply.
3. Verify the truth tables of various gates for different conditions of inputs.
4. Repeat the steps 1&2 for figures 2, 3, 4 & 5.
TRUTH TABLES
AND GATE OR GATE NAND GATE NOR GATE NOT GATE

A B Y A B Y A B Y A B Y A Y
0 0 0 0 0 0 0 0 0
0 1 0 1 0 1 0 1
1 0 1 0 1 0 1 0 1
1 1 1 1 1 1 1 1
QUESTIONS:
1. Realize AND, OR, NOT gates using NAND & NOR gates
2. Why NAND & NOR gates are called universal gates.
CONCLUSION:
Conclusions can be made on theoretical and practical values of the truth tables for the
given logic gates
31
32
Experiment No:6
STUDY OF FLIP-FLOPS
AIM: To verify the truth table of SR latch, J-K flip-flop,J-K master Slave flip-
flop, T flip-flop and D flip-flop.
1. IC 74LS00
2. IC 74LS10
3. IC 74LS04.
4. Digital Trainer Kit.
THEORY:
RS FLOP-FLOP:
Consider the logic Symbol for RS flip-flop shown in Fig. Notice that the RS flip-flop has
two inputs, labeled S and R. The two outputs are labeled Q and Q . Note that the outputs are
always opposite, or complementary in the flip-flops.
Fig. shows the timing diagram for an RS flip-flop. Notice that the output Q goes high
whenever R goes low; and the output Q goes LOW whenever S goes LOW. The logic levels (0,
1) are on the left side of the wave forms. The output Q ‘holds’, whenever the both inputs are
high.
S S /R Q
FLIP-FLOP
R Q
Fig. Logic symbol for RS FLIP-FLOP
CLOCKED RS FLIP-FLOP (RST FLIP-FLOP):
We know that the flip-flops are synchronous bistable devices. The term synchronous
indicates that the output changes its state only at a specified point on a triggering input called the
‘clock’; i.e. changes in the output occur in synchronization with the clock.
By adding gates to the inputs of the basic circuit, the flip-flop can be made to respond to input
levels during the occurrence of a clock pulse. Note that the clock signal is a square wave signal
and the signal prevents the flip-flops from changing the states until the right time occurs. The
clocked RS flip-flop using NAND gates are shown in Fig.
33
SET S Q
CLOCK CLK
Q
RESET R
Fig. Logic symbol for clocked RS FLIP-FLOP
INPUTS OUTPUTS Mode of

operation
CLK R S Q Q
0 0 0
0 0 1
0 1 0 NO CHANGE HOLD
0 1 1
1 0 0
1 0 1 1 0 SET
1 1 0 0 1 RESET
1 1 1 Do not Use Prohibited
D (DELAY) FLIP-FLOP:
The D (Delay) flip-flop is used for storing the information. It is basically an RS
flip-flop with an inverter in the R input. Fig. shows a clocked D flip-flop. NAND gates 1 and 2
from a basic RS flip-flop and gates 3 and 4 modify it into a clocked RS flip-flop. The D input is
to the S input and its complement through gate 5 is applied to the R input. The D flip-flop is
often called a ‘delay flip-flop’. The word ‘delay’ describes what happens to the data or
information at input D. In other words, the data, i.e. 0 or 1 at the input D is delayed by one clock
pulse from getting to output Q.
D S Q
CLK
Q
R
Modification of clocked RS Flip-Flop into D Flip-Flop
Inputs Outputs
D Q CLK D Q Q
CLK 0 0
Q No change
0 1
Logic Symbol 1 0 0 1
1 1 1 0
34
Truth Table
JK FLIP-FLOP:
The JK flip-flop has the features of all other flip-flops, and hence it can also be
considered as ‘Universal’flip-flop. This JK flip-flop is a refinement of the RS flip-flop.
The indeterminate state (when R=S=1) of the RS type is defined in the JK type. In that condition
the state of the output is changed; i.e. the complement of the previous state is available. In other
words, if the previous state of the output Q is 0; it becomes 1; and vice versa. This can be written
as Qn ? 1 ? Qn .
The logic diagram of a clocked JK flip-flop is shown in Fig. Inputs J and K behave like
inputs S and R to set and reset the flip-flop. Note that in a JK flip-flop, the letter j is for set and
the letter K is for reset.
Fig. shows the logic symbol for JK flip-flop and it’s truth table is shown in the Fig. Note that the
RS flip-flop is converted into JK flip-flop by making S ? J ?Q and
R ? K ?Q
J Q
CLK
Q
K
Logic Symbol
Inputs Outputs
CLK J K Q Q
0 0 0
0 0 1 No Change
0 1 0
0 1 1 ( HOLD)
1 0 0
1 0 1 0 1
1 1 0 1 0
1 1 1 Toggle
35
J – K MASTER-SLAVE FLIP-FLOP:
In the operation of a JK flip-flop, it is very difficult to satisfy the requirements, which

should be fulfilled to avoid the ‘racing condition’, when both the data inputs are at High. The
practical approach to overcome this problem is to use ‘Master-slave JK flip-flop’. The Logic
diagram of a master-slave JK flip-flop is shown in Fig. which contains two clocked flop-flops.
One flip-flop serves as a MASTER and the other as a SLAVE; and overall circuit is known as
‘Master-Slave flip-flop’. Whenever the clock is HIGH, the master is active. According to the
state of the data inputs, The output of the master is set or reset. At this stage, the slave is inactive
and its output remains in the previous state. Whenever the input clock is LOW, then the master
is inactive and the slave is active. Note that final output of the master-slave flip-flop is the output
of the slave flip-flop. Hence the final output of the master-slave flip-flop is available at the end
of a clock pulse.
J
MASTER SLAVE Q
CLK
FLIP-FLOP FLIP-FLOP Q
K
CLK
LOGIC DIAGRAM OF MASTER-SLAVE

J-K FLIP-FLOP
T (TOGGLE) FLIP-FLOP:
The single input version of the JK flip-flop is ‘T (toggle) flip-flop’and it is obtained

from a JK flip-flop if both inputs are tied together. The name T comes from the ability of the
flip-flop to ‘toggle’or change the state. Generally T flip-flop IC’s are not available. It can be
realized using JK, SR, or D flip-flop.
Fig 1. shows the logic diagram of a clocked T flip-flop; which has only one input
referred to as T-input.
CLK I/P(T) O/P(Q)
T T Q
0 0 Qn
1 0 No change
CL 0 1 No change
K Q 1 1 Toggle
Fig 1.Logic Truth table

Symbol
36
CIRCUIT DIAGRAMS:
1 SR Latch
S 3 12
11 Q
2
13
Clk
10
4 8
6 Q
R 9 Flop
5 S – R Flip
3
4 6 Q
J
S – R Latch
5
9
10 8
K Q
11
J - K Flip Flop
DATA DATA
J Q S Q
Clk Clk
K Q R Q
T Flip flop D – Flip flip
37
7410 7400 7400

J 7400
Q
7400
7400 7400
K Q
MASTER SLAVE
7410
7400
CL
J-K MASTER-SLAVE FLIP-FLOP
PROCEDURE:
1. Connect the circuit diagram as shown in the diagram.

2. Verify the truth table of the SR latch.
3. Connect the JK flip-flop circuit using 3-input NAND gates and verify the truth table.
4. Verify the truth table for T and D Flip-flops.
5. Verify the truth table for J-K MASTER-SLAVE FLIP-FLOP
QUESTIONS:
1. What is a sequential logic circuit? How is it different from a combinational system?
2. What is a binary? What is a flip-flop?
3. Explain the meaning of set and reset?
4. Explain the need of flip-flop?
5. What basic purpose does all flip-flops serve?
6. Is it possible to toggle a SR flip-flop? Explain?
7. Explain the meaning of race – around problem? How does it affect the behavior of a flip-
flop?
8. Explain how the race – around problem is overcome in the JK Master Slave flip flop
9. Explain how a shift register can be constructed from SR flip-flop?
CONCLUSION:
given logic gates and also check whether all the gates are working or not .
38
Experiment No:7
SAMPLING GATES
AIM: To observe the output of the Unidirectional diode gate for different Control Input
Voltages
APPARATUS: 1. Resistors 1k? -2

2. Capacitor - 10? F
3. 1N4007 Diode
4. Bread board
5. CRO (1Hz-20MHz)
6. Function generator (1Hz-1MHz)- 2
THEORY:
Unidirectional Diode Gates:
At point A receives both the signal Vs and the control input Vc we observe here that
while the input signal Vs is capacitively connected to A, the control input Vc is directly coupled.
The net signal at point A can be determined by employing superposition theorem .A careful
inspection indicates that the input signal Vs is passing through a high pass filter and the control
input Vc is passing through a low pass filter to reach point A
It can be seen that the input to the sampling gates has a low duty cycle pulse train. The
width of the control pulse is large compared to input pulse width .The diode in the sampling
circuit is less reverse biased when the control input rises to its higher voltage level –V2.
However the diode is forward biased only during the narrow input signal Vs reaches point A.
The input pulse that lies with in the duration of the control pulse is transmitted through the
diode as output .The effect of the level –V2 on the output of the gate waveform can be seen in
fig 2 .In fig 2.a we have –V2 = -5V and for a 10V input pulse; a 5V pulse appears as output.
Operation in this manner is advantageous when the bottom line of the input signal has a noise
signal surrounding it This would enable us to choose a noise threshold appears at the output
.When used in this manner , the circuit is referred to as a threshold gate .In fig 2-b –V2 = 0 and
the entire input pulse is transmitted to the output , whereas in fig 2-c –V2 is positive and the
signal appears super imposed on a 5V pedestal
We have to remind the reader that the waveforms shown above are unrealistic as they do
not take the effects of the high pass filter and the low pass filter mentioned at the beginning of
this section .We are quite aware of the fact that R1C1 networks constitutes an integrator to the
control input Vc .As a consequence , the control input at A would be rising exponentially and
exponentially falling at a similar rate .The rates and fall are controlled by the time constant R1C1
The above discussion makes it clear that this form of a sampling gate is not particularly
suitable for selecting a portion of a continuous waveform .However when the input signal is a
short pulse whose duration is clearly smaller than the width of the control input , the
performance of the gate is acceptable .
39
C1
Signal
input
RL V0
R1
control
input
Fig.1 Unidirectional Diode Gate
Signal 15V
input 10V Output
Output Output Pedestal
5V -V2
0V - V2
-5V -V 2
-15V -V1
Gating
input
a) Output waveform when b) Output waveform when c) Output waveform when

–V2 is negative –V2 is zero –V2 is positive
Fig .2 Effect of control voltage on the output waveform
CIRCUIT DIAGRAM
C1
Signal
input
RL V0
R1
control
input
Unidirectional Diode Gate
40
Procedure:
1. Connect the circuit as shown in the circuit diagram.
2. Connect the signal generator at the signal input with a frequency of 10KHz , 10Vp-p .
3. Connect the another signal generator at the control input with a frequency of 1KHz ,
-10Vp-p .
4. Vary the control input voltage and observe the output for different control input voltages
say 0V, -5V & -10V
MODEL GRAPH:
Signal 15V
10V Output
input
Output Output Pedestal
5V -V2
0V -V2
-5V -V2
-15V -V1
Gating
input
a) Output waveform b) Output waveform c) Output waveform

when –V 2 is negative when –V2 is zero when –V2 is positive
Questions:
1. What is sampling gate?

2. Sketch the simple diode Unidirectional sampling gates that functions as a coincidence
gate
3. Write some applications of sampling gate?
4. Write short notes on four diode bi- directional diode sampling gate?
41
42
Experiment No:8
ASTABLE MULTIVIBRATOR
AIM : a) To design an Astable Multivibrator to generate clock pulse for a given

frequency and obtain the wave forms and test its performance.
COMPONENTS REQUIRED:
1. Resistors
2. Capacitors 0.1 ? f 2 No.s
3. Transistors 2N2369 2 No.s
APPARATUS :
1. CRO 1Hz-20MHz 1No.
2. Power supply 0-30V 1 No
3. Bread board
4. Connecting wires
THEORY:
An Astable multivibrator has two quasi-stable states, and it keeps on switching between
these two states, by itself, No external triggering signal is needed. The astable multivibrator
cannot remain indefinitely in any of these two states. The two amplifiers of an astable
multivibrator are regeneratively cross-coupled by capacitor.
Principle:
A collector-coupled astable multivibrator using n-p-n transistor in figure 1. The working
of an astable multivibrator can be studied with respect to the figure1.
VCC 12V
RC1 R2 R1 RC2
C D
C2 C1
Q1 Q2
2N2369 2N2369
A B
Figure:1
Let it be assumed that the multivibrator is already in action and is oscillating i.e.,
switching between the two states. Let it be further assumed that at the instant considered, Q2 is
ON and Q1 is OFF.
i) Since Q2 is ON, capacitor C2 charges through resistor RC1. The voltage across C2 is VCC.
43
ii) Capacitor C1discharges through resistor R1, the voltage across C1 when it is about to start
discharging is VCC.(Capacitor C1 gets charged to VCC when Q1 is ON).
As capacitor C1 discharges more and more, the potential of point A becomes more and
more positive (or less and less negative), and eventually VA becomes equal to V? , the cut in
voltage of Q1. For VA > V? , transistor Q1 starts conducting. When Q1 is ON Q2 becomes OFF.
Similar operations repeat when Q1 becomes ON and Q2 becomes OFF.
Thus with Q1 ON and Q2 OFF, capacitor C1 charges through resistor RC2 and capacitor
C2 discharges through resistor R2. As capacitor C2 discharges more and more , it is seen that the
potential of point B becomes less and less negative (or more and more positive), and eventually
VB becomes equal to V? , the cut in voltage of Q2. when VB > V? , transistor Q2 starts conducting.
When Q2 becomes On, Q1 becomes OFF.
It is thus seen that the circuit keeps on switching continuously between the two quasi-
stable states and once in operation, no external triggering is needed. Square wave voltage are
generated at the collector terminals of Q1 and Q2 i.e., at points C and D.
DESIGN:
IC max = 5 mA ; VCC = 12 V; VCE (SAT) = 0.2V

RC = (VCC - VCE(SAT)) / IC MAX
Let C = 0.1 ? f and R= 10K?
T = 0.69 (R1C1+R2C2) = 0.69(2RC) ? ( R1=R2 ; C1=C2)
=TON+TOFF
PROCEDURE:
1. Connect the circuit as shown in figure 1.

2. Observe the waveforms at VBE1, VBE2, VCE1, VCE2 and find frequency.
3. Vary C from 0.01 to 0.001? F and measure the frequency at each step.
4. Keep the DC- AC control of the Oscilloscope in DC mode.
44
EXPECTED WAVEFORMS:
Q1 OFF, Q2 ON Q1 OFF, Q2 ON
VCC
Q1 ON, Q2 OFF Q1 ON, Q2 OFF

VC1 V CE (SAT)
t
V CC
VC2 VCE (SAT)

t
VB1 V??
t
VB2 V??
t
I.R?C
Figure 2
OBSERVATIONS:
TON (Theoritical) = 0.69RC = TOFF (Theoritical) = 0.69RC =
T(TON + TOFF) (Theoritical) = 1.38RC =
TON (practical) = TOFF (practical) = T(TON + TOFF) (practical) =
QUESTIONS:
1. What is a switching circuit?

2. Justify that the Astable Multivibrator is a two stage RC coupled Amplifier using
negative feedback. How does it generate square wave.
3. What is the difference between a switching transistor and an ordinary transistor?
4. What is the effect of slew rate on the working of an Op-amp Multivibrator?
CONCLUSION:
Conclusion can be made on time period of the output waveforms of the Astable
multivibrator theoretically and practically and output waveforms of the multi vibrator are
identical or not when compared with the theoretical wave forms.
45
46
Experiment No:9
MONOSTABLE MULTIVIBRATOR
AIM : To design a monostable multivibrator to generate clock pulse for a given

frequency and obtain the waveforms and test its performance
1. Resistors
2. Capacitors.
3. Transistors 2N2369 2 No.s
Apparatus Required:
1. CRO 1Hz-20MHz 1 No.
2. Power supply 0-30V 1 No.
3. Bread board
4. Connecting wires
CIRCUIT DIAGRAM:
VCC = 6V
RC1 R=10KO RC2
R1
C=0.1? F
2N2369 Q1 Q2 2N2369
R2
-VBB -1.5V
Figure-1
THEORY :
‘A monostable multivibrator has only one stable state, the other state being quasi-
stable. Normally the multivibrator is in the stable state, and when an external triggering pulse is
applied, it switches from the stable to the quasi-stable state. It remains in the quasi-stable state
fro a short duration, but automatically reverts i.e. switches back to its original stable state,
without any triggering pulse’.
47
Principle of operation
A collector-coupled Monostable multivibrator of the two transistors Q1 and Q2, Q1 is
normally OFF and Q2 is Normally ON. Resistor R1 and R2 are connected to the normally OFF
transistor, and the capacitor C is connected to the normally ON transistor.
It is seen from the circuit of the monostable multivibrator that, under normal conditions,
the supply voltage VCC provides enough base drive to the transistor Q2 through resistor R, with
the result that Q2 goes into saturation. With Q2 ON, Q1 goes OFF, as already studied in the
context of binary operation.
With Q2 ON and Q1 OFF, the capacitor finds a charging path. The voltage across the
capacitor is VCC with polarity. It is obvious that in the stable state of the multivibrator, Q2 is ON
and Q1 is OFF.
If the negative triggering pulse is applied to the collector of Q1, it is transmitted to the
base of Q2 through the capacitor, and hence makes the base of Q2 negative. Immediately Q2 goes
OFF and Q1 becomes ON. However, this is only a quasi-stable state as is obvious form the
following observation.
With Q1 ON and Q2 OFF, the capacitor C finds a discharging path. As the capacitor
discharges, it is seen that the potential at the base of the transistor Q2 becomes less and less
negative, and after a time, we have VB = V? , the cut-in-voltage of Q2.
As soon as VB crosses the level of V? , Q2 starts conducting and gets saturated.
When Q2 becomes ON, Q1 becomes OFF. Thus the original stable state of the multivibrator is
restored.
[ In quasi-stable state: Q1 is ON and Q2 is OFF]

The interval during which the quasi-stable state of the multivibrator persists i.e., Q2
remains OFF is dependent upon the rate at which the capacitor C discharges. This duration of the
quasi-stable state is termed as delay time or pulse width or gate time. It is denoted as T. The
wave forms of the voltage at base of the transistor Q2 and C (Collector of Q1)
DESIGN:
VCE = 5.56v, VCC = 6v, VCE(sat) = 0.3v, VBE(sat), = 0.7v, IC = 6mA,VF = -0.3v
Rc = (VCC–VCE(sat))/IC.
? V BB R1
V R
VF ? ?
CE ( sat ) 2
VCC R1 VBE ( sat ) RC
VCE ? ? R1 ? R2 R1 ? R2
R1 ? RC R1 ? RC
Find the values of R1 and R2
Theoretical gate width ‘T’with Q1 in saturation = 0.69RC
PROCEDURE:
1. Connect the circuit as shown in figure.
2. With the help of a triggering circuit and using the condition T (trig) >
T(Quasi) a pulse waveform is generated.
3. The output of the triggering circuit is connected to the base of the off
transistor.
4. The Off transistor goes into ON state.
5. Observe the waveforms at VBE1, VBE2, VCE1, VCE2
7. Compare the theoretical and practical gate widths.
48
EXPECTED WAVEFORMS:
Q2 OFF, Q1 ON Q1 OFF, Q2 ON
V CC
VC2 Q2 ON, Q1 OFF VCE (SAT)
V??
VB2
t
I.R?C
VCC
VCE (SAT)
VC1
t
V??
VB1
t
Figure 2
OBSERVATIONS:
TON (Theoritical) = 0.69RC =
TON (practical) =
QUESTIONS:
1. Explain the operation of collector coupled Monostable Multivibrator?

2. Derive the expression for the gate width of a transistor Monostable Multivibrator?
3. Give the application of a Monostable Multivibrator.
CONCLUSION:
Conclusion can be made on time gate width ‘T’of the monostable multivibrator
theoretically and practically and output waveforms of the multi vibrator are identical or
not when compared with the theoretical wave forms.
49
50
Experiment No:10
BISTABLE MULTIVIBRATOR
AIM: To design a fixed bias Bistable Multivibrator and to measure the stable state
voltages before and after triggering.
1. Resistors
2. Transistors 2N2369 1 No.
APPARATUS:
1. Bread board
2. Power supply 0-30V 1 No.
3. CRO 1Hz-20MHz 1 No.
4. Connecting wires
5. Digital Multimeter
THEORY:
A bistable multivibrator has two stable output states. It can remain indefinitely in any
one of the two stable states, and it can be induced to make an abrupt transition to the other stable
state by means of suitable external excitation. It would remain indefinitely in this stable state,
until it is again induced to switch into the original stable state by external triggering.
Bistable multivibrators are also termed as ‘Binary’s or Flip-flops’. A binary is sometimes

referred to as ‘Eccles-Jordan Circuit’.
+VCC
I I2
RC1 RC2
R1 R1
C D
Q1 A B Q2
R2 R2
-VBB
Figure 1
51
Principle of Operation of bistable multivibrator.
Consider the circuit as shown in the figure.1. The transistor Q1 and Q2 are n-p-n
transistors. They are coupled to each other as shown in figure 1. It is evident that the output of
each transistor is coupled to the input of the other transistor. Since the transistors are identical,
there quiescent currents would be the same, unless the loop gain is greater than unity. When I1
increases slightly, the voltage drop across the collector resistance RC1 increases. Since VCC is
fixed, the voltage of point C decreases. This has the effect of decreasing the base current of Q2.
This, in turn, decreases the collector current of Q2 viz. I2 decreases, the voltage drop I2RC2
decreases. Hence the voltage of point D increases.
Due to increase of VD, the base current of Q1 increases. This increases the collector
current of Q1 viz I1. Thus I1 further increases. I1RC1 drop further increases, VC further decreases,
the base current of Q2 further decreases, with the result that I2 further decreases. Thus it can
easily seen that if the collector current I1 increases even marginally, I2 would go on progressively
decreasing and as a result, I1 would progressively increase. Eventually I2 would become
practically zero, cutting off the transistor Q2, at the same time transistor Q1 would conduct
heavily with the result that it would be driven into saturation. Thus Q2 becomes OFF and Q1
becomes ON. It can similarly be shown that if I2 increases even marginally similar sequence of
operation would result and ultimately Q2 would be ON and Q1 OFF. Thus when Q1 is ON, Q2 is
OFF and when Q1 is OFF Q2 is ON.
CIRCUIT DIAGRAM:
VCC 12V
RC1 RC2
2.2KO 2.2KO
R1 15KO R1 15KO
2N2369 2N2369
Q2 Q1
R2 100KO
100KO
R2
-VBB = -1.5V
Figure: 2
52
PROCEDURE:
1. Connect the circuit as shown in figure 2.

2. Observe the waveforms at VBE1, VBE2, VCE1, VCE2 using CRO & multimeter
3. Observe the voltages at VC1 and VC2.
4. If VC1= VCE(Sat) and VC2=VCC(Approximately) then Q1 is ‘ON’and Q2 is ‘OFF’
Otherwise VC1= VCC (Approximately) and VC2= VCE(Sat) ) then Q1 is‘OFF’and Q2
is‘ON’.
5. Observe which transistor is in ON state and which transistor is in OFF state. and
observe the voltages VC1, VC2, VB1, and VB2.
6. Apply –ve triggering at the base of the ON transistor and observe the voltages VC1,
VC2, VB1, and VB2.
EXPECTED WAVEFORMS:
Voltage
Voltage
VC1 VC2
VC2 VC1
0 t 0 t
Before Triggering After Triggering
OBSERVATIONS:
Before Triggering : When Q1 is ‘ON’and Q2 is ‘OFF’
VBE1 VBE2 VCE1 VCE2

Stable state Voltages
After Triggering: When Q1 is‘OFF’ and Q2 is‘ON’.
VBE1 VBE2 VCE1 VCE2

Stable state Voltages
QUESTIONS:
1. What is Multivibrator? Explain the principle on which it works? Why is it called a
binary?
2. Explain the role of commutating capacitors in a Bistable Multivibrator?
3. Give the Application of a Binary.
53
CONCLUSION:
Conclusion can be made on which transistor is ‘ON’and which transistor is
‘OFF’before triggering and after triggering.
54
Experiment No: 11
SCHMITT TRIGGER
AIM: To design a Schmitt trigger and to observe the waveforms for a given UTP & LTP
Values and test its performance.
1. Resistors
2. Transistors 2N2369 – 2
3.
APPARATUS:
1. Bread board
3. Signal generator(1Hz-1MHZ)
4. CRO(1Hz-20MHz)
CIRCUIT DIAGRAM:
VCC = 12V
RC1 RC2
R1
RB Q2 2N2369
Q1 2N2369
+
Signal V0
Vi Generator RE
- R2
Figure:1
55
THEORY:
The most important application of Schmitt Trigger circuit are amplitude comparator and
squaring circuit are amplitude comparator and squaring circuit. The circuit is used to obtain a
square waveform from any arbitrary input waveform. The loop gain is to be less than unity.
If Q2 is conducting there will be voltage drop across RZ which will elevate the emitter of
Q1. Consequently if V is small enough in voltage, Q1 will be cut-off with Q1 conducting, the
circuit amplifies and since the gain is positive, the output to rise, V2 continues to fall and Z2
continues to rise. Therefore a value of V will be reached where Q2 is turned OFF. At the point
the output no longer responds to the input.
Here the input signal is arbitrary except that it has large enough excursion to carry input
beyond the limits of hysteresis range, VH = (V1 – V2).
The output is a square wave whose amplitude is independent of the amplitude of the
input waveform.
DESIGN: Given UTP=5V,LTP=3V
IC2 = 5mA
(Rc2 + RE) = VCC / IC2
U.T.P = VE2 = 5V
VE2 = (RE ? VCC) / (Rc2+RE)
I2 = 0.1? IC2
L.T.P = VE1 = 3V
R2 = ER2i / I2 = VE1 / I2 = L.T.P / I2
Rc1 = {(RE? VCC) / VE1} –RE
IB2 = IC2 / hfe(min)
(VCC - VE2) / (R1+Rc1))) = (VE2/R2)+IB2
RB = (hfe? RE) / 10
Find R1, R2, RE, Rc1and Rc2 from the above equations
PROCEDURE:
1. Connect the circuit as shown in figure 1 with designed values.

2. Apply VCC of 12V and an input frequency of 1KHz with an amplitude more than the
designed UTP.
3. Now note down the output wave forms
4. Observe that the output comes to ON state when input exceeds UTP and it comes to OFF
state when input comes below LTP
5. Observe the waveforms at VC1, VC2, VB2 and VE and plot graphs.
56
MODEL GRAPHS:
Input sine wave

VMAX>UTP UTP
LTP
VC2
Schmitt Trigger
output
VC1
VB2
QUESTIONS:
1. Explain how a Schmitt trigger acts as a comparator?
2. Derive its expressions for UTP & LTP.
CONCLUSIONS:
Conclusion can be made on desined and practical values of U.T.P and L.T.P. and also made on
output waveform of Schmitt trigger for the given sinusoidal input.
57
58
Experiment No: 12
UJT RELAXATION OSCILLATOR
AIM : To obtain a saw tooth waveform using UJT and test its performance as an
oscillator
APPARATUS :
1. Resistors 47k? , 100?

2. Capacitor - 0.1? F
3. 2n2646 UJT
4. Bread board
6. CRO(1Hz-20MHz)
THOERY :
‘A Unijunction transistor (UJT), as the very implies, has only one p-n junction, unlike a
BJT which has two p-n junctions’.
+ is as shown in figure 1.
The equivalent circuit of the UJT
RB2
IE
VBB
RB1 V1
VE
Figure:1 -
RB1 is the resistance between base B1 and the emitter, and it is basically a variable
resistance, its value being dependent upon the emitter current IE.
RB2 is the resistance between base B2 and the emitter, and the value is fixed.
Consider the circuit as shown in figure 1.
Let IE = 0. Due to the applied voltage VBB a current I results as shown.
59
VBB
RB2
We have V1 = iRB1.
V BB
V1 But i ?
R B1 ? R B 2
i
? V BB ?
RB1 ? V1 ? ?? ?? RB1
? RB1 ? RB 2 ?
Figure 2.
? R B1 ?
? ?? ??V BB
? R B1 ? R B 2 ?
? R B1 ?
The ratio ?? ?? is termed as the intrinsic stand
? R B1 ? RB 2 ?
off ratio and it is denoted as ? .
? RB1 ? ? V1 ? ? V BB .
?? ? when , I E ? 0?
? RB1 ? RB 2 ?
Form the equivalent circuit, it is evident that the diode cannot conduct unless the emitter voltage
VE = V? + V1, where V? is the cutin voltage of the diode.
This value of the emitter voltage which makes the diode conduct is termed as peak
voltage, and it is denoted as VP.
We have VE = V? + V1,
or since VP = V? + ? VBB V1 = ? VBB.
It is obvious that if VE < VP, the UJT is OFF, and

if VE < VP, the UJT is ON.
Figure 3. shows the emitter characteristics of a UJT (plot of VE vs IE)

VE
VP Peak Point
Negative
resistance
region
VV
Valley Point
IE
0 IP IV
Figure 3.
60
The main application of UJT is in switching circuits wherein rapid discharging of

capacitor is very essential.
Having understood the basic of UJT, we shall next study the working of UJT relaxation
oscillator.
Working of UJT relaxation oscillator (OR UJT sweep circuit)

V or VBB
RB2 R
B2 E
+
B1
C Vs
RB1
Figure:4
The UJT sweep circuit shown in the figure 4 consists of a UJT, a capacitor and a resistor
arranged as shown.
We studied that a UJT is OFF as long as VE < VP, the peak voltage. Hence initially when
the UJT is OFF, the capacitor C charges through the resistance R from the supply voltage V.
Let VS = capacitor voltage.

It is seen that when the capacitor voltage VS rises to the value V P the UJT readily
conducts. When the UJT becomes ON, the capacitor discharges and its voltage falls. When the
voltage falls to the valley point VV, the UJT becomes OFF and the capacitor charges again to VP.
This cycle of charging and discharging of the capacitor C repeats, and as a result, a saw
tooth wave form of voltage across C is generated.
CIRCUIT DIAGRAM :
R1 VCC =12V
47k?
E B2
2N2646
B1
R2
100?
C 1. Emitter 2. Base1 3. Base2
0.1? F
Figure:5
61
PROCEDURE:
1. Connect the circuit as shown in figure with designed values.
2. Note down the voltages and frequencies across C& R2 .
3. The time period of the output wave form is noted and is compared with theoretical
value
T = R1 ? C[ ln {(VBB – VV) / (VBB – VP)}]
4. Plot the graphs of Vc and VR1.
EXPECTED WAVEFORMS:
VC VR2
VP
VV
t t
QUESTIONS:
1. Describe some important applications of a UJT?
2. Is the name UJT appropriate?
3. Write short notes on UJT as a relaxation oscillator?
4. Discuss the concept of –ve resistance?
5. Define the intrinsic stand off ratio and explain its importance?
CONCLUSIONS:
Conclusion can be made on how the UJT works as a saw tooth generator, which components in a
UJT circuit is used to generate the saw tooth wave form and also conclude on time period of the
output wave form of UJT theoretically and practically and also made on if the output waveform
of the UJ are identical with the theoretical wave forms or not.
62
Experiment No:13
BOOT STRAP SWEEP CIRCUIT
AIM: To design a bootstrap sweep circui and test its performan .
1. Resistors – 100k? , 5.6k? , 10 k?
2. Capacitors – 0.1? F, 10? F, 100? F
3. IN4007 Diode
4. 2N2369 Transistors – 2
Apparatus Required:
1. Bread board
2. Power supply(0V-30V)
3. CRO(1Hz-20MHz)
4. Signal generator(1Hz-1MHZ)
CIRCUIT DIAGRAM
VCC = 12V
IN4007 100µF
100K? 5.6K?
2N2369
Q2
2N2369
Function 0.1µF
generator Q1
10µF 10K? V0
Vi
Figure -VBB =-10V
DESIGN:
VCC ? Tg
VS ?
RC
TR ?
?(C ? V S ) / VCC ?
?
(h fe / RB ) ? (1 / R ) ?
Sweep time = TS = RC
63
THEORY:
The input to Q1 is the gating waveform. Before the application of the gating waveform, at
t = 0, transistor Q1 is in saturation. The voltage across the capacitor C and at the base of Q2 is
VCE(sat). To ensure Q1 to be in saturation for t = 0, it is necessary that its current be at least equal
to iCE / hFE so that Rb < hfeR.
With the application of the gating waveform at t = 0, Q1 is driven OFF. The current iC1
V t
now flow into C and assuming units gain in the emitter follower V0 ? CC . When the sweep
RC
starts, the diode is reverse biased, as already explained above, the current through R is supplied
by C1. The current VCC / R through C and R now flows from base to emitter of Q2.if the output
V0 reaches the voltage VCC in a time TS / Tg, then from above we have TS = RC.
If the sweep amplitude is less than VCC, then the maximum ramp voltage is given by
VCC Tg
VS ?
RC
PROCEDURE:
1. Connect the circuit as shown in figure.
2. Apply the square wave or rectangular wave form at the input terminals.
3. Connect the CRO at output terminals now plug the power card into line switch on and
observe the power indication.
4. As mentioned in circuit practical calculation. Observe and record the output waveforms from
CRO and compare with theoretical values.
EXPECTED WAVEFORMS :
Vi
Input
Vo
Output
ts tr
tg
64
Q1UESTIONS:
1. Describe the operation a single transistor Boot strap time base voltage waveform generator
making use of its related circuit diagrams?
2. Explain the principle of working of Boot strap circuit?
Conclusion:
Conclusions can be made on swee4p time Ts and retrace time TR and sweep voltage Vs of the
sweep waveform theoretically and practically and also made on if the output waveform of the
Bootstrap are identical with the theoretical wave forms or not.
65
66
Experiment No:14
SYNCHRONIZATION OF A UJT RELAXATION OSCILLATOR
AIM : To obtain synchronization and frequency division of a UJT relaxation oscillator by

applying negative pulse at base 2 of UJT and plot the waveforms
APPARATUS :
1. Resistors 47k? , 100? , 330?

2. Capacitor - 0.1? F, 10? F
3. 2n2646 UJT
4. Bread board
5. Power supply 0-30V
6. CRO (1Hz-20MHz)
7. Function generator (1Hz-1MHz)
THOERY
‘A Unijunction transistor (UJT), as the very implies, has only one p-n junction, unlike a
BJT which has two p-n junctions’.
+ is as shown in figure 1.
The equivalent circuit of the UJT
RB2
IE
VBB
RB1 V1
VE
Figure:1 -
RB1 is the resistance between base B1 and the emitter, and it is basically a variable resistance, its
value being dependent upon the emitter current IE.
RB2 is the resistance between base B2 and the emitter, and the value is fixed.
Consider the circuit as shown in figure 1.
Let IE = 0. Due to the applied voltage VBB a current I results as shown.
67
VBB
We have V1 = iRB1.
V BB
RB2 But i ?
R B1 ? R B 2
? V BB ?
V1 ? V1 ? ?? ?? RB1
i ? RB1 ? RB 2 ?
RB1 ? R B1 ?
? ?? ??V BB
? R B1 ? R B 2 ?
Figure 2. ? RB1 ?
The ratio ?? ?? is termed as the intrinsic stand
? RB1 ? RB 2 ?
off ratio and it is denoted as ? .
? RB1 ? ? V1 ? ? V BB .
?? ? when , I E ? 0?
? RB1 ? RB 2 ?
Form the equivalent circuit, it is evident that the diode cannot conduct unless the emitter voltage
VE = V? + V1, where V? is the cutin voltage of the diode.
This value of the emitter voltage which makes the diode conduct is termed as peak
voltage, and it is denoted as VP.
We have VE = V? + V1,
or since VP = V? + ? VBB V1 = ? VBB.
It is obvious that if VE < VP, the UJT is OFF, and

if VE < VP, the UJT is ON.
Figure 3. shows the emitter characteristics of a UJT (plot of VE vs IE)
VE
VP Peak Point
Negative
resistance
region
VV
Valley Point
Figure 3.
IE
0 IP IV
68
The main application of UJT is in switching circuits wherein rapid discharging of capacitor is
very essential.
Having understood the basic of UJT, we shall next study the working of UJT relaxation
oscillator.
69
Working of UJT relaxation oscillator (OR UJT sweep circuit)

V or VBB
RB2 R
B2 E
+
B1
C Vs
RB1
Figure:4
The UJT sweep circuit shown in the figure 4 consists of a UJT, a capacitor and a resistor
arranged as shown.
We studied that a UJT is OFF as long as VE < VP, the peak voltage. Hence initially when
the UJT is OFF, the capacitor C charges through the resistance R from the supply voltage V.
Let VS = capacitor voltage.

It is seen that when the capacitor voltage VS rises to the value V P the UJT readily
conducts. When the UJT becomes ON, the capacitor discharges and its voltage falls. When the
voltage falls to the valley point VV, the UJT becomes OFF and the capacitor charges again to VP.
This cycle of charging and discharging of the capacitor C repeats, and as a result, a saw
tooth wave form of voltage across C is generated.
Synchronization and frequency division of UJT:

The synchronization principle of UJT is shown in fig (a)
Synchronization to an external signal is possible because this signal may be introduced at the
sync terminal in such a a manner as to change the peak voltage Vp .Thus in the UJT a negative
pulse applied at B2 as shown in fig (b) will lower Vp ,whereas in the SCS , the thyristor and the
thyraton a positive pulse applied at the gate , the base , or the grid will serve the same purpose
The situation which results when synchronizing pulses are applied shown in fig c.The effect of
the sync pulse is to lower for the duration of the pulse , the peak or break down voltage as
indicated .A pulse train of regular space is shown starting at an arbitrary time t = 0
The first several pulses have no influence on the sweep generator , which continues to run
unsynchronized .Eventually however the exact moment at which the negative resistance device
goes ON is determined by the instant of occurrence of a pulse as is also each succeeding
beginning of the ON interval .From the point on the sweep generator runs synchronously with
the pulses
In order that synchronization may result , it is necessary that each pulse shall occur at a time
when it may serve to terminate the cycle prematurely .This requirement mean that the interval
between pulses , Tp must be less than the natural period, To, of the sweep generator .in fig (d)the
case in which Tp>To .Here synchronization of each cycle does not occur . The pulses do serve to
establish that four sweep cycles shall occur during the course of 3 pulse periods, but
synchronization of this type is normally of no value .Even if the requirement Tp<To is met ,
70
synchronization cannot result unless the pulse amplitude is at least large enough to bridge the
gap between the quiescent breakdown voltage Vc. In fig (e) have the case Tp is less than To as
required but the pulses amplitude is too small and again synchronization does not result
VYY
+ C +
Vi
S Vc
-
-
a) A sweep generator
VBB =12v
330?
R1
47k?
B2 10? F
E
2N2646
Function
B1 Vi generator
Vc o/p R2
100?
0.1? F 1. Emitter 2. Base1 3. Base2
Fig (b)
t=T
VC TP
To
Vv , valley or maintaining voltage
c)an initially unsynchronized generator falls into synchronization shortly after the application of
synchronizing pulses
71
TP
To
d) illustrating that for synchronization to result ,Tp must less than To;
TP
To
e) illustrating failure of synchronization due to inadequate amplitude of sync pulses

Tp
2 1 2 1 2 1 2
V
S
Vs
1
V
Tp
Ts
To
f) frequency division by a factor of 2 in a sweep generator
CIRCUIT DIAGRAM
VBB =12v
330?
R1
47k?
B2 10? F
E
2N2646
Function
B1 Vi generator
Vc o/p R2
100? 72
0.1? F
PROCEDURE:
1. Connect the circuit as shown in circuit diagram
2. Note down the voltage Vs and time period To across the capacitor ‘c’without
giving external sync pulses
3. Now apply external negative sync pulses to the Base2 of UJT
4. Now adjust the amplitude and time period Tp in such a way Tp<To of the sync
pulses until synchronization is achieved
5. Now note down the sweep voltage Vs and time period if the sweep wave form
across capacitor ‘c’
6. Now adjust the Amplitude and Time period Tp is such a way Tp<<To to achieve
frequency division of 2:1, 3:1, 4:1.
QUESTIONS:
1. Describe some important applications of a UJT?
2. Is the name UJT appropriate?
3. Write short notes on UJT as a relaxation oscillator?
4. Discuss the concept of –ve resistance?
5. Define the intrinsic stand off ratio and explain its importance?
6. Explain how synchronization is achieved using UJT?
7. What are the conditions to achieve frequency division using UJT?
Conclusion:
Conclusions can be made on what are the conditions required to achieve for the synchronization
and frequency division using UJT sweep generator.
73
Experiment No:15
STUDY OF LOGIC GATES USING INTEGRATED CIRCUITS
AIM : To study the various logic gates by using digital integrated circuits
COMPONENTS:
1. IC 74LS00,
2. IC 74LS02,
3. IC 74LS04,
4. IC 74LS08,
5. IC 74LS10,
6. IC 74LS32,
7. IC 74LS86.
8. Digital IC trainer kit.
9. Patch cards
THEORY:
The logical operations involved in Boolean algebra are OR, AND, NOT. These
operations are involved in the design of digital systems. These functions are performed by an
electronic circuit known as ‘gate’, such as OR gate, AND gate and NOT gate. These logic gates
are the basic building blocks of digital systems.
NOT gate:
A NOT gate has only one input and one output. It performs a basic logic function called
‘inversion’ or ‘complementation’. In this logic function, when a High level is applied to this gate
as input, a low level will appear on its output. When a low level is applied to its input, a High
level will appear on its output. Thus in the logic function, the output of this gate is the
‘complement’of the input.
A Y= A
Symbol
AND gate:
AND gate performs logical multiplication. The operation of this gate is such that the
output is high only when all the inputs are high. When any of the inputs are low, the output is
low. The AND gate is composed of two or more inputs and a single output. Fig shows the logic
symbol for a AND gate with two inputs A and B, and the output Y.
A
Y=A.B
B
74
Pulse and Digital Circuits LabSYMBOL
MANUAL ONLY FOR REFERENCE
OR gate:
An OR gate has two or more inputs and one output. The operation of OR gate is such
that a High on the output is produced when any of the inputs are High. The output is low only
when all of the inputs are low. Fig. shows the logic symbol for an OR gate with two inputs A
and B and the output Y.
A
Y=A+B
1
SYMBOL
NAND gate:
The term NAND is a contraction of NOT-AND and implies an AND function with an
inverted (NOT) output. The operation of this gate can be analyzed, using an equivalent circuit
shown in fig. Which has an AND gate followed by an inverter (NOT). If the inputs are A and B,
then the output of AND gate is A.B and complement of this is A.B ? A ? B
A
Y = A.B Y ? A.B
A
Y ? A.B
B
Symbol
NOR gate:
The term NOR is a contraction of NOT-OR and implies an OR function with an inverted
(NOT) output. The operation of this gate can be analyzed using an equivalent circuit, shown in
Fig. Which has an OR gate followed by an inverter (NOT). If the inputs are A and B, then the
output of OR gate is A + B, and complement of this is
NAND and NOR gates are very popular logic gates because they have a ‘Universal’
function, i.e., they can be used to construct an AND gate, an OR gate, a NOT gate or any
combination of these functions. Hence NAND and NOR gates are known as ‘Universal gates’.
A
Y=A+B Y ? A? B
A
Y ? A? B
B
75
Symbol
Exclusive-OR gate:
Exclusive-OR operation is not a basic operation. It can be performed by using either

basic gates or Universal gates. Exclusive-OR gate, abbreviated as XOR or EX-OR. The output
expression for the circuit is Y ? AB ? AB. Fig. shows a standard symbol for EX-OR gate, Notice
that the output is High only when the two inputs must be different to get a High output.
A
Y ? A? B
B
Symbol
PIN CONFIGURATIONS:
14 13 12 11 10 9 8 14 13 12 11 10 9 8
VCC VCC
74LS00 74LS02
Gnd Gnd
1 2 3 4 5 6 7 1 2 3 4 5 6 7
NAND GATE IC NOR GATE IC
14 13 12 11 10 9 8 14 13 12 11 10 9 8
VCC VCC
74LS04 74LS08
Gnd Gnd
1 2 3 4 5 6 7 1 2 3 4 5 6 7
NOT GATE IC AND GATE IC
14 13 12 11 10 9 8 14 13 12 11 10 9 8
VCC VCC
74LS10 74LS32
Gnd Gnd
1 2 3 4 5 6 7 1 2 3 4 5 6 7
3-INPUT NAND GATE IC OR GATE IC
14 13 12 11 10 9 8
VCC
74LS86 76
Gnd
1 2 3 4 5 6 7
EX-OR GATE IC
77
Tabular forms:
AND Gate OR Gate NAND Gate NOR Gate EX-OR Gate

A B Y A B Y A B Y A B Y A B Y
0 0 0 0 0 0 0 0 0 0
0 1 0 1 0 1 0 1 0 1
1 0 1 0 1 0 1 0 1 0
1 1 1 1 1 1 1 1 1 1
3 Input NAND gate NOT Gate

A B C Y A Y
0 0 0 0
0 0 1 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Digital circuit can be classified into two types. These are combinational and sequential
logic circuits. The logic circuits, in which their outputs at any instant of time may depend upon
the inputs present at that time, are known as combinational logic circuits. The combinational
logic circuit which includes memory elements in its feed back path is known as sequential logic
circuits. The outputs in a sequential circuit are a function not only of inputs but also of the
present state of the memory elements. Flip-Flops are the basic building blocks for the sequential
logic circuits.
The basic digital memory circuit is known as Flip-flop. It has two stable states which are
known as the 1 state and the 0 state. It can be obtained by using NAND or NOR gates.
PROCEDURE:
1. Place the IC on the bread board in the Digital Trainer Kit.

2. Connect the VCC and Ground to pin number 14 and & 7 respectively.
3. Verify the truth table by giving the inputs and observing the output for each gate in
the given IC
QUESTIONS:
1. What are the Universal gates?
2. Design an AND gate using NAND gates?
3. Design an OR gate using NOR gates?
CONCLUSION:
given logic gates and also check whether all the gates are working or not .
78

PDCLab Manual

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

PDCLab Manual

Uploaded by

Copyright:

Available Formats

Pulse and Digital Circuits Lab MANUAL ONLY FOR REFERENCE

LINEAR WAVE SHAPING

a) RC Low Pass Circuit :

Figure 1: RC Low Pass Circuit.

Let Vi = alternating input voltage.

Applying Kirchoff’s Voltage Law to RC low pass circuit (fig.1).

Multiplying throughout by C, we get

Integrating with respect to T on both sides, we get

?CVi .dt ? RC ?i.dt

The output voltage is proportional to the integral of the input voltage.

b) High Pass Circuit.

Figure: 2. RC High Pass Circuit.

Applying Kirchoff’s Voltage Law to RC high pass circuit (fig.2)

As RC << T, the above equation is modified as

Differentiating above equation with respect to T.

1. Connect the circuit as shown in the figure1 &2.

High pass filter:

NON LINEAR WAVE SHAPING - CLIPPERS

There are three different types of clipping circuits.

In negative clipping circuit instead of positive portion of sinusoidal signal, negative

Figure: 2(a). Input waveform Figure: 2(b)Output waveform.

II. Positive Clipping with Positive Reference Voltage

Figure:4(a). Input waveform Figure:4(b). Output waveform.

III. Positive Clipping with Negative Reference Voltage

Figure:6(a). Input waveform Figure:6(b) Output waveform.

IV Negative Clipping Circuit

Figure:8 (a). Input waveform Figure:8 (b). Output waveform.

V. Negative Clipping with Negative Reference Voltage

Figure:10(a). Input waveform. Figure:10(b) Output waveform.

VI. Negative Clipping with Positive Reference Voltage

Figure:12(a) Input waveform Figure:12(b) Output waveform.

Figure:14(a). Input waveform Figure14(b). Output waveform.

NON LINEAR WAVE SHAPING – CLAMPERS

1. Positive Clamping Circuit.

Negative Clamping Circuit

Positive Clamping Circuit:

Negative Clamping with Positive Reference Voltage

Similarly, the average of

Figure:4 (a).Input waveform Figure:4 (b) Output waveform.

II. Negative Clamping with Positive Reference Voltage.

Figure:6 (a).Input waveform Figure:6 (b) Output waveform.

III. Negative Clamping with Negative Reference Voltage.

Figure:8 (a).Input waveform Figure:8 (b) Output waveform.

IV. Positive Clamping.

Figure:10 (a).Input waveform Figure:10 (b) Output waveform.

V. Positive Clamping with Negative Reference Voltage.

Figure:12 (a).Input waveform Figure:12 (b) Output waveform.

VI. Positive Clamping with Positive reference Voltage.

Figure:14 (a).Input waveform Figure:14 (b) Output waveform.

AIM : To design and observe the performance of a transistor as a switch.

Fig.1. Transistor as a switch. Fig.2 Pin configuration of transistor 2N2369.

CIRCUIT DIAGRAM: VCC +12V

Pin Configuration 2N2369 Figure 4.

Ic max = 5mA, VBE = 0.7V,VCE (sat) = 0.2V,Vcc = 12V.

1. Connect the circuit as shown in the figure 4.

EXPECTED WAVE FORMS:

VBE VCE VCB

When transistor is OFF

1. Discuss the advantages of an electronic switch over a mechanical or electro

STUDY OF LOGIC GATES

AIM : To study the various logic gates by using discrete components.

1. Resistors - 1k? -1, 10 k? -2