School of Electrical & Information Engineering

EEET 1013 Digital Devices and Systems

Practical 2
VHDL method of design entry
31/03/2010

A. Introduction:

In Practical 1, you learnt how to design simple digital logic using ‘Schematic
Entry’ procedure, using Xilinx (ISE) software package. You also learnt how to
create a schematic diagram and save it as a .sch( schematic). You must have
realized that a waveform file .tbw( test bench waveform) is needed to create
‘inputs’ to any circuit. Now, that you are familiar with the process of compiling
the above files through Compilation Editor and also with the process of
simulating the functionality of the circuit through Simulation Editor, the next
step is to use second method of design entry using Hardware Description
Languages such as VHDL, introduced in Week 4 & 5 lectures.

(Note: You have to clear your working directory in d: drive before leaving the
laboratory. You are encouraged to copy your files into your own ‘flash disk’(
memory stick).As files are bigger in size, you may not be able to store them in 3
½” floppy disks)

B. Objective

In Practical 2, you will use the same CAD tool namely Xilinx(ISE) 9.2. You will
be programming a CPLD XC 95108. Xilinx (Integrated Synthesis Environment)
software package is a very powerful tool for designing complex systems and I
would encourage you to explore many features of this package through your own
‘search methods’. The practical is designed to satisfy the UniSA Graduate
Quality 4 by working as an individual in applying knowledge gained through
lectures and as a team to achieve the final desired outcome, in addition to
satisfying the Graduate Qualities GQ3 and GQ4.

The main objectives of this practical are as follows:

• To examine the function of a decoder
• To design and test a 2-4 decoder with active-low outputs using VHDL
HDL.
• To design and simulate a 3-8 decoder design with active-high outputs in
HDL by writing a VHDL code and test the functionality through
simulation.( This is an exercise and the results are to be shown to the
tutor at the end-of-the hour)

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C . Programmable Logic Device (PLD)Software Simulation: ( P197)

Part A introduced to a Quick Start procedure that will be used throughout the
semester to create a digital logic circuit. Loading this digital logic circuit into a
CPLD IC will be dealt with toward the end of semester for designing small
projects. However, due to time constraints, this may not be guaranteed.
Whether you are using the PLD software from Altera or Xilinx, the five-step
process for creating a digital circuit prototype using a PLD will be the same.
These steps are

PLD prototyping process

Step 1: Create the new circuit using any one of the following design entry
methods.(the software‘s schematic editor, text editor or state machine entry).

Step 2: Compile the circuit into a bit stream file that when loaded into the
CPLD will instruct it to act like the entered schematic

Step3: Verify the operation of your circuit using the software’s functional and
timing simulator

Step 4: Download the circuit file from the PC to the PLD.

Step 5: Physically test the PLD by activating its inputs and monitoring its
outputs

The software simulator listed in Step 3 is a useful tool that can make you
aware of circuit errors before you program the CPLD. You can perform both a
functional simulation and timing simulation on your newly created and
compiled circuit.

A functional simulation checks the logical operation of the circuit by

showing what binary outputs will occur for each of the binary input
combinations. This type of simulation is useful for quick analysis of the
circuit’s behaviour, but does not take into account any errors that could occur
due to propagation delays.

A timing simulation is by far the most crucial part of the verification process,
since it simulates the responses you will get from the circuit once it has been
implemented within the PLD. The timing simulation takes into account the
delays associated with the PLD’s internal logic gates, routing capacitances
and input impedances.

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You must note that the results from the simulation of the circuit can be printed
out and used later in STEP 5 above to compare the simulated behaviour of
the circuit

Following steps can be performed to perform a functional simulation of a

logic gate using Xilinx software package.

D. Quick Start Procedure: ( Design a 2-to-4 Decoder using VHDL)

Creating a new design with Xilinx

(as you will be using new version of the software, there might be few
changes in the diagram Take help from Tutor)

1. Start Xilinx’s project navigator : StartÆ All ProgramsÆXilinx ISE 6Æ

Project Navigator or by double clicking in the following icon.

2. The following Project Navigator window will pop up.

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 Figure 2.1 Project Navigator Window

3. Create a new project called Decoder2_4 first by selecting File Æ New

Project. Following window pops up.

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 Figure 2.2 Project Window

4. From the pull down menu of Top-Level Module Type, choose, HDL
Click Next. The window shown in Figure 2.3 will pop up.

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 Figure 2.3 Device & Design Flow window

5. As necessary, change Device Family, Device, Package and speed

grade to XC9500 CPLDs, xc95108, PC84 and -7 respectively.

6. Choose Synthesis tool as XST(VHDL/Verilog); simulator as others,

Generated Simulation language as VHDL. Click Next button. Following
window pops up as shown in Figure 2.4.

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 Figure 2.4 Create a New Source window

7. Click Next. And for the next window also click Next. The following
window as shown in Figure 2.4 will emerge giving details of your project.
Click ‘Finish’ button.

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 Figure 2.4 Details of Project Decoder2_4

4. Select Project Æ New Source. In the New Source message box shown
in Figure 2.5, select by highlighting VHDL Module as the source. Type in the
file name Decoder2_4 and make sure Add to project is checked. Then click
on the Next button.

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 Figure 2.5 Add VHDL Module as new source to Decoder2_4 project

8. The Define VHDL Source window pops up. You can now enter all the
inputs and outputs for your 2-4 decoder. Type inputs A and B in the
column Port Name and use the default direction in. Type Z0 throughZ3
and select out for outputs of the decoder as shown in Figure 2.6.Then
click on the Next button.

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 Figure 2.6 Define VHDL Source

9. New source information dialog box as shown in Figure 2.7 now pops
up and it displays information about the VHDL module. Observe that 2
input ports and 4 output ports are defined. Click Finish.

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 Figue 2.7 New Source Information dialog box

10. In the Project Navigator window , a skeleton VHDL code for

Decoder2_4.vhd is displayed as shown in Figure 2.8 . Keywords such
as library, use, all, entity, is, Port, in, out, architecture, of , begin
and end are shown in blue color on your screen. Note that either
lowercase or upper case are permitted in these keywords.

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 Figure 2.8 The template of HDL code for Decoder2_4

There are few lines you have to be familiar with. The first line of the file(
library IEEE) is similar to the #include directive in C or C++ program in that
it specifies libraries specified in the design. The IEEE library allows the
designer to access various micros, definitions and functions. A library can
be further divided into packages. Each package contains a group of
features in a certain area.

The second line ( use IEEE.STD_LOGIC _1164.ALL) specifies that this

design will have access to all the features in the STD_LOGIC_1164
package of the IEEE library.

The section between entity Decoder2_4 is and end Decoder2_4; defines

the interface to the Decoder2_4 circuit. All inputs and outputs are declared
here. External circuitry can access the functions of the circuit through
those inputs and outputs. Note that we have to follow the specific format of
the syntax for the interface definition.

The following line is the beginning of the architecture for the Decoder2_4
circuit. It is in this part that we will enter the statement code to describe
our decoder circuit.

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11. Add the four Boolean equations describing the functionality of the 2-to-4
decoder circuitry between begin and end Behavioral in the workspace.
Z0 <= not ( not A and not B);
Z1 <= not ( not A and B);
Z2 <= not ( A and not B);
Z3 <= not (A and B);
To define the logic operations of the circuit, the keywords not, and, and or
Are used.
(Note: VHDL does not allow us to write complemented outputs such
as not Z0)

Hence, the right sides of Boolean Equations are complemented to obtain

uncomplemented outputs. Figure 2.9 shows the completed VHDL code
after the addition of the above four statements.

Figure 2.9 Completed VHDL code

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 Simulation :
You can use the ModelSim simulation tools to verify the circuit. We will
next introduce how to perform simulation using ModelSim tool. Simulate
your VHDL design with ModelSim.

12. You need to add a Test Bench Waveform Source to your .vhd design. To
do this, first highlight Decoder2_4.vhd in your Project Navigator
Window. Then, choose Project Æ New Source from the menu bar. In
the New window that appears next, select Test Bench Waveform, type
Decoder2_4w.tbw and check the Add to project box. Then, click on
the Next button.

Figure 2.10 The New Message box for generating Test Bench Waveform

13. This will bring up the dialog box shown in Figure 2.11.

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 Figure 2.11 Source Dialog box

14. Click on the Next button in the Select window and this will bring New
Source Information window as shown in Figure 2.12.

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 Figure 2.12. New Source Information Dialog box

15. Click Finish button on the New Source Information window. You
should see now Initialize Timing window as shown in Figure 2.13. In
this window, accept the default settings as follows by clicking the OK
button.
• Combinatorial Design (or internal clock) checked
• Check outputs 50 ns
• Assign inputs 50 ns
• Time Scale ns

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 Figure 2.13 The Initialize Timing Window

16. The test waveform for Decoder2_4w.tbw is displayed as shown in

Figure 2.14 . Click on the Zoom in or Zoom out icons to change the
number of cycles you want to view.

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 Figure 2.14 Testbench waveform in HDL bencher

17. Next you will initialize the inputs A and B to produce outputs Z0,Z1,Z2
and Z3. A and B will take the binary values 1 and 0. See the truth table
below.

A B
L L
L H
H L
H H

In the Waveform HDL Bencher window, enter the input stimulus in the
blue area in each cell. For example to get A=1 in third cell (A is used as
MSB), click the blue area in time column 200 . Double clicking any blue
area will change to white area with ‘Pattern’ word showing up. You can
now change t0 0 or 1.
Repeat the same to assign input values for other time columns so as to
satisfy the above table. When you finish, the Waveform HDL Bencher
window should look similar to Figure 2.15.

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Figure 2.15. Test Bench waveform in HDL Bencher after input assignments

18. Save your testbench waveform by selecting File Æ save . The new test
bench waveform source Decoder2-4w.tbw is added to the project.

19. Now you will be able to generate the expected outputs for the
Decoder2_4 module based on the input values you initiated. To
accomplish this, first highlight Decoder2_4w.tbw in the Sources in
Project pane. In the Processes for Source pane, click the +sign beside
ModelSim Simulator to expand the hieracrchy.

Then, double-click on the Generated Expected Simulation Results.

This process runs a background simulation using the inputs you
initialized. A dialog box with the message ‘ The file has been modified.
Do you want to reload it?’ will appear. Click ‘yes’ button. The outputs are
now added to the test bench waveform and the modified waveforms will
look similar to Figure 2.16. Obtain a print out of the results and paste it
here.

Figure 2.16 Final output of the decoder2_4

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 Exit the HDL Bencher without saving your waveform.

Exercise: (This carries 5% in the overall assessment for

undergarduates)

Multiplexers and demultiplexers are often used in many applications.

They are used internally inside microcomputer bus system. Also, they
are used in communication system for channel sharing. Basically,
multiplexer divides/shares one line data to multiple lines and function
of demultiplexer exactly opposite of the multiplexer.

You are required to generate a function of 1-line to 8-line

demultiplexer. You have two 1-line to 4-line demultiplexer ICs and
one inverter available with you. Perform following tasks:

1. Write VHDL code for 1-line to 4-line demultiplexer IC with

behavioral style of modeling.

2. Write VHDL code for Inverter with data flow style of modeling.

3. Now write VHDL code for 1-line to 8-line demultiplexer using 1-

line to 4-line demultiplexer generated in task 1 and an Inverter
generated in task 2 as components. You must use structural style
of modeling here. You may do so by component declaration with
package or without component declaration without package.

Enter the code for this IC by implementing using VHDL method of design entry,
and test the function of the chip using ModelSim Simulator. Mention any
assumptions made in the design.

Show print outs of VHDL code, input stimulus & the output waveforms to the tutor
and attach the printouts of the code & the waveforms directly to the 'Practical
assessment feedback' cover sheet, attached to the next page.

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 Practical Assessment feedback
School of Electrical and Information Engineering
EEET 1013: Digital Devices and Systems(5%)

Practical 2: To write VHDL code for a Combinational Circuit (implemented in a device) using HDL entry
method and verify the operation. This is due on the same day of practical at the end of the hour ( Week 5 &
6 for UG's)

The Graduate qualities being assessed by this practical are the ability to
• Be an effective problem solver by employing the right features of the CAD tool such as Xilinx(ISE) and
• contribute individually and as a group to the overall success of the practical

Student 1 ID: Group ID:

Student 2 ID:
Student 3 ID:

Names (1): Marker: Kollengode S Ananthakrishnan/

(2): Aakash Dawadee

Key components of this practical Mark Comment by marker

Part 1: Design(Combinational Circuit) /10

• ability to develop the correct VHDL code
• write VHDL code with minimal errors
Part 2: Implementation /10
• Create the correct code, compile with no errors & warnings
• Generate correct input stimulus
Part 3: Results /10
• demonstration of the correct output waveforms
• brief discussion of results (oral questions by tutor)
Summary Comment

The Graduate qualities being assessed by this assignment are indicated by an X:

GQ1: operate effectively with and upon a body of
knowledge
GQ2: are prepared for lifelong learning
x GQ3: are effective problem solvers
x GQ4:can work both autonomously and collaboratively
GQ5: are committed to ethical action and social
responsibility
GQ6: communicate effectively
GQ7: demonstrate an international perspective

Practical 1 marks /30

This form meets the 2006 requirements of UniSA’s Code of Good Practice: Student Assessment

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