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Gain [dB]
-20
-40
-60
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Frequency [GHz]
m1
freq=2.540GHz
nf(2)=1.416
60
50
Layout 20
10 m1
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Frequency [GHz]
Frequency Synthesizer
Chip photograph
“TOP_Rogers” 35 microns
“Bottom_FR4” 35 microns
PCB Cross-section
Frequency Synthesizer
16 Bands
Layout 3D Simulation
EM Similation of BAW Filter
dB(measurement..S(2,1))
dB(measurement..S(3,2))
0 0
dB(TD_FD..S(2,1))
dB(TD_FD..S(3,2))
-20 -20
-40 -40
-60
-60
-80
-80
1.70
1.75
1.80
1.85
1.90
1.95
2.00
2.05
2.10
1.78
1.82
1.86
1.90
1.94
1.98
2.02
2.06
2.10
2.14
2.18
A freq, GHz
freq, GHz
C
D
dB(measurement..S(3,1))
-20
dB(TD_FD..S(3,1))
-40
-60
-80
-100 A: Rx Chip
1.80
1.83
1.86
1.89
1.92
1.95
1.98
2.01
B: Application board with laminate
B
freq, GHz and bondwire
E C: TX pass band
D: RX pass band
E: Isolation between TX and RX
chip
Disc Monopole Antenna for Handhelod Devices
Hardware part:
• Programming a CPLD in VHDL
• Implementation of a controller to
disconnect DRAM modules from
memory bus to apply test modes
• Implementation of a microcontroller
interface
Microcontroller part:
• 8051
• RS232 a control PC interfaces
• SRAM and CPLD interfaces
• To load test vectors and trigger
CPLD
FPGA Programming for DDR2
Hardware part:
• PCI core development and
implementation
• To make interface for various units on
the PCI card
Microcontroller part:
• 8051
• RS485 bus to control PC
• Implementation of SRAM interface
• Interface to FPGA internal register
• Implementation of x86 PNP conform
boot ROM into microcontroller to boot
PC off the CF card
DDR3 Timing Analysis
Thank You !
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