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  • Following Is The Verilog Code For A 3-Bit 1-Of-9 Priority Encoder

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    rameshbe048030
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    The document contains code for several Verilog modules: 1. A 3-bit 1-of-9 priority encoder that encodes a 8-bit input into a 3-bit output code based on which input bit is high. 2. A 3-input multiplexer that selects one of four data inputs to output based on a 2-bit select code. 3. A 4-bit comparator that compares two 4-bit inputs and outputs a 3-bit code indicating if one input is greater than, less than, or equal to the other. 4. Descriptions of nets in Verilog, which connect circuit elements and can carry signals, and of variable data types like reg that store logic values and are

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    The document contains code for several Verilog modules: 1. A 3-bit 1-of-9 priority encoder that encodes a 8-bit input into a 3-bit output code based on which input bit is high. 2. A 3-input multiplexer that selects one of four data inputs to output based on a 2-bit select code. 3. A 4-bit comparator that compares two 4-bit inputs and outputs a 3-bit code indicating if one input is greater than, less than, or equal to the other. 4. Descriptions of nets in Verilog, which connect circuit elements and can carry signals, and of variable data types like reg that store logic values and are

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    Attribution Non-Commercial (BY-NC)
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    88 views5 pages

    Following Is The Verilog Code For A 3-Bit 1-Of-9 Priority Encoder

    Uploaded by

    rameshbe048030
    The document contains code for several Verilog modules: 1. A 3-bit 1-of-9 priority encoder that encodes a 8-bit input into a 3-bit output code based on which input bit is high. 2. A 3-input multiplexer that selects one of four data inputs to output based on a 2-bit select code. 3. A 4-bit comparator that compares two 4-bit inputs and outputs a 3-bit code indicating if one input is greater than, less than, or equal to the other. 4. Descriptions of nets in Verilog, which connect circuit elements and can carry signals, and of variable data types like reg that store logic values and are

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 5

    Following is the Verilog code for a 3-bit 1-of-9 Priority Encoder.

    module priority (sel, code);


    input [7:0] sel;
    output [2:0] code;
    reg [2:0] code;

    always @(sel)
    begin
    if (sel[0]) code = "000";
    else if (sel[1]) code = "001";
    else if (sel[2]) code = "010";
    else if (sel[3]) code = "011";
    else if (sel[4]) code = "100";
    else if (sel[5]) code = "101";
    else if (sel[6]) code = "110";
    else if (sel[7]) code = "111";
    else code = 3'bxxx;
    end
    endmodule
    MUX

    module mux3( select, d, q );

    input[1:0] select;
    input[3:0] d;
    output q;

    reg q;
    wire[1:0] select;
    wire[3:0] d;

    always @( select or d )
    begin
    if( select == 0)
    q = d[0];

    if( select == 1)
    q = d[1];

    if( select == 2)
    q = d[2];

    if( select == 3)
    q = d[3];
    end

    endmodule
    Decoder
    verilog code for 4 bit comparator is: 
    module comp(a,b,y); 
    input [3:0]a; 
    input [3:0]b; 
    output [2:0]y; 
    reg [2:0]y; 
    always @(a or b) 
    begin 
    if(a=b) 
      y2='1'; 
      y1='0'; 
      y0='0'; 
    else if(a<b) 
       y2<='0'; 
       y1<='1'; 
       y0<='1'; 
    else 
       y2<='0'; 
       Y1<='0'; 
       Y0<='1'; 
    end if; 
    end if; 
    end module

    Nets
    A net signifies a connection from one circuit unit to another. Such a net carries the
    value of the signal it is connected to and transmits to the circuit blocks connected
    to it. If the driving end of a net is left floating, the net goes to the high impedance
    state. A net can be specified in different ways.
    wire: It represents a simple wire doing an interconnection. Only one output is
    connected to a wire and is driven by that.
    tri: It represents a simple signal line as a wire. Unlike the wire, a tri can be
    driven by more than one signal outputs.
    Functionally, wire and tri are identical. Distinct nomenclatures are provided
    for the convenience of assigning roles. Other types of nets are discussed in
    Chapter 5.
    SCALARS AND VECTORS 41
    3.10.2 Variable Data Type
    A variable is an abstraction for a storage device. It can be declared through the
    keyword reg and stores the value of a logic level: 0, 1, x, or z. A net or wire
    connected to a reg takes on the value stored in the reg and can be used as input
    to other circuit elements. But the output of a circuit cannot be connected to a reg.
    The value stored in a reg is changed through a fresh assignment in the program.
    time, integer, real, and realtime are the other variable types of data;
    these are dealt with later.

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