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GMS81C1404
GMS81C1408
User’s Manual
Table of Contents
GMS81C1404 / GMS81C1408
CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
1. OVERVIEW
1.1 Description
The GMS81C1404 and GMS81C1408 are an advanced CMOS 8-bit microcontroller with 4K/8K bytes of ROM. The Hynix
semiconductor’s GMS81C1404 and GMS81C1408 are a powerful microcontroller which provides a highly flexible and cost
effective solution to many small applications such as controller for battery charger. The GMS81C1404 and GMS81C1408
provide the following standard features: 4K/8K bytes of ROM, 192 bytes of RAM, 8-bit timer/counter, 8-bit A/D converter,
10-bit high speed PWM output, programmable buzzer driving port, 8-bit serial communication port, on-chip oscillator and
clock circuitry. In addition, the GMS81C1404 and GMS81C1408 supports power saving modes to reduce power consump-
tion.
Operatind
Device name ROM Size EPROM Size RAM Size Package
Voltage
GMS81C1404 4K bytes - 192bytes 2.2 ~ 5.5V 28 SKDIP or SOP
GMS81C1408 8K bytes - 192bytes 2.2 ~ 5.5V 28 SKDIP or SOP
GMS87C1404 - 4K bytes 192bytes 2.5 ~ 5.5V 28 SKDIP or SOP
GMS87C1408 - 8K bytes 192bytes 2.5 ~ 5.5V 28 SKDIP or SOP
1.2 Features
• 4K/8K Bytes On-chip Program Memory • One 8-bit Serial Peripheral Interface
2. BLOCK DIAGRAM
Program
RESET System controller Memory
System 8-bit Basic
Clock Controller Interval Inte rrupt C ontroller Data Table
Timer
Timing generator
Xin
Clock Generator
Xout
Instruction
Decoder
8-bit 8-bit High Buzzer
Watch-dog A/D Timer/ Speed SPI
Timer Converter Counter PWM Driver
VDD
RA RB RC RD
VSS
Power
Supply
3. PIN ASSIGNMENT
28 SKINNY DIP
AN4 / RA4 1 28 RA3 / AN3
28 SOP
AN4 / RA4 1 28 RA3 / AN3
4. PACKAGE DIAGRAM
TYP 0.300
1.375
1.355 0.300
MIN 0.020
0.275
MAX 0.180
0.120
0.140
4
0.01
8
0.021 0.00
0.0 15 0.055 0 ~ 15°
TYP 0.100
0.045
28 SOP
0.293
0.299
0.414
0.398
0.708
0.608
0.006
0.012
0.106
0.096
0.019 0 ~ 8°
0.013 0.042
0.008
0.012
5. PIN FUNCTION
VDD: Supply voltage. RC3~RC6: RC is a 4-bit, CMOS, bidirectional I/O port.
RC pins can be used as outputs or inputs according to “1”
VSS: Circuit ground.
or “0” written the their Port Direction Register(RCIO).
RESET: Reset the MCU.
RC serves the functions of the serial interface following
XIN: Input to the inverting oscillator amplifier and input to special features in Table 5-3 .
the internal main clock operating circuit.
XOUT: Output from the inverting oscillator amplifier. Port pin Alternate function
RA0~RA7: RA is an 8-bit, CMOS, bidirectional I/O port. RC3 SRDYIN (SPI Ready Input)
SRDYOUT (SPI Ready Output)
RA pins can be used as outputs or inputs according to “1”
RC4 SCKI (SPI CLK Input)
or “0” written the their Port Direction Register(RAIO).
SCKO (SPI CLK Output)
RC5 SIN (SPI Serial Data Input)
Port pin Alternate function RC6 SOUT (SPI Serial Data Output)
RA0 EC0 ( Event Counter Input Source )
Table 5-3 RC Port
RA1 AN1 ( Analog Input Port 1 )
RA2 AN2 ( Analog Input Port 2 )
RA3 AN3 ( Analog Input Port 3 ) RD0~RD2: RD is a 3-bit, CMOS, bidirectional I/O port.
RA4 AN4 ( Analog Input Port 4 ) RC pins can be used as outputs or inputs according to “1”
RA5 AN5 ( Analog Input Port 5 ) or “0” written the their Port Direction Register(RDIO).
RA6 AN6 ( Analog Input Port 6 )
RD serves the functions of the external interrupt following
RA7 AN7 ( Analog Input Port 7 )
special features in Table 5-4
Table 5-1 RA Port
Port pin Alternate function
In addition, RA serves the functions of the various special RD0 INT2 (External Interrupt Input Port 2)
features in Table 5-1 . RD1 INT3 (External Interrupt Input Port 3)
RB0~RB7: RB is a 8-bit, CMOS, bidirectional I/O port. RD2
RB pins can be used as outputs or inputs according to “1”
Table 5-4 RD Port
or “0” written the their Port Direction Register(RBIO).
RB serves the functions of the various following special
features in Table 5-2
XOUT 20 O
6. PORT STRUCTURES
• RESET
Internal RESET
VSS
• Xin, Xout
VDD
Xout
VSS
STOP
• RA0/EC0
Data Reg.
Data Bus
Direction Reg.
Data Bus
Data Bus
Read
EC0
• RA1/AN1 ~ RA7/AN7
VDD
Data Reg.
Data Bus
Direction Reg.
Data Bus
VSS
Data Bus
Read
To A/D Converter
VDD
Data Reg.
Data Bus
AVREFS
Direction Reg.
Data Bus
VSS
Data Bus
Read
To A/D Converter
To Vref of A/D
0
AVREFS
PWM/COMP
BUZ,TMR2OV,SOUT VDD
1
Data Reg.
Data Bus 0
Function
Select Direction Reg.
Data Bus
VSS
Data Bus
Read
Pull-up
Select Weak Pull-up
Data Bus
Function
Select Direction Reg.
Data Bus
VSS
Data Bus
• RB6/EC1
Data Reg.
Data Bus
Direction Reg.
Data Bus
Data Bus
Read
EC1
• RD2
VDD
Data Reg.
Data Bus
Direction Reg.
Data Bus
VSS
Data Bus
Read
• RC5/SIN
Data Bus
Function
Select Direction Reg.
Data Bus
VSS
Data Bus
SRDYOUT
SCKOUT VDD
1
Data Reg.
Data Bus 0
Function
Select Direction Reg.
Data Bus
VSS
Data Bus
Specifications
Parameter Symbol Condition Unit
Min. Max.
fXIN=8MHz 4.5 5.5 V
Supply Voltage VDD
fXIN=4.2MHz 2.2 5.5 V
VDD=4.5~5.5V 1 8 MHz
Operating Frequency fXIN
VDD=2.2~5.5V 1 4.2 MHz
Operating Temperature TOPR -20 (-40 for GMS81C140XE) 85 °C
Specifications
Parameter Symbol Condition Unit
Min. Typ. Max.
AVREFS=0 VSS - VDD
Analog Input Voltage Range VAIN V
AVREFS=1 VSS - VREF
VDD=5V 3 - VDD V
Analog Power Supply Input Voltage Range VREF
VDD=3V 2.4 - VDD V
Overall Accuracy NACC - ±1.0 ±1.5 LSB
Non-Linearity Error NNLE - ±1.0 ±1.5 LSB
Differential Non-Linearity Error NDNLE - ±1.0 ±1.5 LSB
Zero Offset Error NZOE - ±0.5 ±1.5 LSB
Full Scale Error NFSE - ±0.25 ±0.5 LSB
Gain Error NNLE - ±1.0 ±1.5 LSB
fXIN=8MHz - - 10
Conversion Time TCONV µS
fXIN=4MHz - - 20
AVREF Input Current IREF AVREFS=1 - 0.5 1.0 mA
Specifications
Parameter Symbol Pin Condition Unit
Min. Typ. Max.
VIH1 XIN, RESET 0.8 VDD - VDD
Input High Voltage VIH2 Hysteresis Input1 0.8 VDD - VDD V
VIH3 Normal Input 0.7 VDD - VDD
VIL1 XIN, RESET 0 - 0.2 VDD
Input Low Voltage VIL2 Hysteresis Input1 0 - 0.2 VDD V
VIL3 Normal Input 0 - 0.3 VDD
Output High Voltage VOH All Output Port VDD=5V, IOH=-5mA VDD -1 - - V
Output Low Voltage VOL All Output Port VDD=5V, IOL=10mA - - 1 V
Input Pull-up Current IP RB2, RB3, RD0, RD1 VDD=5V -550 -320 -200 µA
7.5 AC Characteristics
(TA=-20~85°C for GMS81C1404/1408 or TA=-40~85°C for GMS81C1404E/1408E, VDD=5V±10%, VSS=0V)
Specifications
Parameter Symbol Pins Unit
Min. Typ. Max.
Operating Frequency fCP XIN 1 - 8 MHz
External Clock Pulse Width tCPW XIN 80 - - nS
External Clock Transition Time tRCP,tFCP XIN - - 20 nS
Oscillation Stabilizing Time tST XIN, XOUT - - 20 mS
INT0, INT1, INT2, INT3
External Input Pulse Width tEPW 2 - - tSYS
EC0, EC1
RESET Input Width tRST RESET 8 - - tSYS
tCPW tCPW
1/fCP
VDD-0.5V
XIN 0.5V
tRCP tFCP
tSYS
tRST
RESET
0.2VDD
tEPW tEPW
0.8VDD
INT0, INT1 0.2VDD
INT2, INT3
EC0, EC1
8
6
fXIN = 8MHz
6
4
4MHz
4
2
2
0 VDD
2 3 4 5 6 (V)
0 VDD
2 3 4 5 6 (V)
0.2 0.5
4MHz
0 VDD 0 VDD
2 3 4 5 6 (V) 2 3 4 5 6 (V)
15
10 TRCWDT = 80uS
0 VDD
2 3 4 5 6 (V)
30 -15
-10
20
10 -5
0 0 VOH
VOL
2 3 4 5 6 (V)
1 2 3 4 5 (V)
3 3 3
2 2 2
1 1 1
3 3 3
2 2 2
1 1 1
Specifications
Parameter Symbol Condition Unit
Min. Max.
fXIN=8MHz 4.5 5.5 V
Supply Voltage VDD
fXIN=4.2MHz 2.5 5.5 V
VDD=4.5~5.5V 1 8 MHz
Operating Frequency fXIN
VDD=2.5~5.5V 1 4.2 MHz
Operating Temperature TOPR -20 85 °C
Specifications
Parameter Symbol Condition Unit
Min. Typ. Max.
AVREFS=0 VSS - VDD
Analog Input Voltage Range VAIN V
AVREFS=1 VSS - VREF
VDD=5V 3 - VDD V
Analog Power Supply Input Voltage Range VREF
VDD=3V 2.4 - VDD V
Overall Accuracy NACC - ±1.0 ±1.5 LSB
Non-Linearity Error NNLE - ±1.0 ±1.5 LSB
Differential Non-Linearity Error NDNLE - ±1.0 ±1.5 LSB
Zero Offset Error NZOE - ±0.5 ±1.5 LSB
Full Scale Error NFSE - ±0.25 ±0.5 LSB
Gain Error NNLE - ±1.0 ±1.5 LSB
fXIN=8MHz - - 10
Conversion Time TCONV µS
fXIN=4MHz - - 20
AVREF Input Current IREF AVREFS=1 - 0.5 1.0 mA
Specifications
Parameter Symbol Pin Condition Unit
Min. Typ. Max.
VIH1 XIN, RESET 0.8 VDD - VDD
Input High Voltage VIH2 Hysteresis Input1 0.8 VDD - VDD V
VIH3 Normal Input 0.7 VDD - VDD
VIL1 XIN, RESET 0 - 0.2 VDD
Input Low Voltage VIL2 Hysteresis Input1 0 - 0.2 VDD V
VIL3 Normal Input 0 - 0.3 VDD
Output High Voltage VOH All Output Port VDD=5V, IOH=-5mA VDD -1 - - V
Output Low Voltage VOL All Output Port VDD=5V, IOL=10mA - - 1 V
Input Pull-up Current IP RB2, RB3, RD0, RD1 VDD=5V -550 -420 -200 µA
8.5 AC Characteristics
(TA=-20~+85°C, VDD=5V±10%, VSS=0V)
Specifications
Parameter Symbol Pins Unit
Min. Typ. Max.
Operating Frequency fCP XIN 1 - 8 MHz
External Clock Pulse Width tCPW XIN 80 - - nS
External Clock Transition Time tRCP,tFCP XIN - - 20 nS
Oscillation Stabilizing Time tST XIN, XOUT - - 20 mS
INT0, INT1, INT2, INT3
External Input Pulse Width tEPW 2 - - tSYS
EC0, EC1
RESET Input Width tRST RESET 8 - - tSYS
tCPW tCPW
1/fCP
VDD-0.5V
XIN 0.5V
tRCP tFCP
tSYS
tRST
RESET
0.2VDD
tEPW tEPW
0.8VDD
INT0, INT1 0.2VDD
INT2, INT3
EC0, EC1
8
6
fXIN = 8MHz
6
4
4MHz
4
2
2
0 VDD
2 3 4 5 6 (V)
0 VDD
2 3 4 5 6 (V)
0.2 0.5
4MHz
0 VDD 0 VDD
2 3 4 5 6 (V) 2 3 4 5 6 (V)
15
10 TRCWDT = 80uS
0 VDD
2 3 4 5 6 (V)
30 -15
-10
20
10 -5
0 0 VOH
VOL
2 3 4 5 6 (V)
1 2 3 4 5 (V)
3 3 3
2 2 2
1 1 1
3 3 3
2 2 2
1 1 1
9. MEMORY ORGANIZATION
The GMS81C1404 and GMS81C1408 have separate ad- to 4K /8K bytes of Program memory. Data memory can be
dress spaces for Program memory and Data Memory. Pro- read and written to up to 192 bytes including the stack area.
gram memory can only be read, not written to. It can be up
9.1 Registers
This device has six registers that are the Program Counter Generally, SP is automatically updated when a subroutine
(PC), a Accumulator (A), two index registers (X, Y), the call is executed or an interrupt is accepted. However, if it
Stack Pointer (SP), and the Program Status Word (PSW). is used in excess of the stack area permitted by the data
The Program Counter consists of 16-bit register. memory allocating configuration, the user-processed data
may be lost.
A ACCUMULATOR
The stack can be located at any position within 00H to BFH
X X REGISTER of the internal data memory. The SP is not initialized by
hardware, requiring to write the initial value (the location
Y Y REGISTER with which the use of the stack starts) by using the initial-
SP STACK POINTER ization routine. Normally, the initial value of “BFH” is
used.
PCH PCL PROGRAM COUNTER
Stack Address (000H ~ 0BFH)
PROGRAM STATUS
PSW WORD 15 8 7 0
0 SP
MSB LSB
BRK FLAG
INTERRUPT ENABLE FLAG
F000H
GMS81C1404 PROGRAM
The interrupt causes the CPU to jump to specific location,
MEMORY where it commences the execution of the service routine.
FEFFH The External interrupt 0, for example, is assigned to loca-
FF00H
tion 0FFFAH. The interrupt service locations spaces 2-byte
interval: 0FFF8H and 0FFF9H for External Interrupt 1,
FFC0H TCALL PCALL
AREA
0FFFAH and 0FFFBH for External Interrupt 0, etc.
FFDFH AREA
FFE0H INTERRUPT As for the area from 0FF00H to 0FFFFH, if any area of
FFFFH VECTOR AREA
them is not going to be used, its service location is avail-
able as general purpose Program Memory.
0FFE0H -
Page Call (PCALL) area contains subroutine program to E2 -
reduce program byte length by using 2 bytes PCALL in- E4 Serial Peripheral Interface Interrupt Vector Area
stead of 3 bytes CALL instruction. If it is frequently called, E6 Basic Interval Interrupt Vector Area
it is more useful to save program byte length. E8 Watchdog Timer Interrupt Vector Area
EA A/D Converter Interrupt Vector Area
Table Call (TCALL) causes the CPU to jump to each EC Timer/Counter 3 Interrupt Vector Area
TCALL address, where it commences the execution of the EE Timer/Counter 2 Interrupt Vector Area
service routine. The Table Call service area spaces 2-byte F0 External Interrupt 3 Vector Area
for every TCALL: 0FFC0H for TCALL15, 0FFC2H for F2 External Interrupt 2 Vector Area
TCALL14, etc., as shown in Figure 9-6 . F4 Timer/Counter 1 Interrupt Vector Area
F6 Timer/Counter 0 Interrupt Vector Area
F8 External Interrupt 1 Vector Area
FA External Interrupt 0 Vector Area
FC -
FE RESET Vector Area
NOTE:
“-” means reserved area.
0FFC0H
TCALL 15
C1
C2
TCALL 14
C3
C4
TCALL 13
Address PCALL Area Memory C5
C6
0FF00H TCALL 12
C7
C8
TCALL 11
C9
PCALL Area CA
TCALL 10
(256 Bytes) CB
CC
TCALL 9
CD
CE
TCALL 8
0FFFFH CF
D0
TCALL 7
D1
D2
TCALL 6
D3
D4
TCALL 5
D5
D6
TCALL 4
D7
D8
TCALL 3
D9
DA
TCALL 2
DB
DC
TCALL 1
DD
DE
TCALL 0 / BRK *
DF
NOTE:
* means that the BRK software interrupt is using
same address with TCALL0.
4A 01001010
4F
Reverse
35 ➊
~
~ ~
~
PC: 11111111 11010110
~
~ ~
~ 0F125H NEXT FH FH DH 6H
0FF00H
➌
0FF35H NEXT 0FF00H ➋
0FFD6H 25
0FFFFH 0FFD7H F1
0FFFFH
Example: The usage software example of Vector address and the initialize part.
ORG 0FFE0H
DW NOT_USED ; (0FFEO)
DW NOT_USED ; (0FFE2)
DW SPI_INT ; (0FFE4) Serial Peripheral Interface
DW BIT_INT ; (0FFE6) Basic Interval Timer
DW WDT_INT ; (0FFE8) Watchdog Timer
DW AD_INT ; (0FFEA) A/D
DW TMR3_INT ; (0FFEC) Timer-3
DW TMR2_INT ; (0FFEE) Timer-2
DW INT3 ; (0FFF0) Int.3
DW INT2 ; (0FFF2) Int.2
DW TMR1_INT ; (0FFF4) Timer-1
DW TMR0_INT ; (0FFF6) Timer-0
DW INT1 ; (0FFF8) Int.1
DW INT0 ; (0FFFA) Int.0
DW NOT_USED ; (0FFFC)
DW RESET ; (0FFFE) Reset
ORG 0F000H
;********************************************
; MAIN PROGRAM *
;*******************************************
;
RESET: DI ;Disable All Interrupts
LDX #0
RAM_CLR: LDA #0 ;RAM Clear(!0000H->!00BFH)
STA {X}+
CMPX #0C0H
BNE RAM_CLR
;
LDX #0BFH ;Stack Pointer Initialize
TXSP
;
CALL INITIAL ;
;
LDM RA, #0 ;Normal Port A
LDM RAIO,#1000_0010B ;Normal Port Direction
LDM RB, #0 ;Normal Port B
LDM RBIO,#1000_0010B ;Normal Port Direction
:
:
LDM PFDR,#0 ;Enable Power Fail Detector
:
:
1. “byte, bit” means that register can be addressed by not only bit
Stack Area
but byte manipulation instruction. The stack provides the area where the return address is
2. “byte” means that register can be addressed by only byte saved before a jump is performed during the processing
manipulation instruction. On the other hand, do not use any routine at the execution of a subroutine call instruction or
read-modify-write instruction such as bit manipulation for
clearing bit.
the acceptance of an interrupt.
When returning from the processing routine, executing the
subroutine return instruction [RET] restores the contents of
Note: Several names are given at same address. Refer to
the program counter from the stack; executing the interrupt
below table.
return instruction [RETI] restores the contents of the pro-
gram counter and flags.
When read When write The save/restore locations in the stack are determined by
Addr. Timer Capture PWM Timer PWM the stack pointed (SP). The SP is automatically decreased
Mode Mode Mode Mode Mode after the saving, and increased before the restoring. This
D1H T0 CDR0 - TDR0 - means the value of the SP indicates the stack location
number for the next save.
D3H - TDR1 T1PPR
D4H T1 CDR1 T1PDR - T1PDR
D7H T2 CDR2 - TDR2 -
D9H - TDR3 T3PPR
DAH T3 CDR3 T3PDR - T3PDR
ECH BITR CKCTLR
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
C0H RA RA Port Data Register
C1H RAIO RA Port Direction Register
C2H RB RB Port Data Register
C3H RBIO RB Port Direction Register
C4H RC RC Port Data Register
C5H RCIO RC Port Direction Register
C6H RD RD Port Data Register
C7H RDIO RD Port Direction Register
CAH RAFUNC ANSEL7 ANSEL6 ANSEL5 ANSEL4 ANSEL3 ANSEL2 ANSEL1 ANSEL0
CBH RBFUNC TMR2OV EC1I PWM1O PWM0O INT1I INT0I BUZO AVREFS
CCH PUPSEL - - - - PUPSEL3 PUPSEL2 PUPSEL1 PUPSEL0
CDH RDFUNC - - - - - - INT3I INT2I
D0H TM0 - - CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST
T0/TDR0/
D1H Timer0 Register / Timer0 Data Register / Capture0 Data Register
CDR0
D2H TM1 POL 16BIT PWM0E CAP1 T1CK1 T1CK0 T1CN T1ST
TDR1/
D3H Timer1 Data Register / PWM0 Period Register
T1PPR
T1/CDR1/
D4H Timer1 Register / Capture1 Data Register / PWM0 Duty Register
T1PDR
D5H PWM0HR PWM0 High Register
D6H TM2 - - CAP2 T2CK2 T2CK1 T2CK0 T2CN T2ST
T2/TDR2/
D7H Timer2 Register / Timer2 Data Register / Capture2 Data Register
CDR2
D8H TM3 POL 16BIT PWM1E CAP3 T3CK1 T3CK0 T3CN T3ST
TDR3/
D9H Timer3 Data Register / PWM1 Period Register
T3PPR
T3/CDR3/
DAH Timer3 Register / Capture3 Data Register / PWM1Duty Register
T3PDR
DBH PWM1HR PWM1 High Register
DEH BUR BUCK1 BUCK0 BUR5 BUR4 BUR3 BUR2 BUR1 BUR0
E0H SIOM POL SRDY SM1 SM0 SCK1 SCK0 SIOST SIOSF
E1H SIOR SPI DATA REGISTER
E2H IENH INT0E INT1E T0E T1E INT2E INT3E T2E T3E
E3H IENL ADE WDTE BITE SPIE - - - -
E4H IRQH INT0IF INT1IF T0IF T1IF INT2IF INT3IF T2IF T3IF
E5H IRQL ADIF WDTIF BITIF SPIF - - - -
E6H IEDS IED3H IED3L IED2H IED2L IED1H IED1L IED0H IED0L
0F035H data
E45535 LDM 35H,#55H ➋
~
~ ~
~ A+data+C → A
➊
0F100H 07
0F101H 35 address: 0F035
0035H data data ← 55H 0F102H F0
~
~ ~
~
➊ ➋
0F100H E4
0F101H 55
0F102H 35
The operation within data memory (RAM) X indexed direct page, auto increment→ {X}+
ASL, BIT, DEC, INC, LSR, ROL, ROR
In this mode, a address is specified within direct page by
Example; Addressing accesses the address 0135H. the X register and the content of X is increased by 1.
983500 INC !0035H ;A ←RAM[035H] LDA, STA
Example; X=35H
DB LDA {X}+
0035H data
➌
~
~ ~
~ ➋
data+1 → data
35H data ➋
0F100H 98 ➊
0F101H 35 ~ ~ data → A
address: 0035 ~ ~
0F102H 00 ➊ 36H → X
DB
D4 LDA {X} ;ACC←RAM[X]. ADC, AND, CMP, EOR, LDA, LDY, OR, SBC, STA
STY, XMA, ASL, DEC, INC, LSR, ROL, ROR
Example; X=015H
15H data
C645 LDA 45H+X
➋
~ ~ data → A
~ ~
➊
5AH data
0E550H D4
➌
~ ~ ➋ data → A
~ ~
0E550H C6 ➊
0E551H 45
45H+15H=5AH
Sets the value of 16-bit absolute address plus Y-register 0E30AH NEXT
data as Memory. This addressing mode can specify mem-
ory in whole area. ~
~ ~
~ ➊
Example; Y=55H 0FA00H 3F
0F100H D5
➊
0F101H 00 X indexed indirect → [dp+X]
0F102H FA 0FA00H+55H=0FA55H
Processes memory data as Data, assigned by 16-bit pair
~
~ ~
~ ➋ memory which is determined by pair data
[dp+X+1][dp+X] Operand plus X-register data in Direct
page.
0FA55H data data → A
➌ ADC, AND, CMP, EOR, LDA, OR, SBC, STA
Example; X=10H
1625 ADC [25H+X]
PROGRAM MEMORY
25H 05 0E025H 25
26H E0 0E026H E7
~
~ ~
~ ~
~ ~
~
0FA00H 0FA00H 1F
17
25 25
➌ A + data + C → A E0
RA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 PORT RAFUNC.7~0 Description
RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 - - - - PUP3 PUP2 PUP1 PUP0
Regardless of the direction register RBIO, RBFUNC is se- a corresponding alternate features.
lected to use as alternate functions, port pin can be used as
SIOM
PORT Function Description
SRDY SM [1:0] SCK [1:0]
INT3I INT2I
0 : RD0
1 : INT2
0 : RD1
1 : INT3
PRESCALER
STOP
WAKEUP
Peripheral clock
RCWDT
BTS[2:0]
÷8 3 BTCL To Watchdog Timer
÷ 16
÷ 32 Clear
fxin
÷ 64 8
0
÷ 128
MUX
Basic Interval Timer
÷ 256 BITR (8BIT) BITIF
Interrupt
÷ 512 1
÷ 1024
Internal RC OSC
ADDRESS : D0H
TM0 - - CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST RESET VALUE : --000000
- - 0 X X X X X
ADDRESS : D2H
TM1 POL 16BIT PWME CAP1 T1CK1 T1CK0 T1CN T1ST RESET VALUE : 00000000
X 0 0 0 X X X X
These timers have each 8-bit count register and data regis- (latched in T0F bit). As TDRx and Tx register are in same
ter. The count register is increased by every internal or ex- address, when reading it as a Tx, written to TDRx.
ternal clock input. The internal clock has a prescaler divide
In counter function, the counter is increased every 0-to 1
ratio option of 2, 4, 8, 32,128, 512, 2048 (selected by con-
(rising edge) transition of EC0 pin. In order to use counter
trol bits T0CK2, T0CK1 and T0CK0 of register TM0) and
function, the bit RA0 of the RA Direction Register RAIO
1, 2, 8 (selected by control bits T1CK1 and T1CK0 of reg-
is set to “0”. The Timer 0 can be used as a counter by pin
ister TM1). In the Timer 0, timer register T0 increases
EC0 input, but Timer 1 can not.
from 00H until it matches TDR0 and then reset to 00H. The
match output of Timer 0 generates Timer 0 interrupt
TDR1
n
n-1
~~ PCP
~~
9
nt
ou
8
-c
7
up
~~
6
5
4
3
2
1
0
TIME
Interrupt period
= PCP x (n+1)
Timer 1 (T1IF)
Interrupt
Occur interrupt Occur interrupt Occur interrupt
TDR1
disable enable
stop
oun
-c
up
~~
TIME
Timer 1 (T1IF)
Interrupt
Occur interrupt Occur interrupt
T1ST
Start & Stop
T1ST = 0 T1ST = 1
T1CN
Control count
T1CN = 0 T1CN = 1
ADDRESS : D0H
TM0 - - CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST RESET VALUE : --000000
- - 0 X X X X X
ADDRESS : D2H
TM1 POL 16BIT PWME CAP1 T1CK1 T1CK0 T1CN T1ST RESET VALUE : 00000000
X 1 0 0 1 1 X X
1
EC0 MUX T1 (8-bit) T0 (8-bit)
÷2 CLEAR
÷4
÷8
fxin ÷ 32 T0CN T0IF TIMER 0
÷ 128 COMPARATOR
INTERRUPT
÷ 512
÷ 2048 TDR1 (8-bit) TDR0 (8-bit)
F/F
COMP0 PIN
timer register T0 (T1) increases and matches TDR0 tured into registers CDRx (CDR0, CDR1), respectively.
(TDR1). After captured, Timer x register is cleared and restarts by
hardware.
This timer interrupt in capture mode is very useful when
the pulse width of captured signal is more wider than the It has three transition modes: “falling edge”, “rising edge”,
maximum period of Timer. “both edge” which are selected by interrupt edge selection
register IEDS (Refer to External interrupt section). In ad-
For example, in Figure 13-8 , the pulse width of captured
dition, the transition at INTx pin generate an interrupt.
signal is wider than the timer data value (FFH) over 2
times. When external interrupt is occurred, the captured
value (13H) is more little than wanted value. It can be ob- Note: The CDRx, TDRx and Tx are in same address. In
tained correct value by counting the number of timer over- the capture mode, reading operation is read the
CDRx, not Tx because path is opened to the CDRx,
flow occurrence.
and TDRx is only for writing operation.
Timer/Counter still does the above, but with the added fea-
ture that a edge transition at external input INTx pin causes
the current value in the Timer x register (T0,T1), to be cap-
ADDRESS : D0H
TM0 - - CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST RESET VALUE : --000000
- - 1 X X X X X
ADDRESS : D2H
TM1 POL 16BIT PWME CAP1 T1CK1 T1CK0 T1CN T1ST RESET VALUE : 00000000
X 0 0 1 X X X X
T0CK[2:0] T0ST
Edge Detector 0 : Stop
1 : Clear and Start
1
CLEAR
EC0 MUX T0 (8-bit)
÷2
÷4
÷8 T0IF TIMER 0
INTERRUPT
fxin ÷ 32 T0CN COMPARATOR
÷ 128
÷ 512 CAPTURE CDR0 (8-bit) TDR0 (8-bit)
÷ 2048
INT0IF INT 0
INTERRUPT
INT0 T0ST
0 : Stop
IEDS[1:0] 1 : Clear and Start
÷1 1
CLEAR
÷2 MUX T1 (8-bit)
÷8
T1IF TIMER 1
INTERRUPT
T1CN COMPARATOR
T1CK[1:0]
CAPTURE
INT1IF INT 1
INTERRUPT
INT1
~~
~~
9
nt
ou
8
-c
7
up
6
5
4
3
~~
2
1
0
TIME
Interrupt Request
(INT0F)
Interrupt Interval Period
Interrupt Request
(INT0F)
Delay
Interrupt Request
(INT0F)
Interrupt Interval Period = FFH + 01H + FFH +01H + 13H = 213H
Interrupt Request
(T0F)
FFH FFH
T0
13H
00H 00H
ADDRESS : D0H
TM0 - - CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST RESET VALUE : --000000
- - 1 X X X X X
ADDRESS : D2H
TM1 POL 16BIT PWME CAP1 T1CK1 T1CK0 T1CN T1ST RESET VALUE : 00000000
X 1 0 X 1 1 X X
X: The value “0” or “1” corresponding your operation.
T0CK[2:0] T0ST
Edge Detector 0 : Stop
1 : Clear and Start
1
CLEAR
EC0 MUX T0 + T1 (16-bit)
÷2
÷4
÷8 T0CN T0IF TIMER 0
INTERRUPT
fxin ÷ 32
COMPARATOR
÷ 128
÷ 512 CAPTURE CDR1 CDR0 TDR1 TDR0
÷ 2048 (8-bit) (8-bit) (8-bit) (8-bit)
INT0IF INT 0
INTERRUPT
INT0
IEDS[1:0]
If it needed more higher frequency of PWM, it should be It can be changed duty value when the PWM output. How-
reduced resolution. ever the changed duty value is output after the current pe-
riod is over. And it can be maintained the duty value at
Frequency present output when changed only period value shown as
Resolution
Figure 13-12 . As it were, the absolute duty time is not
T1CK[1:0] = T1CK[1:0] = T1CK[1:0] =
changed in varying frequency. But the changed period val-
00(125nS) 01(250nS) 10(1uS)
ue must greater than the duty value.
10-bit 7.8KHz 3.9KHz 0.98KHZ
9-bit 15.6KHz 7.8KHz 1.95KHz Note: If changing the Timer1(3) to PWM function, it
8-bit 31.2KHz 15.6KHz 3.90KHz should be stop the timer clock firstly, and then
set period and duty register value. If user
7-bit 62.5KHz 31.2KHz 7.81KHz writes register values while timer is in opera-
tion, these register could be set with certain
Table 13-2 PWM Frequency vs. Resolution at 8MHz values.
Ex) LDM TM1,#00H
The bit POL of TM1 decides the polarity of duty cycle. LDM T1PPR,#00H
LDM T1PDR,#00H
If the duty value is set same to the period value, the PWM LDM PWM0HR,#00H
output is determined by the bit POL (1: High, 0: Low). And LDM RBFUNC,#0001_1100B
if the duty value is set to “00H”, the PWM output is deter- LDM TM1,#1010_1011B
mined by the bit POL (1: Low, 0: High).
ADDRESS : D2H
TM1 POL 16BIT PW ME C A P1 T1C K 1 T1C K 0 T 1C N T 1S T RESET VALUE : 00000000
X 0 1 0 X X X X
ADDRESS : D5H
PWM0HR - - - - PW M 0HR3 PW M0HR2 PW M0HR1 PW M0HR0 RESET VALUE : ----0000
Bit Manipulation Not Available
- - - - X X X X
T1ST T1PPR(8-bit)
T0 clock source 0 : Stop
COMPARATOR
1 : Clear and Start
S Q RB4/
PWM0
CLEAR
1 R
MUX T1 (8-bit)
÷1 PWM0O
fxin ÷2 [RBFUNC.4]
÷8 COMPARATOR POL
T1CN
T1CK[1:0]
Slave T1PDR(8-bit)
PWM0HR[1:0]
Master T1PDR(8-bit)
~
~
~
~
fxin
~ ~
~
~
~ ~
T1 00 01 02 03 04 05 7F 80 81 3FF 00 01 02 03
~
~ ~
~
PWM
POL=1
~
~
~
~
PWM
POL=0
~
~
Duty Cycle [80H x 125nS = 16uS]
T 1 C K [1:0 ] = 10 (1 uS )
P W M 0 H R = 0 0H
T1PPR = 0EH
Write T1PPR to 0AH Period changed
T 1 P D R = 0 5H
Source
clock
T1 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 01 02 03 04 05 06 07 08 09 0A 01 02 03 04 05
PWM
POL=1
Period Cycle [0EH x 1uS = 14uS, 71KHz] Period Cycle [0AH x 1uS = 10uS, 100KHz]
Figure 13-12 Example of Changing the Period in Absolute Duty Cycle (@8MHz)
ADDRESS : E0H
SIOM POL SRDY SM1 SM0 SCK1 SCK0 SIOST SIOSF RESET VALUE : 00000001
POL Serial Clock Polarity Selection bit. SCK[1:0] Serial Clock Selection bits
0 : Data Transmission at falling edge 00 : fxin ÷ 4
(Received data latch at rising edge)
1 : Data Transmission at rising edge 01 : fxin ÷ 16
(Received data latch at falling edge) 10 : TMR2OV (Overflow of Timer 2)
11 : External Clock
SRDY Serial Ready Enable bit SIOST Serial Transmit Start bit
0 : Disable (RC3) 0 : Disable
1 : Enable (SRDYIN / SRDYOUT) 1 : Start (After one SCK, becomes “0”)
SM[1:0] Serial Operation Mode Selection bits SIOSF Serial Transmit Status bit
00 : Normal Port (RC4, RC5, RC6) 0 : During Transmission
01 : Transmit Mode (SCK, RC5, SOUT) 1 : Finished
10 : Receive Mode (SCK, SIN, RC6)
11 : Transmit & Receive Mode (SCK, SIN, SOUT)
ADDRESS : E1H
SIOR RESET VALUE : Undefined
SOUT
SIN SIOR
SM1
POL
00 fxin ÷4
01 fxin ÷ 16
SCK Polarity
10 TMR2OV
11 External Clock
SCK1
SCK0
2
SCK[1:0]
SM1
SM0
SRDY
R SIOST
SRDY Q
S From Control Circuit
To Control Circuit
The SPI allows 8-bits of data to be synchronously transmit- The serial data transfer operation mode is decided by set-
ted and received. To accomplish communication, typically ting the SM1 and SM0 of SPI Mode Control Register, and
three pins are used: the transfer clock rate is decided by setting the SCK1 and
SCK0 of SPI Mode Control Register as shown in Figure
- Serial Data In RC5/SIN
14-1 . And the polarity of transfer clock is selected by set-
- Serial Data Out RC6/SOUT
ting the POL.
- Serial Clock RC4/SCK
The bit SRDY is used for master / slave selection. If this
Additonarlly a fourth pin may be used when in a master or
bit is set to “1” and SCK[1:0] is set to “11”, the controller
a slave mode of operation:
is performed to slave controller. As it were, the port RC3
- Serial Transfer Ready RC3/SRDYIN/SRDYOUT is served for SRDYOUT.
SIOST
SCK
(POL=1)
SCK
(POL=0)
SOUT D0 D1 D2 D3 D4 D5 D6 D7
SIN D0 D1 D2 D3 D4 D5 D6 D7
SPIF
(SPI Int. Req)
SRDY
SIOST
SCK
(POL=1)
SCK
(POL=0)
SOUT D0 D1 D2 D3 D4 D5 D6 D7
SIN D0 D1 D2 D3 D4 D5 D6 D7
SPIF
(SPI Int. Req)
ADDRESS : DEH
BUR BUCK1 BUCK0 BUR5 BUR4 BUR3 BUR2 BUR1 BUR0 RESET VALUE : 11111111
Bit Manipulation Not Available
Input clock selection Buzzer Period Data
00 : fxin ÷ 8
01 : fxin ÷ 16
10 : fxin ÷ 32
11 : fxin ÷ 64
÷8
÷ 16
fxin MUX COUNTER (6-bit)
÷ 32
÷ 64
F/F
COMPARATOR
BUCK[1:0]
RB1/BUZ PIN
BUZO
BUR (6-bit) [RBFUNC.1]
ADS[2:0]
111
RA7/AN7
ANSEL7
110
RA6/AN6
A/D Result Register
ANSEL6
101 ADDRESS : EBH
RA5/AN5 ADCR(8-bit)
RESET VALUE : Undefined
ANSEL5
100
RA4/AN4 Sample & Hold
ANSEL2 Resistor
001 Ladder
RA1/AN1 Circuit
ANSEL1
000
RB0/AN0/AVref
ANSEL0 (RAFUNC.0)
VDD Pin 0
ADEN
AVREFS (RBFUNC.0)
Reserved
A/D Status bit
Analog Channel Select
0 : A/D Conversion is in process
000 : Channel 0 (RB0/AN0) 1 : A/D Conversion is completed
001 : Channel 1 (RA1/AN1)
A/D Start bit
010 : Channel 2 (RA2/AN2) 1 : A/D Conversion is started
011 : Channel 3 (RA3/AN3) After 1 cycle, cleared to “0”
100 : Channel 4 (RA4/AN4) 0 : Bit force to zero
101 : Channel 5 (RA5/AN5)
110 : Channel 6 (RA6/AN6)
111 : Channel 7 (RA7/AN7)
ADSF = 1 Analog
NO Input AN0~AN7
YES 100~1000pF
READ ADCR
(3) Pins AN0/RB0 and AN1/RA1 to AN7/RA7 noise. Therefore, avoid applying pulses to pins adjacent to
the pin undergoing A/D conversion.
The analog input pins AN0 to AN7 also function as input/
output port (PORT RA and RB0) pins. When A/D conver- (4) AVref pin input impedance
sion is performed with any of pins AN0 to AN7 selected,
A series resistor string of approximately 10KΩ is connected be-
be sure not to execute a PORT input instruction while con-
tween the AVref pin and the VSS pin.
version is in progress, as this may reduce the conversion
resolution. Therefore, if the output impedance of the reference voltage
source is high, this will result in parallel connection to the
Also, if digital pulses are applied to a pin adjacent to the
series resistor string between the AVref pin and the VSS pin, and
pin in the process of A/D conversion, the expected A/D
there will be a large reference voltage error.
conversion value may not be obtainable due to coupling
17. INTERRUPTS
The GMS81C1404 and GMS81C1408 interrupt circuits erated it is cleared by the hardware when the service rou-
consist of Interrupt enable register (IENH, IENL), Inter- tine is vectored to only if the interrupt was transition-
rupt request flags of IRQH, IRQL, Interrupt Edge Selec- activated.
tion Register (IEDS), priority circuit and Master enable
The Timer 0, Timer 1, Timer 2 and Timer 3 Interrupts are
flag(“I” flag of PSW). The configuration of interrupt cir-
generated by T0IF, T1IF, T2IF and T3IF, which are set by
cuit is shown in Figure 17-1 and Interrupt priority is shown
a match in their respective timer/counter register. The AD
in Table 17-1 .
converter Interrupt is generated by ADIF which is set by
The External Interrupts INT0, INT1, INT2 and INT3 can finishing the analog to digital conversion. The Watch dog
each be transition-activated (1-to-0, 0-to-1 and both transi- timer Interrupt is generated by WDTIF which set by a
tion). match in Watch dog timer register (when the bit WDTON
is set to “0”). The Basic Interval Timer Interrupt is gener-
The flags that actually generate these interrupts are bit
ated by BITIF which is set by a overflowing of the Basic
INT0IF, INT1IF, INT2IF and INT3IF in Register IRQH.
Interval Timer Register(BITR).
When an external interrupt is generated, the flag that gen-
7
External Int. 0 INT0IF
IEDS
External Int. 1 6
INT1IF
Timer 0 T0IF
5
Release STOP
Timer 1 4
T1IF
3
External Int. 2 INT2IF
Priority Control
IEDS
External Int. 3 2 To CPU
INT3IF
Timer 2 T2IF
1
I Flag
Timer 3 0
T3IF Interrupt Master
Enable Flag
ADIF 7 Interrupt
A/D Converter
Vector
WDT 6 Address
WDTIF
Generator
BIT 5
BITIF
SPI 5
SPIF
When an interrupt is occurred, the I-flag is cleared and dis- The interrupt request flag bit(s) must be cleared by soft-
able any further interrupt, the return address and PSW are ware before re-enabling interrupts to avoid recursive inter-
pushed into the stack and the PC is vectored to. Once in the rupts. The Interrupt Request flags are able to be read and
interrupt service routine the source(s) of the interrupt can written.
be determined by polling the interrupt request flag bits.
System clock
Instruction Fetch
Data Bus Not used PCH PCL PSW V.L. ADL ADH OP code
Internal Read
Internal Write
Figure 17-3 Timing chart of Interrupt Acceptance and Interrupt Return Instruction
The following method is used to save/restore the general- General-purpose register save/restore using push and pop
purpose registers. instructions;
Example: Register save using push and pop instructions
RETI RET
:
:
:
enable INT0 LDM IENH,#0FFH ;Enable all interrupts
enable other LDM IENL,#0F0H
POP Y
POP X
POP A
RETI
INT1 INTERRUPT
:
:
ADDRESS : EDH
WDTR WDTCL 7-bit Watchdog Counter Register RESET VALUE : 01111111
Bit Manipulation Not Available
RCWDT
BTS[2:0]
÷8 3
WDTR (8-bit)
÷ 512 1 0
÷ 1024 Overflow Detection
Watchdog Timer
Interrupt Request
BITIF Basic Interval Timer
Internal RC OSC
Interrupt
Oscillator
(XIN pin)
~
~
~ ~
~ ~
Internal
Clock
~
~
External
~
~
Interrupt
~
~
BIT
N-2 N-1 N N+1 N+2 00 01 FE FF 00 00
Counter
~
~
STOP Mode
~
~
Oscillator
(XIN pin)
~~
~ ~
~ ~
Internal
Clock
~ ~
~
~
~
~
RESET
Internal
~
~
RESET
~
~
STOP Instruction Execution
Stabilizing Time
Time can not be control by software tST = 64mS @4MHz
~
~
Oscillator
(XIN pin)
~
~
~
~
Internal
RC Clock
~
~
Internal
Clock
~
~
External ~
Interrupt
~
~
~
(or WDT Interrupt)
STOP Instruction Execution Clear Basic Interval Timer
~
~
BIT
N-2 N-1 N N+1 N+2 00 01 FE FF 00 00
Counter
~
~
Normal Operation STOP Mode Stabilizing Time Normal Operation
tST > 20mS
Figure 19-4 STOP Mode Releasing by External Interrupt or WDT Interrupt(using RCWDT)
STOP Mode
~
~
Oscillator
(XIN pin)
~
~
~
~
Internal
RC Clock
~
~
Internal
Clock
~
~
RESET
~
~
~
~
RESET by WDT
Internal
~
~
RESET
~
~
Oscillator
(XIN pin)
~ ~
~ ~
CPU
Clock
STOP Instruction
Execution
Interrupt
~
~
Request
Normal Operation Wake-up Timer Mode Normal Operation
(stop the CPU clock) Do not need Stabilizing Time
Figure 19-6 Wake-up Timer Mode Releasing by External Interrupt or Timer0(Timer2) Interrupt
VDD
INPUT PIN
INPUT PIN VDD VDD
internal
pull-up i=0
VDD
OPEN
O
O i
i
Very weak current flows
VDD
GND
X i=0 GND
X
Weak pull-up current flows
OPEN
O
O When port is configure as an input, input level should
be closed to 0V or 5V to avoid power consumption.
OFF
O OFF i ON i=0
i
ON
X X O
OFF In the left case, Tr. base current flows from port to GND.
O To avoid power consumption, there should be low output
to the port.
20. RESET
The reset input is the RESET pin, which is the input to a Internal RAM is not affected by reset. When VDD is turned
Schmitt Trigger. A reset in accomplished by holding the on, the RAM content is indeterminate. Therefore, this
RESET pin low for at least 8 oscillator periods, while the RAM should be initialized before reading or testing it.
oscillator running. After reset, 64ms (at 4 MHz) add with
Initial state of each register is shown as Table 9-1 .
7 oscillator periods are required to start execution as shown
in Figure 20-1 .
1 2 3 4 5 6 7
~
~
Oscillator
(XIN pin)
RESET ~
~
~
~
DATA ? OP
? ? ? FE ADL ADH
BUS
~
~
MAIN PROGRAM
RESET Process Step
Stabilizing Time
tST = 64mS at 4MHz
Reserved
Power Fail Status
0 : Normal Operate
1 : This bit force to “1” when
Power fail was detected
Operation Mode
0 : System Clock Freeze during power fail
1 : MCU will be reset during power fail
Disable Flag
0 : Power fail detection enable
1 : Power fail detection disable
RESET VECTOR
YES
PFS =1
NO
RAM CLEAR
INITIALIZE RAM DATA Skip the
initial routine
FUNTION
EXECUTION
VDD
PFVDDMAX
PFVDDMIN
64mS
Internal
RESET
VDD PFVDDMAX
When PFDM = 1 PFVDDMIN
Internal 64mS
t < 64mS
RESET
VDD
PFVDDMAX
PFVDDMIN
64mS
Internal
RESET
VDD
PFVDDMAX
PFVDDMIN
System
Clock
When PFDM = 0
VDD PFVDDMAX
PFVDDMIN
System
Clock
0F50H
ID 0F50H
DEVICE
CONFIGURATION ID 0F60H
AREA
ID 0F70H
Configuration Register
0FF0H ID 0F80H
CONFIG
ID 0F90H
PFD
ID 0FA0H - - - - - LOCK LEVEL - ADDRESS : 0FF0H
ID 0FB0H
PFD Level Select
ID 0FC0H
0 : PFD Level High (2.5~3.5V)
ID 0FD0H 1 : PFD Level Low (2.0~3.0V)
A_D4 1 28 A_D3
A_D5 2 27 A_D2
A_D6 3 26 A_D1
A_D7 4 25 A_D0
VDD 5 24
CTL0 6 23
CTL1 7 22 VSS
CTL2 8 21 VPP
9 20 NC
10 19 EPROM Enable
11 18
12 17
13 16
14 15
~
~
EPROM
~
~
Enable
TVPPS VIHP
~
~
~
~
VPP TVPPR
TVDDS
CTL0 0V
~
~ ~
~ ~
~
VDD1H
~
0V TCD1 TCD1
CTL1
VDD1H ~
~ TCD1
~
~
TCD1
CTL2 0V
~
~
~
~
A_D7~ DATA DATA
HA LA DATA IN LA DATA IN
A_D0 OUT OUT
~
~
~~
VDD1H
VDD
High 8bit Low 8bit Write Mode Verify Low 8bit Write Mode Verify
Address Address Address
Input Input Input
EPROM
Enable
TVPPS VIHP
CTL0 0V
VDD2H
0V TCD2 TCD2
CTL1
VDD2H
TCD1
TCD1
CTL2 0V
A_D7~
HA LA DATA LA DATA HA LA DATA
A_D0
VDD2H
VDD
High 8bit Low 8bit DATA Low 8bit DATA High 8bit Low 8bit DATA
Address Address Output Address Output Address Address Output
Input Input Input Input Input
START
Set VDD=VDD1H
END
NO
EPROM Write YES
100uS program time Verify pass
NO
Verify pass
YES
NO
Last address
YES
START
Set VPP=VIHP
NO
Last address
YES
Report Read OK
VDD=0V
VPP=0V
END
A. INSTRUCTION MAP
LOW 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111
HIGH 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
SET1 BBS BBS ADC ADC ADC ADC ASL ASL TCALL SETA1 BIT POP PUSH
000 - BRK
dp.bit A.bit,rel dp.bit,rel #imm dp dp+X !abs A dp 0 .bit dp A A
SBC SBC SBC SBC ROL ROL TCALL CLRA1 COM POP PUSH BRA
001 CLRC
#imm dp dp+X !abs A dp 2 .bit dp X X rel
CMP CMP CMP CMP LSR LSR TCALL NOT1 TST POP PUSH PCALL
010 CLRG
#imm dp dp+X !abs A dp 4 M.bit dp Y Y Upage
OR OR OR OR ROR ROR TCALL OR1 CMPX POP PUSH
011 DI RET
#imm dp dp+X !abs A dp 6 OR1B dp PSW PSW
AND AND AND AND INC INC TCALL AND1 CMPY CBNE INC
100 CLRV TXSP
#imm dp dp+X !abs A dp 8 AND1B dp dp+X X
EOR EOR EOR EOR DEC DEC TCALL EOR1 DBNE XMA DEC
101 SETC TSPX
#imm dp dp+X !abs A dp 10 EOR1B dp dp+X X
LDA LDA LDA LDA LDY TCALL LDC LDX LDX
110 SETG TXA XCN DAS
#imm dp dp+X !abs dp 12 LDCB dp dp+Y
LDM STA STA STA STY TCALL STC STX STX
111 EI TAX XAX STOP
dp,#imm dp dp+X !abs dp 14 M.bit dp dp+Y
LOW 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111
HIGH 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F
BPL CLR1 BBC BBC ADC ADC ADC ADC ASL ASL TCALL JMP BIT ADDW LDX JMP
000
rel dp.bit A.bit,rel dp.bit,rel {X} !abs+Y [dp+X] [dp]+Y !abs dp+X 1 !abs !abs dp #imm [!abs]
BVC SBC SBC SBC SBC ROL ROL TCALL CALL TEST SUBW LDY JMP
001
rel {X} !abs+Y [dp+X] [dp]+Y !abs dp+X 3 !abs !abs dp #imm [dp]
BCC CMP CMP CMP CMP LSR LSR TCALL TCLR1 CMPW CMPX CALL
010 MUL
rel {X} !abs+Y [dp+X] [dp]+Y !abs dp+X 5 !abs dp #imm [dp]
BNE OR OR OR OR ROR ROR TCALL DBNE CMPX LDYA CMPY
011 RETI
rel {X} !abs+Y [dp+X] [dp]+Y !abs dp+X 7 Y !abs dp #imm
BMI AND AND AND AND INC INC TCALL CMPY INCW INC
100 DIV TAY
rel {X} !abs+Y [dp+X] [dp]+Y !abs dp+X 9 !abs dp Y
BVS EOR EOR EOR EOR DEC DEC TCALL XMA XMA DECW DEC
101 TYA
rel {X} !abs+Y [dp+X] [dp]+Y !abs dp+X 11 {X} dp dp Y
BCS LDA LDA LDA LDA LDY LDY TCALL LDA LDX STYA
110 XAY DAA
rel {X} !abs+Y [dp+X] [dp]+Y !abs dp+X 13 {X}+ !abs dp
BEQ STA STA STA STA STY STY TCALL STA STX CBNE
111 XYX NOP
rel {X} !abs+Y [dp+X] [dp]+Y !abs dp+X 15 {X}+ !abs dp
B. INSTRUCTION SET
1. ARITHMETIC/ LOGIC OPERATION
OP BYTE CYCLE FLAG
NO. MNEMONIC OPERATION
CODE NO NO NVGBHIZC
1 ADC #imm 04 2 2 Add with carry.
2 ADC dp 05 2 3 A←(A)+(M)+C
3 ADC dp + X 06 2 4
4 ADC !abs 07 3 4 NV--H-ZC
5 ADC !abs + Y 15 3 5
6 ADC [ dp + X ] 16 2 6
7 ADC [ dp ] + Y 17 2 6
8 ADC { X } 14 1 3
9 AND #imm 84 2 2 Logical AND
10 AND dp 85 2 3 A← (A)∧(M)
11 AND dp + X 86 2 4
12 AND !abs 87 3 4 N-----Z-
13 AND !abs + Y 95 3 5
14 AND [ dp + X ] 96 2 6
15 AND [ dp ] + Y 97 2 6
16 AND { X } 94 1 3
17 ASL A 08 1 2 Arithmetic shift left
18 ASL dp 09 2 4 C 7 6 5 4 3 2 1 0 N-----ZC
19 ASL dp + X 19 2 5
“0”
20 ASL !abs 18 3 5
21 CMP #imm 44 2 2 Compare accumulator contents with memory contents
22 CMP dp 45 2 3 (A) -(M)
23 CMP dp + X 46 2 4
24 CMP !abs 47 3 4 N-----ZC
25 CMP !abs + Y 55 3 5
26 CMP [ dp + X ] 56 2 6
27 CMP [ dp ] + Y 57 2 6
28 CMP { X } 54 1 3
29 CMPX #imm 5E 2 2 Compare X contents with memory contents
30 CMPX dp 6C 2 3 (X)-(M) N-----ZC
31 CMPX !abs 7C 3 4
32 CMPY #imm 7E 2 2 Compare Y contents with memory contents
33 CMPY dp 8C 2 3 (Y)-(M) N-----ZC
34 CMPY !abs 9C 3 4
35 COM dp 2C 2 4 1’S Complement : ( dp ) ← ~( dp ) N-----Z-
36 DAA DF 1 3 Decimal adjust for addition N-----ZC
37 DAS CF 1 3 Decimal adjust for subtraction N-----ZC
38 DEC A A8 1 2 Decrement N-----Z-
39 DEC dp A9 2 4 M← (M)-1
40 DEC dp + X B9 2 5 N-----Z-
41 DEC !abs B8 3 5
42 DEC X AF 1 2
43 DEC Y BE 1 2
44 DIV 9B 1 12 Divide : YA / X Q: A, R: Y NV--H-Z-
3. 16-BIT OPERATION
OP BYTE CYCLE FLAG
NO. MNEMONIC OPERATION NVGBHIZC
CODE NO NO
16-Bits add without carry
1 ADDW dp 1D 2 5 NV--H-ZC
YA ← ( YA ) + ( dp +1 ) ( dp )
4. BIT MANIPULATION
OP BYTE CYCLE FLAG
NO. MNEMONIC OPERATION
CODE NO NO NVGBHIZC
1 AND1 M.bit 8B 3 4 Bit AND C-flag : C ← ( C ) ∧ ( M .bit ) -------C
2 AND1B M.bit 8B 3 4 Bit AND C-flag and NOT : C ← ( C ) ∧ ~( M .bit ) -------C
3 BIT dp 0C 2 4 Bit test A with memory : MM----Z-
4 BIT !abs 1C 3 5 Z ← ( A ) ∧ ( M ) , N ← ( M7 ) , V ← ( M6 )
5 CLR1 dp.bit y1 2 4 Clear bit : ( M.bit ) ← “0” --------
6 CLRA1 A.bit 2B 2 2 Clear A bit : ( A.bit )← “0” --------
7 CLRC 20 1 2 Clear C-flag : C ← “0” -------0
8 CLRG 40 1 2 Clear G-flag : G ← “0” --0-----
9 CLRV 80 1 2 Clear V-flag : V ← “0” -0--0---
10 EOR1 M.bit AB 3 5 Bit exclusive-OR C-flag : C ← ( C ) ⊕ ( M .bit ) -------C
11 EOR1B M.bit AB 3 5 Bit exclusive-OR C-flag and NOT : C ← ( C ) ⊕ ~(M .bit) -------C
12 LDC M.bit CB 3 4 Load C-flag : C ← ( M .bit ) -------C
13 LDCB M.bit CB 3 4 Load C-flag with NOT : C ← ~( M .bit ) -------C
14 NOT1 M.bit 4B 3 5 Bit complement : ( M .bit ) ← ~( M .bit ) --------
15 OR1 M.bit 6B 3 5 Bit OR C-flag : C ← ( C ) ∨ ( M .bit ) -------C
16 OR1B M.bit 6B 3 5 Bit OR C-flag and NOT : C ← ( C ) ∨ ~( M .bit ) -------C
17 SET1 dp.bit x1 2 4 Set bit : ( M.bit ) ← “1” --------
18 SETA1 A.bit 0B 2 2 Set A bit : ( A.bit ) ← “1” --------
19 SETC A0 1 2 Set C-flag : C ← “1” -------1
20 SETG C0 1 2 Set G-flag : G ← “1” --1-----
21 STC M.bit EB 3 6 Store C-flag : ( M .bit ) ← C --------
Test and clear bits with A :
22 TCLR1 !abs 5C 3 6 N-----Z-
A - ( M ) , ( M ) ← ( M ) ∧ ~( A )
Test and set bits with A :
23 TSET1 !abs 3C 3 6 N-----Z-
A-(M), (M)← (M)∨(A)
11 2F 2 4 Branch always
BRA rel --------
pc ← ( pc ) + rel
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