Buses

• There are a number of possible interconnection systems

• Single and multiple BUS structures are most common

• e.g. Control/Address/Data bus (PC)

• e.g. Unibus (DEC-PDP)

What is a Bus?

• A communication pathway connecting two or more devices

• Usually broadcast

• Often grouped

— A number of channels in one bus

— e.g. 32 bit data bus is 32 separate single bit channels

• Power lines may not be shown

Data Bus

• Carries data

— Remember that there is no difference between “data” and “instruction” at this

level

• Width is a key determinant of performance

— 8, 16, 32, 64 bit

Address bus

• Identify the source or destination of data

• e.g. CPU needs to read an instruction (data) from a given location in memory

• Bus width determines maximum memory capacity of system

— e.g. 8080 has 16 bit address bus giving 64k address space

Control Bus

• Control and timing information

— Memory read/write signal

 — Interrupt request

— Clock signals

Bus Interconnection Scheme

Physical Realization of Bus Architecture

Single Bus Problems

If large number of devices are connected to the single shared bus , performance will suffer.
There are following problems
1>Bus length is longer. Therefore propagaton time is more. This propagation dealy can affect
performance. When control of the bus passes from one device to another frequently

2>The bus may become bottleneck as aggreagate data transfer demand approaches the
capacity of bus. Because data rate generated by attached deviceslike graphics and video
controller are growing rapidly

3>Only one master bus can operate at a time, other waits. To overcome this problem most
computer system use multiple buses, generally laid out in hierarchy.

Figure shows some typical example of I/O devices that might be attached to expansion devices
The traditional bus connection uses three buses local bus , system bus and expansion bus

1. Local bus connects the processor to cache memory and may support one or more local
devices

2. The cache memory controller connects the cache to local bus and to the system bus.

3. System bus also connects main memory module

4. Input /output transfer to and from the main memory across the system bus do not interface
with the processor activity because process accesses cache memory.
5. It is possible to connect I/O controllers directly on to the system bus. A more efficient solution
is to make use of one or more expansion buses for this purpose.An expansion bus interface
buffers data transfer between system bus and i/o controller on the expansion bus.

This arrangement allows the system to support a wide variety of i/o devices and at the same
time insulate memory to process or traffic from i/o traffic.

Bus design parameter

Before designing a bus there are some few parameters like
1. Type : Dedicated or multiplexed
2. Arbitration : Centralized or distributed
3. Timing ; Synchronous or Asynchronus
4. Bus width ; Address or data
5. Data Transfer Type ; R, W, Read, Modify Write, after write, block
Bus Design Parameter in details
1. Bus Type :
i) Dedicated bus:
When a bus is permanently assigned only 1 functiion , it is called dedicated bus.
E.g. separate address and data lines separate bus for memory and I/O modules
Advantages: It gives high performance and less bus contention
Disadvantages : Increased size and cost.

ii) Multiplexed bus:

When the bus is used for more than 1 funcion in different time zones it is called multiplexed bus.
E.g. 8085 microprocessor outputs A7- A0 in first clock cycles on pins. AD7 – AD0.
Advantages ; few pins lines are required . less cost and save space
Disadvantages: slow in speed
2. Bus Arbitration:
Several bus master connected to a common bus may require access to the same bus at the
same time. A selection mechanism called bus arbitration describes which device should be
given access to the bus

i) In Centralized approach; A hardware device called bus controller or bus arbiter allocates bus.
It uses one of the following type
(1) Daisy chaining
(2) Polling
(3) Multiple priority levels

ii) In Distributed Approach: each master has arbiter compared to only single in centralized
approach. Equal responsibility is given to all devices to carry out arbitration process, without
using a central arbiter
3. Bus Timing: In synchronous timing ,e very event is synchronized by clock whereas in
asynchronous every event occurring depends on previous events of bus .

4. Bus width: It decides the number of lines to be used for address and data. More addrss lines
means more memory can be accessed e.g 16 line address make 2 16 = 64 kb , 20 address line
makes 220 = 1 mb memory access .
More data lines means more number of bits can be transferred at a time. Therefore speed
increases.
5. Data transfer type; A bus can support various type of data transfer
1) For multiplexed bus

a) Write operation : data is outputted immediately outputting address

b) Read operation: First address is outputted then sufficient acces s time is given gto address
device to output data. Now data is read from bus
c) Read , modify write; Read data transfer is followed by write data transfer at the same
address. It stop other cpu to use bus.
d) Read after write; Writer transfer is followed with read transfer after some access time . it is
used for checking purpose.
e) Block operation; number of data are transferred at the same address one after another e.g.
saving file in secondary storage.

2) For non-multiplexed bus :

Address and data outputted at the same time on different bus. It is faster system.
PCI
The Peripheral Component Interconnect is an interconnect bus developed by Intel in 1992
which runs at 33 MHz and supports plug-and-play . It allows high speed connection between
peripherals, and from the peripherals to the processor.It Allows for transfer of data amongst
peripherals

independently of the processor. It is found on many desktops, but not limited to them.The PCI
bus is a 32 bit wide bus capable of transferring at data rates up to 132 MBytes per second. A
66 MHz, 64-bit version is capable of transfer
rates of up to 524 Mbytes/second.