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3. Implementing Logic in CMOS
J. A. Abraham
Department
60 of Electrical and Computer Engineering
The University of Texas at Austin
EE 382M, VLSI I
Fall 2010
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September 13, 2010
ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 1 / 30
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ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 1 / 30
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ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 2 / 30
mm F = (A40
Example: · B) + (C · 60
D) 80 100 120
1 Take uninverted function F = (A · B) + (C · D) and derive
N-network
2 Identify AN D, OR components: F is OR of AB, CD
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3 Make connections of transistors
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ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 3 / 30
4 Construct P-network
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taking complement of
N-expression (AB + CD),
which gives the
expression,
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(A + B) · (C + D)
5 Combine P and N circuits
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ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 4 / 30
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AND-OR-INVERT (AOI) gate
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F = (A + B + C) · D)
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Note:
N- and P- graphs are duals of each
other
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In this case, the function is the
complement of the switching
function between F and GND
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Question: Does it make any
difference to the function if the
transistor with input D is connected
between the parallel A, B, C,
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transistors and GND?
What about the electrical behavior?
ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 6 / 30
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OU T = (A + B) · (C + D) · (E + F + (G · H))
ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 7 / 30
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ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 8 / 30
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ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 9 / 30
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F = a·b+a·b+a·c+c·d+a·b
ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 10 / 30
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G=
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ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 11 / 30
Signal Strength
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Voltages represent digital logic values
Strength of signal:
How close it approximates ideal voltage
V40DD and GN D rails are strongest 1 and 0
nMOS transistors pass a strong 0
But degraded or weak 1
pMOS transistors pass a strong 1
60 But degraded or weak 0
ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 12 / 30
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ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 13 / 30
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“Pull-Up” Circuit
Used to restore degraded logic 1 from output of nMOS pass
transistor
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ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 14 / 30
Group
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similar transistors, 60 can be in80the same well
so they 100 120
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ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 15 / 30
Tristates
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Non-Restoring Tristate
Transmission gate acts as a tristate buffer
Only two transistors, but nonrestoring
Noise
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ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 16 / 30
Tristate Inverter
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ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 17 / 30
Multiplexers
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S D1 D0 Y
0 X 0 0
0 X 1 1
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1 0 X 0
1 1 X 1
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ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 18 / 30
Nonrestoring
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Uses two transmission
gates =⇒ only 4
transistors
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Inverting MUX – adds an inverter
Uses compound gate AOI22
Alternatively, a pair of tristate inverters (same thing)
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ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 19 / 30
4:1 Multiplexer
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ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 20 / 30
D Latch
Basicmm
Memory Element
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When CLK = 1, latch is transparent
D flows through to Q like a buffer
When CLK = 0, the latch is opaque
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a.k.a., transparent latch or level-sensitive latch
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ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 21 / 30
D Latch, Cont’d
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D Latch Design: 40 60 80 100 120
MUX chooses
between D and
old Q
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D Latch
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Operation
ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 22 / 30
D Flip-Flop (D-Flop)
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ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 23 / 30
D Flip-Flop Operation
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ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 24 / 30
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Back-to-back flops can malfunction from clock skew
Second flip-flop fires late
Sees first flip-flop change and captures its result
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Called hold-time failure or race condition
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ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 25 / 30
Non-Overlapping Clocks
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ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 26 / 30
Gate Layout
ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 27 / 30
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mmTrack is the
Wiring 40 space 60 Example,
80 well spacing:
100 wells 120
required for a wire must surround transistors by
Example, 4λ width, 4λ spacing 6λ
from neighbor = 8λ pitch Implies 12λ between opposite
Transistors
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also consume one transistor flavors
wiring track Leaves room for one wire track
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ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 29 / 30
Estimate
mmarea by counting
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wiring tracks Sketch a stick diagram and estimate
Multiply by 8 to express in λ area
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ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 30 / 30