Professional Documents
Culture Documents
DataSheet
Table of Contents
Page 2 Design Criteria
Page 11 Deliverables
Page 12 Guidelines
Page 18 Appendix A
Page 20 Appendix B
© Copyright 2003 ParthusCeva. All rights reserved. All other trademarks are the property of their respective owners. DISCLAIMER: the information is provided "as is" without any express or implied
warranty of any kind including warranties of merchantability, non-infringement of intellectual property, or fitness for any particular purpose. In no event shall ParthusCeva or its suppliers be liable for any
damages whatsoever arising out of the use of or inability to use the materials. ParthusCeva and its suppliers further do not warrant the accuracy or completeness of the information, text, graphics or other
items contained within these materials. ParthusCeva may make changes to these materials, or to the products described therein, at any time without notice.
Page 1 of 23
PLLXpert Clock Synthesis IP
DataSheet
Design Details
© Copyright 2003 ParthusCeva. All rights reserved. All other trademarks are the property of their respective owners. DISCLAIMER: the information is provided "as is" without any express or implied
warranty of any kind including warranties of merchantability, non-infringement of intellectual property, or fitness for any particular purpose. In no event shall ParthusCeva or its suppliers be liable for any
damages whatsoever arising out of the use of or inability to use the materials. ParthusCeva and its suppliers further do not warrant the accuracy or completeness of the information, text, graphics or other
items contained within these materials. ParthusCeva may make changes to these materials, or to the products described therein, at any time without notice.
Page 2 of 23
PLLXpert Clock Synthesis IP
DataSheet
Block Diagram
This is a general block diagram which indicates that up to 10 possible output dividers, xClk01 to xClk10, can be used. This
particular PLL design contains 3 output divider(s). The output divider value(s), X, pertinent to this PLL design are indicated
in the pin description on the following page.
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warranty of any kind including warranties of merchantability, non-infringement of intellectual property, or fitness for any particular purpose. In no event shall ParthusCeva or its suppliers be liable for any
damages whatsoever arising out of the use of or inability to use the materials. ParthusCeva and its suppliers further do not warrant the accuracy or completeness of the information, text, graphics or other
items contained within these materials. ParthusCeva may make changes to these materials, or to the products described therein, at any time without notice.
Page 3 of 23
PLLXpert Clock Synthesis IP
DataSheet
Pin Descriptions
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warranty of any kind including warranties of merchantability, non-infringement of intellectual property, or fitness for any particular purpose. In no event shall ParthusCeva or its suppliers be liable for any
damages whatsoever arising out of the use of or inability to use the materials. ParthusCeva and its suppliers further do not warrant the accuracy or completeness of the information, text, graphics or other
items contained within these materials. ParthusCeva may make changes to these materials, or to the products described therein, at any time without notice.
Page 4 of 23
PLLXpert Clock Synthesis IP
DataSheet
Electrical Performance
© Copyright 2003 ParthusCeva. All rights reserved. All other trademarks are the property of their respective owners. DISCLAIMER: the information is provided "as is" without any express or implied
warranty of any kind including warranties of merchantability, non-infringement of intellectual property, or fitness for any particular purpose. In no event shall ParthusCeva or its suppliers be liable for any
damages whatsoever arising out of the use of or inability to use the materials. ParthusCeva and its suppliers further do not warrant the accuracy or completeness of the information, text, graphics or other
items contained within these materials. ParthusCeva may make changes to these materials, or to the products described therein, at any time without notice.
Page 5 of 23
PLLXpert Clock Synthesis IP
DataSheet
Jitter Information
TDj is the total deterministic jitter and TRj is the total random jitter. Total deterministic jitter, TDj, for the PLL, may be
computed from the following equation
DjI, intrinsic deterministic jitter, is stated in Table 2. TDjVdd, the total deterministic jitter due to VDD noise, may be
computed from the following equation
DjVdd, deterministic jitter due to VDD noise, is stated in Table 2.Vnoise is the amplitude of the (pllVdd/pllVddCore) VDD
noise (expressed in mV) present in the system.
TDjRef, total deterministic jitter due to reference clock jitter, may be computed from the following equation
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warranty of any kind including warranties of merchantability, non-infringement of intellectual property, or fitness for any particular purpose. In no event shall ParthusCeva or its suppliers be liable for any
damages whatsoever arising out of the use of or inability to use the materials. ParthusCeva and its suppliers further do not warrant the accuracy or completeness of the information, text, graphics or other
items contained within these materials. ParthusCeva may make changes to these materials, or to the products described therein, at any time without notice.
Page 6 of 23
PLLXpert Clock Synthesis IP
DataSheet
Aref is the amplitude of the jitter on the reference clock (peak-peak, expressed in ps), and fmod is the rate (frequency) at
which the jitter is occurring. Tref is the period of the reference clock and Tvco is the period of the VCO clock. The gain at
fmod can be estimated from the transfer function and converted from dB to absolute gain before applying in [Equ 5] as
`gain(fmod)'. Total random jitter, TRj, for the PLL must be computed in the context of the reliability of the system being
designed. TRj can be computed from the following equation.
Rj, the random jitter sigma, is stated in Table 2. Total period jitter, TPj, defines a region where a clock edge is to occur.
The question for the designer is how often can an edge occur outside this defined region? If the answer is 3 in every 1000
edges then the percentage reliability required is at least 99.7%. Using Table 3 the appropriate number of sigma,
NumberOfSigma, is 6. TPj can be computed from the following equation.
For a reliability of 99.9999998% or 2 in every 1e9 edges then the relevant equation is
For a commonly used error rate in communications of 1 in every 1e12 edges the requirement for the random component is
14*Rj. Clearly the more reliable the system the greater the number of Rj's included in the equation for TPj. Table 3 shows
Rj versus reliability. (Note Rj is denoted by σ in Table 3
When computing the TPj on an output clock other than the VCO clock, convert the Rjx value for the output clock to an Rj
value using the following equation
© Copyright 2003 ParthusCeva. All rights reserved. All other trademarks are the property of their respective owners. DISCLAIMER: the information is provided "as is" without any express or implied
warranty of any kind including warranties of merchantability, non-infringement of intellectual property, or fitness for any particular purpose. In no event shall ParthusCeva or its suppliers be liable for any
damages whatsoever arising out of the use of or inability to use the materials. ParthusCeva and its suppliers further do not warrant the accuracy or completeness of the information, text, graphics or other
items contained within these materials. ParthusCeva may make changes to these materials, or to the products described therein, at any time without notice.
Page 7 of 23
PLLXpert Clock Synthesis IP
DataSheet
Rj = Rjx/(Fout*100) Equ 7
where Fout is the frequency of the output clock, expressed in Hz. (The resulting Rj will be in units of ps) The TPj can the
be computed using the equations given above.Refer to Appendix B.1 for a sample period jitter calculation.
Note 5 Phase skew between the reference clock and the VCO clock
To compute the worst case phase skew, PS, between the reference clock and the VCO clock, the user must complete the
following calculations. (Note: PS is the magnitude of the phase skew. The reference clock may lead or lag the VCO clock
by this amount)
Spo, the static phase offset, is stated in Table 2 and PSdyn is the dynamic phase skew PSdyn may be computed from the
following equation
DriftI is stated in Table 2. TDtrRef is a measure of the PLL's ability to track a determinsitic modulations on the reference
clock. This may be computed from the following equation
DtrRef(f) is a measure of the PLL's ability to track a modulation on the reference clock occurring at a frequency, f. This
may be computed from the transfer function shown in Fig 2 and the following equation
Aref is the amplitude of the modulation on the reference clock (peak-peak, expressed in ps), and fmod is the rate
(frequency) at which the modulation is occurring. The gain at fmod can be estimated from the transfer function and
converted from dB to absolute gain before applying in [Equ 11] as `gain(fmod)'. Refer to Appendix A.2 for a sample phase
skew calculation.
© Copyright 2003 ParthusCeva. All rights reserved. All other trademarks are the property of their respective owners. DISCLAIMER: the information is provided "as is" without any express or implied
warranty of any kind including warranties of merchantability, non-infringement of intellectual property, or fitness for any particular purpose. In no event shall ParthusCeva or its suppliers be liable for any
damages whatsoever arising out of the use of or inability to use the materials. ParthusCeva and its suppliers further do not warrant the accuracy or completeness of the information, text, graphics or other
items contained within these materials. ParthusCeva may make changes to these materials, or to the products described therein, at any time without notice.
Page 8 of 23
PLLXpert Clock Synthesis IP
DataSheet
Waveforms Plot
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warranty of any kind including warranties of merchantability, non-infringement of intellectual property, or fitness for any particular purpose. In no event shall ParthusCeva or its suppliers be liable for any
damages whatsoever arising out of the use of or inability to use the materials. ParthusCeva and its suppliers further do not warrant the accuracy or completeness of the information, text, graphics or other
items contained within these materials. ParthusCeva may make changes to these materials, or to the products described therein, at any time without notice.
Page 9 of 23
PLLXpert Clock Synthesis IP
DataSheet
GDS Layout
This image has been generated from the GDS II layout for your entered design.
Measured from the top left-hand corner of the pll below the horizontal dimension is
606.9 µm and the vertical dimension is 543.1 µm
© Copyright 2003 ParthusCeva. All rights reserved. All other trademarks are the property of their respective owners. DISCLAIMER: the information is provided "as is" without any express or implied
warranty of any kind including warranties of merchantability, non-infringement of intellectual property, or fitness for any particular purpose. In no event shall ParthusCeva or its suppliers be liable for any
damages whatsoever arising out of the use of or inability to use the materials. ParthusCeva and its suppliers further do not warrant the accuracy or completeness of the information, text, graphics or other
items contained within these materials. ParthusCeva may make changes to these materials, or to the products described therein, at any time without notice.
Page 10 of 23
PLLXpert Clock Synthesis IP
DataSheet
Deliverables
© Copyright 2003 ParthusCeva. All rights reserved. All other trademarks are the property of their respective owners. DISCLAIMER: the information is provided "as is" without any express or implied
warranty of any kind including warranties of merchantability, non-infringement of intellectual property, or fitness for any particular purpose. In no event shall ParthusCeva or its suppliers be liable for any
damages whatsoever arising out of the use of or inability to use the materials. ParthusCeva and its suppliers further do not warrant the accuracy or completeness of the information, text, graphics or other
items contained within these materials. ParthusCeva may make changes to these materials, or to the products described therein, at any time without notice.
Page 11 of 23
PLLXpert Clock Synthesis IP
DataSheet
Guidelines
Layout
The GDS II produced by PLLXpert has been tested for compliance with the following DRC and LVS Decks, to which
ParthusCeva have applied the modifications as outlined in Appendix A.
• DRC CalibreDrc_0.18um_logic_salicide_1.8V/3.3V_1P6M_V2.3a
• LVS CalibreLvs_0.18um_logic_salicide_1.8V/3.3V_1P6M_V1.9d
When integrating the PLL GDSII into a higher level design the following basic guidelines should be considered.
• It is recommended that the PLL should be manually located into the higher level assembly and should be placed close to
the edge of the chip and as close as possible to the reference clock. Placing the PLL close to the reference clock reduces
the possibility of any noise or jitter being picked up by the reference clock before it enters the PLL.
• The ParthusCeva PLL uses 4 metals. The LEF file indicates metal blocking up to 6 metal layers. This is done to prevent
unwanted noisy tracks running over the PLL. If less than 6-metals are being used then the upper blocking layers should be
ignored. If more than 6 metals are being used metal blocking should be enabled on these layers also.
• The pllVdd and the pllGnd pins are located on the guard band that encloses the PLL. A dedicated PLL power supply
pllVdd should be connected at this location. The line connections between pllGnd and pllVdd should be constrained to
have a resistance of less than 1. If possible double bond pllVdd and pllGnd from the pads to the package pins. Avoid IR
drops in the supply.
• The guard band has been designed to provide isolation for the PLL from any adjacent circuitry. This isolation should be
sufficient such that no additional spacing outside the guard band should be required when placing adjacent circuits.
• It is recommended that non-epi material be used.
Routing
If using 2 or more output clocks from the PLL block then care must be taken not to route these clocks too close together
over a long distance otherwise capacitive coupling between metal tracks will cause crosstalk. Recomended separation
distance is at least 1µm. Figure 5 below describes a routing method for the case where all 10 output dividers are used and
its necessary to route the inner 5 output dividers out through the narrow routing channel allocated in the lef file.
© Copyright 2003 ParthusCeva. All rights reserved. All other trademarks are the property of their respective owners. DISCLAIMER: the information is provided "as is" without any express or implied
warranty of any kind including warranties of merchantability, non-infringement of intellectual property, or fitness for any particular purpose. In no event shall ParthusCeva or its suppliers be liable for any
damages whatsoever arising out of the use of or inability to use the materials. ParthusCeva and its suppliers further do not warrant the accuracy or completeness of the information, text, graphics or other
items contained within these materials. ParthusCeva may make changes to these materials, or to the products described therein, at any time without notice.
Page 12 of 23
PLLXpert Clock Synthesis IP
DataSheet
Applications
Programmable Dividers
The Programmable Divider option enables eight bit control of the input and feedback dividers. These dividers can be set to
any integer divider ratio from 1 to 256. The dividers can be programmed via an eight bit register. To set a divider ratio of N
the divider bus must be set to N-1. For example to set a divider ratio of 1 the register should be programmed to 00000000
and for a ratio of 256 the register should be programmed to 11111111.
It should be noted that no hard limits for the divider ratios are established in any delivered GDSII. Thus divider ratios are
selectable which may drive the PLL outside of its specified design range. It is the responsibility of the user to ensure that
any controlling program is designed to limit the range of selectable divider ratios to those that maintain PLL operation
within the specified design range
It should be noted that these these dividers should always be configured while the porL input to the PLL is low.If using an
on-chip register to store divider values do not use sysResetL as the reset on this register, use porL
Table 4 contains an illustration of the divider settings for a number of PLL configurations. In this example it is assumed that
a PLL has been designed using the following design criteria.
From the design specifications for the ParthusCeva IP we can identify that the design has the following frequency
capabilities.
Example 1 in Table 4 illustrates a nominal configuration achieved by selecting divider ratios that allow for operation of the
PLL at the center frequency of both the Ref Clock and the VCO.
Example 2 in Table 4 illustrates a configuration that exercises the lower design limit of the VCO frequency range by
selecting a feedback divider ratio of 40.
Example 3 in Table 4 illustrates a configuration that clearly exceeds the lower design limit of the VCO frequency range
when a feedback divider ratio of 30 is selected without making any compensating adjustment to the Reference Clock or
Input Divider Ratio. Whilst it is the case that ParthusCeva PLLs exhibit a soft degradation characteristic outside the
specified design range, performance is not guaranteed under such conditions.
Example 4 in Table 4 illustrates a configuration that takes advantage of the flexible input frequency range using an above
center 35 MHz Ref Clock but maintains the VCO center frequency by selecting a different set of divider ratios to that used
in Example 1.
© Copyright 2003 ParthusCeva. All rights reserved. All other trademarks are the property of their respective owners. DISCLAIMER: the information is provided "as is" without any express or implied
warranty of any kind including warranties of merchantability, non-infringement of intellectual property, or fitness for any particular purpose. In no event shall ParthusCeva or its suppliers be liable for any
damages whatsoever arising out of the use of or inability to use the materials. ParthusCeva and its suppliers further do not warrant the accuracy or completeness of the information, text, graphics or other
items contained within these materials. ParthusCeva may make changes to these materials, or to the products described therein, at any time without notice.
Page 13 of 23
PLLXpert Clock Synthesis IP
DataSheet
Ex No ErefClk Input ( M ) Input Register PFD Frequency Feedback Feedback Register VCO
ratio ( N ) ratio Frerquency
1 30 MHz 5 (4)00000100 6 MHz 50 (49)00110001 300 MHz
2 30 MHz 5 (4)00000100 6 MHz 40 (39)00100111 240 MHz
3 30 MHz 5 (4)00000100 6 MHz 30 (29)00011101 180 MHz
4 35 MHz 7 (6)00000110 5 MHz 60 (59)00111011 300 MHz
5 35 MHz 7 (6)00000110 5 MHz 75 (74)01001010 375 MHz
6 35 MHz 7 (6)00000110 5 MHz 90 (89)01011001 450 MHz
Table 4. Example Feedback divider settings
PLLLock signal
(Note : pfdClk = refClk/InputDivider and fbClk = vcoClk/FeedbackDivider)
The output signal "pllLock" goes high when the phase frequency detector indicates lock for 32 consecutive cycles of the
pfdClk. The phase frequency detector indicates lock when the pfdClk and the fbClk are within 15.0ns of each other.
The "sysResetL" signal goes high on the third positive edge of the slowest clock after "pllLock" is first set. It will not
deassert if "pllLock" subsequently indicates loss of lock. "sysResetL" is only cleared if it gets "porL" or "sleepL".
Deskew Delay
In order to avoid instability there is a maximum deskew delay that can be introduced into the feedback path between
VCOOut and VCODelayed. If a deskew PLL has deskew selected then the value of the Maximum deskew delay Mdd is
stated in table 2
© Copyright 2003 ParthusCeva. All rights reserved. All other trademarks are the property of their respective owners. DISCLAIMER: the information is provided "as is" without any express or implied
warranty of any kind including warranties of merchantability, non-infringement of intellectual property, or fitness for any particular purpose. In no event shall ParthusCeva or its suppliers be liable for any
damages whatsoever arising out of the use of or inability to use the materials. ParthusCeva and its suppliers further do not warrant the accuracy or completeness of the information, text, graphics or other
items contained within these materials. ParthusCeva may make changes to these materials, or to the products described therein, at any time without notice.
Page 14 of 23
PLLXpert Clock Synthesis IP
DataSheet
1) In this example, the delay through the clkTreeBuffer has been deskewed by placing it in the feedback path. The rising
edge of refClk and the rising edge of VCODelayed will be aligned.
2) In this example, the delay through the on-chip buffer 'b1' has been deskewed by placing a matching buffer 'b2' in the
feedback path. The rising edge of extRefClk and the rising edge of VCOOut will be aligned.
3) In this example, both the on-chip buffer 'b2' and the clkTreeBuffer have been deskewed by placing them in the feedback
path. The rising edge of refClk and the rising edge of the clkToChip will be aligned.
The user should use note [3], Phase skew between the reference clock and the VCO clock, to determine the quality of the
alignment.
Note the pllLock indication does not guarantee that the deskew spec is met. If the user requires an indicator for when the
PLL is within the deskew spec then a counter approximately 1000.00µs long should be built. This counter will begin
counting when pllLock goes high.
When implementing this delay buffer ensure that minimal jitter is added to the VCODelayed signal by having fast transition
times and a clean supply for the buffer.
If the user has selected programmable dividers and wishes to deskew to an output clock other than the VCO clock, then
the user may do so with the following requirements and limitations.
1) The appropriate output clock must tied to VCODelayed via the required delay.
2) The feedback divider bus FBD must be set using the following equation
FBD = (N/X)-1
where N is the required feedback divider ratio and X is the divide ratio of the output divider. A limitation of this equation is
that N must be an integer multiple of X.
© Copyright 2003 ParthusCeva. All rights reserved. All other trademarks are the property of their respective owners. DISCLAIMER: the information is provided "as is" without any express or implied
warranty of any kind including warranties of merchantability, non-infringement of intellectual property, or fitness for any particular purpose. In no event shall ParthusCeva or its suppliers be liable for any
damages whatsoever arising out of the use of or inability to use the materials. ParthusCeva and its suppliers further do not warrant the accuracy or completeness of the information, text, graphics or other
items contained within these materials. ParthusCeva may make changes to these materials, or to the products described therein, at any time without notice.
Page 15 of 23
PLLXpert Clock Synthesis IP
DataSheet
© Copyright 2003 ParthusCeva. All rights reserved. All other trademarks are the property of their respective owners. DISCLAIMER: the information is provided "as is" without any express or implied
warranty of any kind including warranties of merchantability, non-infringement of intellectual property, or fitness for any particular purpose. In no event shall ParthusCeva or its suppliers be liable for any
damages whatsoever arising out of the use of or inability to use the materials. ParthusCeva and its suppliers further do not warrant the accuracy or completeness of the information, text, graphics or other
items contained within these materials. ParthusCeva may make changes to these materials, or to the products described therein, at any time without notice.
Page 16 of 23
PLLXpert Clock Synthesis IP
DataSheet
Licensees of these platforms include 3Com, Agilent, Cirrus Logic, Fujitsu, HP, Hitachi, Motorola, National Semiconductor,
Nvidia, STMircoelectronics, Texas Instruments, and Sharp Microelectronics
The Clock Synthesis Block design featured in this datasheet is based on a design that has been verified by testing and
simulation using the ParthusCeva generic test chip. An evaluation report on the test chip is available and can be
downloaded by Registered Users from the pllxpert.com website.
The standard clock synthesis blocks available from PLLXpert Online can be licensed on an individual pay as you use basis
or, depending on your anticipated annual demand, can be licensed in sets of 5 or 10. For further details of licensing fees
and conditions please contact your nearest local representative who's details are provided below.
Custom and semi-custom variants of the standard designs can also be supplied and will be quoted on request.
ParthusCeva. (Europe)
Building 2,
University Technology Park,
Curraheen Road,
Bishopstown,
Cork,
Ireland.
tel: +353 21 480 1900
fax: +353 21 480 1901
ParthusCeva. (USA)
2033 Gateway Place,
Suite 150,
San Jose.
CA 95110-1002.
tel: +1 408 514 2900
fax: +1 408 514
ParthusCeva. (Asia/Pacific)
801 Stanhope House,
738 King's Road,
Hong Kong.
tel: + 852 2590 6881
fax: + 852 2590 6977
Global e-mail
•pllxpert@parthusceva.com
•pll@parthusceva.com
© Copyright 2003 ParthusCeva. All rights reserved. All other trademarks are the property of their respective owners. DISCLAIMER: the information is provided "as is" without any express or implied
warranty of any kind including warranties of merchantability, non-infringement of intellectual property, or fitness for any particular purpose. In no event shall ParthusCeva or its suppliers be liable for any
damages whatsoever arising out of the use of or inability to use the materials. ParthusCeva and its suppliers further do not warrant the accuracy or completeness of the information, text, graphics or other
items contained within these materials. ParthusCeva may make changes to these materials, or to the products described therein, at any time without notice.
Page 17 of 23
PLLXpert Clock Synthesis IP
DataSheet
Appendix A
drc.template
LAYOUT PATH "TOPCELLNAME.gds"
LAYOUT PRIMARY "TOPCELLNAME"
LAYOUT SYSTEM GDSII
INCLUDE "../newest_rules.drc"
extract.template
LAYOUT PATH "TOPCELLNAME.gds"
LAYOUT PRIMARY "TOPCELLNAME"
LAYOUT ERROR ON INPUT YES
LAYOUT SYSTEM GDSII
INCLUDE "../newest_rules.lvs"
compare.template
LAYOUT SYSTEM SPICE
LAYOUT CASE YES
LAYOUT PATH "TOPCELLNAME.ext"
LAYOUT PRIMARY "TOPCELLNAME"
© Copyright 2003 ParthusCeva. All rights reserved. All other trademarks are the property of their respective owners. DISCLAIMER: the information is provided "as is" without any express or implied
warranty of any kind including warranties of merchantability, non-infringement of intellectual property, or fitness for any particular purpose. In no event shall ParthusCeva or its suppliers be liable for any
damages whatsoever arising out of the use of or inability to use the materials. ParthusCeva and its suppliers further do not warrant the accuracy or completeness of the information, text, graphics or other
items contained within these materials. ParthusCeva may make changes to these materials, or to the products described therein, at any time without notice.
Page 18 of 23
PLLXpert Clock Synthesis IP
DataSheet
TRACE PROPERTY MP W W 0
TRACE PROPERTY MP L L 0
TRACE PROPERTY MN W W 0
TRACE PROPERTY MN L L 0
TRACE PROPERTY D A A 0
TRACE PROPERTY R R R 0.5
TRACE PROPERTY C C C 0
© Copyright 2003 ParthusCeva. All rights reserved. All other trademarks are the property of their respective owners. DISCLAIMER: the information is provided "as is" without any express or implied
warranty of any kind including warranties of merchantability, non-infringement of intellectual property, or fitness for any particular purpose. In no event shall ParthusCeva or its suppliers be liable for any
damages whatsoever arising out of the use of or inability to use the materials. ParthusCeva and its suppliers further do not warrant the accuracy or completeness of the information, text, graphics or other
items contained within these materials. ParthusCeva may make changes to these materials, or to the products described therein, at any time without notice.
Page 19 of 23
PLLXpert Clock Synthesis IP
DataSheet
Appendix B
Period Jitter
An example calculation of total period jitter. The example PLL is specified in Table B.1. The transfer function for this
example PLL is shown on Figure B.1. The example system, that the PLL resides in, is specified as follows
The example application requires a reliability of no more than 1 in every 10000 clock edges occurring outside the defined
jitter region.
© Copyright 2003 ParthusCeva. All rights reserved. All other trademarks are the property of their respective owners. DISCLAIMER: the information is provided "as is" without any express or implied
warranty of any kind including warranties of merchantability, non-infringement of intellectual property, or fitness for any particular purpose. In no event shall ParthusCeva or its suppliers be liable for any
damages whatsoever arising out of the use of or inability to use the materials. ParthusCeva and its suppliers further do not warrant the accuracy or completeness of the information, text, graphics or other
items contained within these materials. ParthusCeva may make changes to these materials, or to the products described therein, at any time without notice.
Page 20 of 23
PLLXpert Clock Synthesis IP
DataSheet
gain(f1) = 10(0/20) 1
© Copyright 2003 ParthusCeva. All rights reserved. All other trademarks are the property of their respective owners. DISCLAIMER: the information is provided "as is" without any express or implied
warranty of any kind including warranties of merchantability, non-infringement of intellectual property, or fitness for any particular purpose. In no event shall ParthusCeva or its suppliers be liable for any
damages whatsoever arising out of the use of or inability to use the materials. ParthusCeva and its suppliers further do not warrant the accuracy or completeness of the information, text, graphics or other
items contained within these materials. ParthusCeva may make changes to these materials, or to the products described therein, at any time without notice.
Page 21 of 23
PLLXpert Clock Synthesis IP
DataSheet
Phase Skew
The example PLL is specified in table B.1. The transfer function for this example PLL is shown on Fig B.1. The example
system, that the PLL resides in, is specified as follows
© Copyright 2003 ParthusCeva. All rights reserved. All other trademarks are the property of their respective owners. DISCLAIMER: the information is provided "as is" without any express or implied
warranty of any kind including warranties of merchantability, non-infringement of intellectual property, or fitness for any particular purpose. In no event shall ParthusCeva or its suppliers be liable for any
damages whatsoever arising out of the use of or inability to use the materials. ParthusCeva and its suppliers further do not warrant the accuracy or completeness of the information, text, graphics or other
items contained within these materials. ParthusCeva may make changes to these materials, or to the products described therein, at any time without notice.
Page 22 of 23
PLLXpert Clock Synthesis IP
DataSheet
© Copyright 2003 ParthusCeva. All rights reserved. All other trademarks are the property of their respective owners. DISCLAIMER: the information is provided "as is" without any express or implied
warranty of any kind including warranties of merchantability, non-infringement of intellectual property, or fitness for any particular purpose. In no event shall ParthusCeva or its suppliers be liable for any
damages whatsoever arising out of the use of or inability to use the materials. ParthusCeva and its suppliers further do not warrant the accuracy or completeness of the information, text, graphics or other
items contained within these materials. ParthusCeva may make changes to these materials, or to the products described therein, at any time without notice.
Page 23 of 23