Professional Documents
Culture Documents
1uF
Chip Shutdown
To System 3 8
CHG_S EN Chip Enable
4 PGOOD 6
To System ISETA
5,
GND RSET
Exposed Pad (11)
OVP
Comparator
2.5V +
Charge Input OVP
-
GND Selection
SENSE ACIN
FET PFET
ISETA BATT
2.5V VREF
Thermal Precharge
0.5V + Comparator
Sense
+
115 C - Precharge
V/I 2.5V -
0.25V
2.5V
Recharge
-
+
Comparator
V/I +
Recharge
2.5V -
0.25V
2.5V
Current VCC
Amplifier Precharge
Voltage
+ Amplifier
Tcrmination PGOOD
Comparator -
- Charge Done Logic
0.25V +
Charge
0.9V - Disable CHG_S
+
1uA
EN
www.richtek.com DS9513-00 July 2008
2
RT9513
Table
RT9513 Flow Chart
ACIN
Power Up
DISABLE MODE
V EN > 1.4V ? YES P-MOSFET OFF
DISABLE
IBATT = 0
NO
IBATT = 0
NO
SLEEP MODE
V ACIN < V BATT ? YES P-MOSFET OFF
IBATT = 0
SLEEP
NO
1ms Delay
Start-Up
V TS > 2.5V
or RECHARGE
V TS < 0.5V?
NO
IBATT = Charge
Current
/CHG_S Pull Down
YES STANDBY
PFET OFF V BATT > 4.1 V?
NO
V BATT = 4.2V,
IBATT = 0
YES
NO
V BATT ~ 4.2V,
IBATT < 0.1 ICHG?
Electrical Characteristics
(ACIN = 5V, TA = 27°C, Unless Otherwise specification)
To be continued
Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. Devices are ESD sensitive. Handling precaution is recommended.
Note 3. The device is not guaranteed to function outside its operating conditions.
Note 4. θJA is measured in the natural convection at TA = 25°C on a high effective thermal conductivity test board (4 layers, 1S)
of JEDEC 51-7 thermal measurement standard. The case point of θJC is on the expose pad for the WDFN package.
VACIN VACIN
(5V/Div) (5V/Div)
VBATT VBATT
(2V/Div) (2V/Div)
CHG_S CHG_S
(5V/Div) (5V/Div)
I CHARGE I CHARGE
(0.5A/Div) (0.5A/Div)
VBATT = 3.7V VBATT = 3.7V
V OUT
V OUT
VACIN VBATT
(5V/Div) (2V/Div)
V IN V IN
VACIN
VBATT
(5V/Div)
(2V/Div)
CHG_S
CHG_S (5V/Div)
(5V/Div)
I CHARGE I CHARGE
(0.5A/Div) (0.5A/Div) ACIN = 5V to 8V to 5V, VBATT = 3.7V
ACIN = 0V to 10V, VBATT = 3.7V
VACIN VACIN
(5V/Div) (5V/Div)
CHG_S CHG_S
(5V/Div) (5V/Div)
I CHARGE I CHARGE
(1A/Div) (1A/Div)
VBATT = 3.7V VBATT = 3.7V
Layout Consideration
The RT9513 is a fully integrated low cost single-cell Li- Ion battery charger ideal for portable applications. Careful PCB
layout is necessary. For best performance, place all peripheral components as close to the IC as possible. A short
connection is highly recommended. The following guidelines should be strictly followed when designing a PCB layout
for the RT9513.
` Input capacitor should be placed close to IC and connected to ground plane. The trace of input in the PCB should be
placed far away the sensitive devices or shielded by the ground.
` The GND should be connected to a strong ground plane for heat sinking and noise protection.
` The connection of RSETA should be isolated from other noisy traces. The short wire is recommended to prevent EMI and
noise coupling.
` Output capacitor should be placed close to IC and connected to ground plane to reduce noise coupling.
The capacitor should be
placed close to IC pin and
connected to ground plane.
C1 C3
ACIN 1 10 BATT
NC 2 9 NC
CHG_S 3 GND 8 EN
PGOOD 4 7 NC
GND 5
9
ISETA
RSETA
GND
The GND should be The connection of R SETA
connected to a strong should be isolated from other
ground plane for heat noisy traces. The short wire
sinking and noise is recommended to prevent
protection. EMI and noise coupling.
Figure 2
www.richtek.com DS9513-00 July 2008
8
RT9513
Outline Dimension
D2
D
E E2
SEE DETAIL A
1 2 1 2 1
e
b
DETAIL A
A
Pin #1 ID and Tie Bar Mark Options
A3
A1
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit
design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be
guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.