Experiment: 1

Object: Write a hardware description for a full Adder / Subtracter having a select line
for selection of the desired operation.

Verilog Code:
module addsub(a, b, sel, y);
input [3:0]a;
input [3:0] b;
input sel;
output [4:0] y;
reg [4:0] y,out;
reg [3:0]c;
always @(a,b,sel)
begin
if(sel==1)
y=a+b;
else
begin
c[0]=~b[0];
c[1]=~b[1];
c[2]=~b[2];
c[3]=~b[3];
out<=a+c+1'b1;
y=out;
y[4]=0;
if (b>a)
y[4]=1;
end
end
endmodule
RTL Schematic:
1
Simulation Output:

O------------o------------O

Experiment:2
Object: Write a hardware description Degree to radian converter.

Verilog code:
2
 module degtorad(deg, rad);
input [15:0] deg;
output [3:0] rad;
reg [3:0] rad;
integer i=0;
integer aa=3;
integer deg1;
always @ (deg)
begin
deg1=deg;
i=0;
for (aa=0;aa<=150;aa=aa+1)
begin
if (deg1<57)
begin
aa=155;
end
deg1=deg1-57;
i=i+1;
end
rad=i-1;
end
endmodule

RTL Schematic:

3
Simulation Output:

O------------o-----------O

Experiment: 3
Object: Write a hardware description for a modulo 13 counter.

Verilog code:
mod13_counter(reset_n, clk, cnt_reg);
4
 input reset_n;
input clk;
output [3:0]cnt_reg;
reg cnt_reg;
reg [3:0] cnt_next;
always @(posedge clk )
begin
cnt_next=cnt_reg+1'b1;
if(reset_n==1'b0)
cnt_reg<=4'b0;
else if(cnt_reg==4'd12)
cnt_reg<=4'b0;
else
cnt_reg<=cnt_next;
end
endmodule

5
RTL Schematic:

Simulation Output:

O------------o-----------O

6
 Experiment: 4
Object: Write a hardware description for 8 bit Shift Register with shift left and shift
right operation.

Verilog code:
module shiftreg(clk, ser_en, sh_l, ser_in, ser_out,reg_out);
input clk, ser_in,ser_en,sh_l;
output ser_out,reg_out;
reg [3:0] reg_out=0;
reg ser_out=0;

always @ (posedge clk) begin

       if (ser_en==1) begin
               if (sh_l==1)
begin
                       ser_out=reg_out[3];
                       reg_out[3]=reg_out[2];
                       reg_out[2]=reg_out[1];
                       reg_out[1]=reg_out[0];
                       reg_out[0]=ser_in;
               end
               else
begin
                       ser_out=reg_out[0];
                       reg_out[0]=reg_out[1];
                       reg_out[1]=reg_out[2];
                       reg_out[2]=reg_out[3];
                       reg_out[3]=ser_in;
               end
       end
end
endmodule

RTL Schematic:

7
Simulation Output:

O------------o-----------O

Assignment 5
Object: Write a hardware description for an Array multiplier of two 4 bit inputs.
8
Verilog code:
module arraym(a,b,p);
input [3:0]a, b;
output [7:0] p;
wire w1,w2,w3,w4,w5,w6;
wire r;
assign a0=a[0];
assign a1=a[1];
assign a2=a[2];
assign a3=a[3];
assign b0=b[0];
assign b1=b[1];
assign b2=b[2];
assign b3=b[3];
assign r=1'b0;
assign p0=a0&b0;
assign x1=b1&a0;
assign y1=b0&a1;
assign x2=b2&a0;
assign y2=b1&a1;
assign z2=b0&a2;
assign x3=b3&a0;
assign y3=b2&a1;
assign z3=b1&a2;
assign u3=b0&a3;
assign x4=b3&a1;
assign y4=b2&a2;
assign z4=b1&a3;
assign x5=b3&a2;
assign y5=b2&a3;
assign x6=b3&a3;
assign p2=(((x2^y2)^z2)^r)^w1;

9
 assign w2=(x2&y2)|(y2&z2)|(z2&r)|(r&w1)|(w1&x2);
assign p1=x1^y1;
assign w1=x1&y1;
assign p3=(((x3^y3)^z3)^u3)^w2;
assign w3=(x3&y3)|(y3&z3)|(z3&u3)|(u3&w2)|(w2&x3);
assign p4=(((x4^y4)^z4)^r)^w3;
assign w4=(x4&y4)|(y4&z4)|(z4&r)|(r&w3)|(w3&x4);
assign p5=((x5^y5)^r)^w4;
assign w5=(x5&y5)|(y5&r)|(r&w4)|(w4&x5);
assign p6=x6^w5;
assign w6=x6&w5;
assign p7=w6;
assign p[0]=p0;
assign p[1]=p1;
assign p[2]=p2;
assign p[3]=p3;
assign p[4]=p4;
assign p[5]=p5;
assign p[6]=p6;
assign p[7]=p7;
endmodule

10
RTL Schematic:

Simulation Output:

O------------o------------O

Experiment: 6
Object: Write a hardware description for Booth Multiplier.
Verilog code:
11
module boothm(a,b, out);
input [3:0] a;
input [3:0] b;
output [7:0] out;
reg [7:0] out=0;
reg [3:0] m;
reg [3:0] q;
reg [3:0] acc=0;
reg q_1=0;
integer count=4;
always @(a,b) begin
       acc=0;
       q_1=0;
       q=a;
       m=b;
       if (a>b) begin
               m=a;
               q=b;
       end
       for (count=0;count<4;count=count+1) begin
               if (q[0]==1 && q_1==0) begin
                       acc=acc-m;
               end
               if (q[0]==0 && q_1==1) begin
                       acc=acc+m;
               end
               q_1=q[0];
               q[0]=q[1];
               q[1]=q[2];
               q[2]=q[3];
               q[3]=acc[0];
               acc[0]=acc[1];
               acc[1]=acc[2];
               acc[2]=acc[3];
       end
       out[7:4]=acc;
       out[3:0]=q;
end
endmodule

RTL Schematic:

12
Simulation Output:

O------------o-----------O

13