Successive Approximation ADC

10-BIT 10 Ms/s SAR ADC

Ivan T. Bogue
Ruba T. Borno
Joseph A. Potkay
Bogue, Borno, and Potkay University of Michigan Electrical Engineering & Computer Science
Successive Approximation ADC

OUTLINE

• Applications and Advantages

• Top Level Circuit Description

• Features

• Results

Bogue, Borno, and Potkay University of Michigan Electrical Engineering & Computer Science
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INTRODUCTION CIRCUIT DESC. CAP ARRAY STABILITY TEST SET-UP RESULTS
 Successive Approximation ADC

STATE OF THE ART TECHNOLOGY

1T

100G ΣΔ

SAR
10G
Sample Rate (s/s)

FLASH
1G

100M 8 16 24
Flash 2-Step Bits of Resolution
10M

1M ΣΔ
100K SAR ΣΔ SAR
10K FLASH

2 4 6 8 10 12 14 16 18 20 22 24 26 10 100 1K 10K 100K 1M 10M 100M

Resolution (bits) Maximum Conversion Speed (Hz)

Bogue, Borno, and Potkay University of Michigan Electrical Engineering & Computer Science
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INTRODUCTION CIRCUIT DESC. CAP ARRAY STABILITY TEST SET-UP RESULTS
Successive Approximation ADC

TOP LEVEL DIFFERENTIAL SAR

Sampling Converting

Bogue, Borno, and Potkay University of Michigan Electrical Engineering & Computer Science
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INTRODUCTION CIRCUIT DESC. CAP ARRAY STABILITY TEST SET-UP RESULTS
Successive Approximation ADC

TIMING DIAGRAM

Bogue, Borno, and Potkay University of Michigan Electrical Engineering & Computer Science
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INTRODUCTION CIRCUIT DESC. CAP ARRAY STABILITY TEST SET-UP RESULTS
Successive Approximation ADC

CAPACITOR ARRAY

Bogue, Borno, and Potkay University of Michigan Electrical Engineering & Computer Science
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INTRODUCTION CIRCUIT DESC. CAP ARRAY STABILITY TEST SET-UP RESULTS
Successive Approximation ADC

CAPACITOR ARRAY

5
CnVr − Vinp CnVr−Vinp
∑
10

n =1 992 ∑
n=6 1024

Bogue, Borno, and Potkay University of Michigan Electrical Engineering & Computer Science
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INTRODUCTION CIRCUIT DESC. CAP ARRAY STABILITY TEST SET-UP RESULTS
Successive Approximation ADC

COMPARATOR INPUT

• Returns to initial voltages

• Differential provides
twice the signal range

Capacitor Output Voltage into Comparator versus Time

Bogue, Borno, and Potkay University of Michigan Electrical Engineering & Computer Science
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INTRODUCTION CIRCUIT DESC. CAP ARRAY STABILITY TEST SET-UP RESULTS
Successive Approximation ADC

CAPACITOR MISMATCH ANALYSIS

Capacitors match to
0.1% giving max. DNL
of 0.1LSB

MATLAB – Max DNL vs. σcap

Bogue, Borno, and Potkay University of Michigan Electrical Engineering & Computer Science
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INTRODUCTION CIRCUIT DESC. CAP ARRAY STABILITY TEST SET-UP RESULTS
Successive Approximation ADC

GAIN STAGE AND STABILITY

Current Reference Differential Buffer

Current reference schematic Buffer schematic with Vbias input

Bogue, Borno, and Potkay University of Michigan Electrical Engineering & Computer Science
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INTRODUCTION CIRCUIT DESC. CAP ARRAY STABILITY TEST SET-UP RESULTS
Successive Approximation ADC

STABILITY

Gain (dB) vs. Freq. Gain (dB) vs. Freq. T=100C,

Vdd=3.63, 3.3, and 2.97V 27C, 0C

Less than 7% change in Less than 3% change in

Bandwidth for +/- 10% supply Bandwidth over entire range of
voltage temperature
Bogue, Borno, and Potkay University of Michigan Electrical Engineering & Computer Science
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OUTLINE CIRCUIT DESC. CAP ARRAY STABILITY TEST SET-UP RESULTS
 Successive Approximation ADC

LINEARITY TEST SETUP

3.3V 2V

VDD Vref+
10MHz Fs
SAR DNL
Vin+ (MATLAB)
Codes 0-40 ADC INL
(5s/code) Vin- 10
gnd Vref-

0V 0V

Linearity Test Setup with Temperature at 27C and typical devices

Bogue, Borno, and Potkay University of Michigan Electrical Engineering & Computer Science
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INTRODUCTION CIRCUIT DESC. CAP ARRAY STABILITY TEST SET-UP RESULTS
Successive Approximation ADC

INL and DNL 5 codes/sample

INL DNL

Bogue, Borno, and Potkay University of Michigan Electrical Engineering & Computer Science
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INTRODUCTION CIRCUIT DESC. CAP ARRAY STABILITY TEST SET-UP RESULTS
Successive Approximation ADC

INL and DNL 10 codes/sample

INL DNL

INL versus Code with 10 codes DNL versus Code for 10 samples
per sample per code

Bogue, Borno, and Potkay University of Michigan Electrical Engineering & Computer Science
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INTRODUCTION CIRCUIT DESC. CAP ARRAY STABILITY TEST SET-UP RESULTS
Successive Approximation ADC

ADC OUTPUT

Bogue, Borno, and Potkay University of Michigan Electrical Engineering & Computer Science
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INTRODUCTION CIRCUIT DESC. CAP ARRAY STABILITY TEST SET-UP RESULTS
 Successive Approximation ADC

SNDR TEST SETUP

3.3V 2V

VDD Vref+
10MHz Fs
DC 1V SAR FFT SNDR
Vin+
2V pk-to-pk sine ADC (MATLAB) ENOB
Vin- 10
180º out of phase
gnd Vref-

0V 0V

SNDR Test Setup with Temperature at 27C and typical devices

Bogue, Borno, and Potkay University of Michigan Electrical Engineering & Computer Science
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INTRODUCTION CIRCUIT DESC. CAP ARRAY STABILITY TEST SET-UP RESULTS
Successive Approximation ADC

SUMMARY
Product AD7674 AD7482 MAX1248 MICHIGAN
Resolution
18 12 10 10
(bits)
Speed
0.8 3 0.13 10
(MHz)
Power 7 (worst)
120 90 3.6
(mW) 4 (Nyquist)
100dB @ 71dB @ 66dB @ 66dB @
SNDR
10kHz 1MHz 10kHz 1MHz
+2.7 to
Supply (V) +5 +5 +3.3
+3.6

Estimated Area: 0.3mm2

Bogue, Borno, and Potkay University of Michigan Electrical Engineering & Computer Science
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INTRODUCTION CIRCUIT DESC. CAP ARRAY STABILITY TEST SET-UP RESULTS