Verilog Hardware Description Language

主講人:孫念皖
廖旂湧
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OUTLINE

z Overview Verilog

z Basics of Verilog Language

z Verilog-HDL Circuit Design

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Why Verilog?
z Verilog is a hardware description language.
z Choice of many design teams.
z Most of us are familiar with C- like syntax/ semantics.
z Simple module/ port syntax is familiar way to organize hierarchical
building blocks.
z With care in how you use features, it’s well- suited for both synthesis
and verification.
z Caveats
¾ Good, consistent coding style is essential
¾ C syntax, but not C execution model: Verilog is a concurrent
programming language (modules, blocks, statements execute in
parallel)

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Verilog History

z Verilog was written to be used by circuit designers.

z Cadence acquired gateway in 1990.
z Cadence released Verilog to the pubic domain in1991.
z In 1995 the language was ratified as IEEE standard 1364.

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Design domain

z Hardware description language that allows you to describe circuit at

different levels of abstractions and allows you to mix any level of
abstraction in the design.

Behavioral Design Model Domain

level of
abstraction Abstraction Structural Physical

System Architecture
Design
Algorithm Structural
Design
RTL Logic
Design
Gate Layout
Design
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Basics of Verilog Language

1. Verilog Module
2. Identifiers
3. Keywords
4. Numbers
5. Four Values Logic
6. Data Types
7. Port Mapping
8. Operators

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1.Verilog Module

Respose
Stimula
Verilog Generation
-tion
Module and
and
Verification
Control

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module module_name (port_name);

port declaration
data type declaration
module functionality or structure

endmodule

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Example 1

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Example 2

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2.Identifiers

z Identifiers are names given to Verilog objects

z Names of modules, ports and instances are all identifiers.
z First character must use a letter,other character can to use
letter, number or “_”.

Example: module fulladd(a_1,a_2,b);

input a_1, a_2; identifiers
output b;

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3.Keywords

z Predefined identifiers to define the language constructs

z All keywords are defined in lower case
z They cannot be used as identifiers
z Examples: module, input ,output, reg,wire…

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4.Numbers

z Numbers are integer or real constants.

Integer constants are written as
<size>’<base format><number>

z A number may be sized or unsized

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z The base format indicates the type of number

¾ Decimal (d or D)
¾ Hex (h or H)
¾ Octal (o or O)
¾ Binary (b or B)

(29355)10

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Truncate and Fill

z 6'hCA , 001010 truncated, not 11001010

truncated
z 6'hA , 001010 filled with two '0' on left

filled

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5.Four Values Logic Level

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6.Data Types

z Nets
¾represent physical connection between devices
z Registers
¾represent abstract storage devices
z Parameters
¾are run-time constants

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Net

z Nets are continuously driven by the devices that

drive them.These devices include gates and
modules.
z Default initial value for a wire is “Z”

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Types of Nets

The net class consists of some data types.

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Strength table
強度等級 縮寫 程度

supply1 Su1 最強的1

strong1 St1

pull1 Pu1

large1 La1

weak1 We1

medium1 Me1

small1 Sm1

highz1 Hiz1 最弱的1

highz Hiz0 最弱的0

small0 Sm0

medium0 Me0

weak0 We0

large0 La0

pull0 Pu0

strong0 St0

20 supply0 Su0 最強的0 NCCU

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Verilog resolves ambiguous strength

a output b output out

strong1 strong0 strongX

a
pull0 weak1 pull0

out pull0 strong1 strong1

b strong1 weak1 strong1

pull0 Hiz pull0

Hiz weak1 weak1

Hiz Hiz Hiz

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Registers

z Registers represent abstract data storage elements

z A register holds its value until a new value is assigned to it
z Default initial value for a register is “X”

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Types of Registers

The register class consists of four data types.

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Parameters

z It use parameters to declare run-time constants.

z Parameters are local ,known only to the module in
which they are defined.

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Types of Parameters

z You can use a parameter anywhere that you can use a

literal.
ex: module mod(ina, inb,out);
……..
Parameter m1=8,
real_constant =1.032,
x_word = 16’bx;
wire [m1:0] w1;
……..
endmodule

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7.Port Mapping

z In Order
Mux Mux_1(Sel,x,y,Mux_Out);
Register8
Register8_1(Clock,Reset,
Top-level
Mux_Out,Reg_Out); module
z By Name a x
Mux Mux_1(.s(sel),.x(a),.y(b), MUX out Mux_Out
b y
.out(Mux_Out));
Register8 sel s
Register8_1(.Clock(Clock),
.Reset(Reset) ,
.data(Mux_Out),.q(Reg_Out));

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8.Operators

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z Relational Operators
¾a<b a less than b
¾a>b a greater than b
¾a<=b a less than or equal to b
¾a>=b a greater than or equal to b
z Arithmetic Operators
¾+, -, *, /, % (the modulus operator)

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z Equality Operators
¾ a === b a equal to b, including x and z
¾ a !== b a not equal to b, including x and z
¾ a == b a equal to b, resulting may be unknown
¾ a != b a not equal to b, result may be unknown

ex： 0= =0 --> 1 true 0= = =0 --> 1 true

0= =1 --> 0 false
0= =x --> x unknown
x= =x --> x unknown
1= =z --> x unknown
29 z= =z --> x unknown
0= = =1 --> 0 false
0= = =x --> 0 false
x= = =x --> 1 true
1= = =z --> 0 false
z= = =z --> 1 true
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z Logical Operators
¾ ! logic negation
¾ && logical and
¾ || logical or
z Shift Operators
¾ << left shift
¾ >> right shift
z Concatenation & Replication Operator
¾ {},{{}}
Ex:{b, {3{c, d}}} this is equivalent to {b, c, d, c, d, c, d}
z Conditional Operators
¾ out = (enable) ? data : 8'bz; // Tri state buffer

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Verilog-HDL Circuit Design

z Structural Modeling
z Behavioral Modeling

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Structural Modeling

z A structural model is equivalent to a schematic. You

connect simple components to create a more complex
component.
z A structural model is created using existing components.
module Add_full(sum, c_out, a, b, c_in);
input a, b, c_in;
output c_out, sum;
wire w1, w2, w3; module instance name
Add_half M1(w1,w2,a,b);
Add_half M2(sum,w3,w1,c_in);
or (c_out,w2,w3);
endmodule

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Structural Modeling (cont.)

z and, nand, nor, or, xor, xnor

¾ First terminal is output, followed by inputs.
and a1 (out1, in1, in2)
nand a2 (out2, in21, in22, in23, in24)
z buf, not
¾ One or more outputs first, followed by one input.
not N1 (OUT1, OUT2, OUT3, OUT4, INA)
buf B1 (BO1, BIN)

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Structural Modeling (cont.)

z bufif0, bufif1, notif0, notif1: three-state drivers.

¾ Output terminal first, then input, then control
bufif1 BF1 (OUTA,INA,CTRLA)

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Structural Modeling (cont.)

module MUX4x1(y, d0, d1, d2, d3, s0, s1);

output y;
input d0,d1,d2,d3,s0,s1;

and (t0,d0,s0_,s1_),
(t1,d1,s0_,s1),
(t2,d2,s0,s1_),
(t3,d3,s0,s1);
not (s0_,s0), (s1_,s1);
or (y,t0,t1,t2,t3);
endmodule

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Structural Modeling (cont.)

z Array of Instances
module driver(in,out,en);
input [2:0] in;
output [2:0] out;
input en;
bufif0 u[2:0]
u2 (out[2],in[2],en);
(out,in,en);
endmodule bufif0 u1 (out[1],in[1],en);
bufif0 u0 (out[0],in[0],en);
endmodule

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Behavioral Modeling

z Behavioral modeling enables you to describe the system at a

high level of abstraction.
z Behavioral modeling in Verilog is described by specifying a
set of concurrently active procedural blocks.

DFF
Clr At every positive edge of Clk
If Clr is not low
Set Q to the value of Data
Data Q Set Qb to inverse of Data

DFF
Clk Qb Whenever Clr goes low
Set Q to 0
Set Qb to 1

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Procedural Blocks

z Procedural blocks are the basic for behavioral modeling.

z Procedural blocks are of two types:
¾ initial procedural blocks
¾ always procedural blocks
z Procedural blocks have the following components:
¾ Procedural assignment statements
¾ High-level constructs (loop, conditional statements)
¾ Timing controls

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Procedural Assignments

z Assignments made inside procedural blocks are called

procedural assignments.
module adder(out, a, b, cin);
input a, b, cin;
output [1:0] out;
wire a, b, cin;
reg half_sum;
half_sum, half_carry;
reg [1:0] out;
always @(a or b or cin)
begin
half_sum = a ^ b ^ cin; //OK
half_carry = a & b | a & !b & cin | !a &b &cin ; // ERROR
out = {half_carry,half_sum};
end

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Procedural Timing Control

z You can specify procedural timing inside of procedural

blocks, using three types of timing controls:
¾ Simple delays: #
¾ Edge-sensitive timing controls: @
¾ Level-sensitive timing control: wait

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Simple Delay

z Use simple delays (# delays) to delay simulation in a test

bench, or to approximate real-world delays in behavioral
models.
module muxtwo (out, a ,b sl);
input a,b,sl;
output out;
reg out;
always @(sl or a or b)
begin
if (!sl)
#10 out = a ; //The delay from a to out is 10 time units
else
#12 out = b; end
endmodule
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Edge-Sensitive Timing

z Use the @ timing control for combinational and sequential

models at the RTL and behavioral levels.

module latch_adder (clock,a_bus,acc,g);

input clock, a_bus, acc;
output g;
reg g;

always @(posedge clock)

begin
g = @(a_bus) acc;
end

endmodule
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The Wait Statement

z Use wait for level-sensitive timing control in behavioral

code.
module latch_adder (out, a, b, enable, c,d);
input enable;
input [2:0]a, b, c, d;
output [3:0]out, out1;

reg [3:0] out, out1;

always @(a or b or c or d)
begin
wait (!enable) // if enable is low, perform addition
out = a + b;
out1=c + d;
end
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Name Events

z Defined named events in behavioral code which you can

then trigger to cause an action.
module add_mult (out, a, b);
input [2:0]a, b;
output [3:0]out;
reg [3:0] out;
event add, mult ; // define events
always @(a or b)
if ( a > b) The operator is the trigger
->add; for the named event.
else
->mult;
always @(add)
out = a + b;
always @(mult)
out = a * b;
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Block Statements

z Sequential block statements are enclosed between the

keywords begin and end.
z Parallel block statements are enclosed between the
keywords fork and join.

always C always C initial C initial C

begin fork begin fork

C C C C

C C C C

C C C C

C C C C

C C C C

end join end join

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Block Statements (cont.)

z In a sequential block, statements are evaluated and executed

one after the other.
z In a concurrent block, statements are immediately scheduled
to be evaluated and executed after their respective delays.

begin fork
#5 a=3; #5 a=3;
#5 a=5; #15 a=4;
#5 a=4; #10 a=5;
end join

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Non-blocking Procedural Assignment

module swap_vals;
reg a, b, clk;
initial
begin
a=0;
b=1;
clk=0;
end
always #5
clk = ~clk;
always @(posedge clk)
begin
a <= b; // Non-blocking procedural assignment
b <= a; // swaps the values of a and b
end
endmodule
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Nonblocking Procedural Assignment (cont.)

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Conditional Statements

z if and if-else Statements

¾ Conditions are evaluated in order from top to bottom.
¾ The first condition, that is true, causes the corresponding
sequence of statements to be executed.
¾ If all conditions are false, then the sequence of statements
associated with the “else” clause is evaluated.

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Conditional Statements (cont.)

z Example: if and if-else

always @(sela
@(sela,or
selb,
selba,orb,ac)or b or c)
begin
begin
ifif(!selb)
(sela)
q q= =c;a;
ifelse
( selb)
q =(selb)
if b;
if ( qsela)
= b;
q = c;
else
end q = c;
end

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Conditional Statements (cont.)

z case Statement
¾ The case statement does a bit-by-bit comparison for an exact
match (including x and z).
¾ The default statement is optional. It is executed when none of
the statements match the case expression.

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Conditional Statements (cont.)

z Example: case

always @(sel or a or b or c or d)
begin
case (sel)
2’b00 : q = a;
2’b01 : q = b;
2’b10 : q = c;
default : q = d;
endcase
end

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Looping Statements

z repeat Loop

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Looping Statements (cont.)

z repeat Loop (cont.)

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Looping Statements (cont.)

z while Loop
…
reg [7:0] tempreg;
reg [3:0] count;
…
count=0;
while (tempreg)
begin
if (tempreg[0]) count = count + 1;
tempreg = tempreg >> 1;
end
end
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Looping Statements (cont.)

z forever Loop
…
reg clk;
initial
begin
clk=0;
forever
begin
# 10 clk=1;
# 10 clk=0;
end
end
…
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Looping Statements (cont.)

z for Loop
…
‘define MAX_STATE 32
integer i;
initial
begin
for(i=0;i<MAX_STATE;i=i+2)
state[i]=0;
end

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Continuous Assignments

z You can model combination logic with continuous

assignments, instead of using gates and interconnect nets.
z Use continuous assignments outside of a procedural block.
They are considered the lowest level construct in behavioral
modeling.
z Syntax for an explicit continuous assignment
<assign> [#delay] [strength] <net_name> = <expression>

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Continuous Assignments (cont.)

z Example: Continuous Assignment

module cond_assign(mux1,a,b,c,d);
output mux1;
input a,b,c,d;
assign mux1= sel == 2'b00 ? a:
sel == 2'b01 ? b:
sel == 2'b10 ? c: d;
endmodule

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Behavioral vs. Structural Modeling

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Reference

z Cadence, Cadence Verilog® Language and Simulation,

February 10, 2000.
z Samir Palnitkar, Verilog®HDL:A Guide to Digital Design
and Synthesis, PRENTICE HALL, 1996.
z Michael D. Chiletti, Modeling, Synthesis and Rapid
Prototyping with Verilog® HDL, PRENTICE HALL, 1999.
z 鄭信源, Verilog 硬體描述語言數位電路設計實務, 儒林
出版社, 2002.

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