HOME WORK: 3

Course No. CSE 262

Course Title: Computer System
Architecture

NAME – BAJRANG KUMAR

ROLL NO-RA1901A07
Q1. How many clock cycles are needed to execute
(a) LDA and STA
(b) BUN and BSA
(c) ISZ
(d) AND and ADD
Ans:-
Clock cycles
LDA 6
STA 5
BUN 5
BSA 6
ISZ 7
AND 6
ADD 6

Q2. Fetching and decoding of any instruction takes three clock cycles.
How?
Ans:-

There are primarily three components of the computer involved in the

cycle

1. The computer memory: since the program is stored there, as is the data

2. The Address and Data buses: since copies of the instructions are stored
in memory but must be decoded in the CPU. Similarly any Data needed must be
transferred to a Register in the CPU

3. The CPU:

o The Registers store relevant data, particularly:

§ Program Counter (PC) holds the address the next instruction in memory

§ Instruction Register (IR) holds an OpCode for the current instruction

§ General Purpose registers hold the data (if any) on which the instruction
will operate
o The Control Unit – here logic decodes the instruction OpCode and
identifies what should happen during execution (The PC and the IR are in the
Control Unit)

o The ALU executes the decoded instructions on the data in the Register (if
any)

Fetch

· A special register, the program counter exists in the CPU to record

where in main memory the next instruction is located

· The CPU communicates this address over the address bus to main
memory, with signals indicating it needs the instruction stored at that address
(This activates the Memory location) (1 clock cycle)

· Main memory then transmits the instruction along the data bus to the
CPU (The Control Unit sends a READ signal) (another clock cycle)

· Sometimes several fetch steps may be required to get all the parts of a
specific instruction ( for example the instruction may act on specific data which
also needs to be recovered from memory in separate clock cycles (another 2
clock cycles)

· The instruction is stored within the CPU ( in an instruction register)

and the program counter is adjusted to `point at' the next instruction (ready for
later on!). Any data would be stored in a general purpose register

Decoding

· Once an instruction has been fetched, it must be decoded

· Decoding determines three things:

 what kind of action needs to take place (Links the OpCode in the
Instruction Register to electronic circuitry inside the ALU) This
Opcode is a part of the Instruction Set for the CPU
 if data is being used, where does the computer obtain that data (eg.
Which register)
 Where should the result be sent (same or another register ?)

Execution

· Once an instruction has been fetched and decoded, it can be carried out
(or executed) in the Arithmetic Logic Unit
· These instructions are carried out at an electronics level within the ALU

Q3. Draw timing diagram for D3T4: SC ← 0

Ans:-
At time T4, SC is cleared to 0 if decoder output D3 is active:-
D3T4: SC  0
T0 T1 T2 T3 T4 T0
Clock

T0

T1

T2

T3

T4

D3

CLR
SC

Q4. How is I bit useful in determining the type of instruction

Ans:-
We can explain that how I bit is useful in determining the type of instruction.
As consider the instruction code format shown in fig(a) below:

(i) It consist of a 3 bit operation code,12 bit address , and an indirect address
mode bit designated by” I” .the mode bit is 0 for a direct address and 1 is for
indirect address. A direct bit address instruction is shown in fig (b) it is placed
in address 22 in memory . the I bit is 0, so the address is considered as direct
address instruction format, the op code specifies th add operation .the address
part is the binary eqivalent of 457. the control finds the operand in memeory at
address 457 and adds it to the content AC.
(ii)The instruction in address 35 shown in fig(c) has amode bit I =1 therefore it
is considered as indirect address instruction. The address part is binary
equuivalent of 300.the control goes to the address 300 to find the address of the
operand. The address of the operand in this case is 1350.the operand found at
address 1350 is added to the content AC.

(a)

15 14 12 11 0
I OPCODE ADDRESS

(b)

15 14 12 11 0
I 111 Register reference

(c)

15 14 12 11 0
I 111 I/O reference

Q5. Why is micro programmed control better than hardwired?

Identify some situations when hardwired is preferred.
Ans:-

Micro programmed control is better than hardwired here are some reasons why
it is better than hardwired.

1. If we want any modification or change then we can do easily by updating

the micro programmed in control memory. But in case of hard wired we
have to construct all the circuit again which is very difficult.
For example:
Taking our basic computer as an example, we notice that its four-bit op-
code permits up to 16 instructions. Therefore, we could add seven more
instructions to the instruction set by simply expanding its microprogram.
To do this with the hard- wired version of our computer would require a
complete redesign of the controller circuit hardware.

2. Another advantage to using micro-programmed control is the fact that

the task of designing the computer in the first place is simplified. The
process of specifying the architecture and instruction set is now one of
software (micro-programming) as opposed to hardware design.
 3. Simplifies design of control unit.
4. Micro programmed control is Cheaper than hardwired control.
5. It is less error-prone
6. It is easy to modify than hard wired.

Some situations when hard wired is preferred

1.In case of speed: If speed is a consideration, hard- wiring may be required
since it is faster to have the hardware issue the required control signals than to
have a "program" do it.
2.In case of implementing RISK: Hardwired control unit is typically use for
implementing control unit in pure RISC while micro programmed is not usually
used for implementing RISC.

Q6. Find out register size of registers in Pentium Processor

ANS:-
register size of registers in Pentium Processor: 32 bits or 64 bits

Q7. Demonstrate the execution of interrupt cycle with the help of an

example.
Ans:-
Interrupt:-
Mechanism by which other modules (e.g. I/O) may interrupt normal sequence
Of processing)
Interrupt cycle:-

Added to instruction cycle

•Processor checks for interrupt
->Indicated by an interrupt signal
•If no interrupt, fetch next instruction
•If interrupt pending:

->Suspend execution of current program

->Save context
->Set PC to start address of interrupt handler

routine
->Process interrupt
->Restore context and continue interrupted
program

Open communication only when some data has to be passed --> interrupt.
- The I/O interface, instead of the CPU, monitors the I/O device.
- When the interface founds that the I/O device is ready for data transfer, it
generates an interrupt request to the CPU
- Upon detecting an interrupt, the CPU stops
momentarily the task it is doing, branches to the service
routine to process the data transfer, and then returns to
the task it was performing.