St.

Johns College of Engineering & Technology

Yerrakota, Yemmiganur – 518 360, Kurnool (Dist) A.P.

II-Mid Term Examination [Objective Type] Academic Year 2010-11 Invigilator Sign.

Year & Sem.: IV-B.Tech. I-Semester (R07) Branch & Section: EEE
Subject: VLSI DESIGN Max. Marks: 20 M
Regd.
Name: No.

Answer the following questions: 1 X 20 = 20 M

1. Logic synthesis systems are very useful for [ ]

a. transforming between technologies b. very good silicon implementation
c. to create control logic d. to create micro code
2. Behavioral synthesis is [ ]
a. technology dependent and specify the implementation
b. technology independent and specify the implementation
c. technology independent and without specify the implementation
d. technology dependent and without specify the implementation
3. Which of the following synthesis converts RTL description to a set of registers and combinational logic [ ]
a. behavioral synthesis b. RTL synthesis c. logic level synthesis d. layout synthesis
4. The number of input and output pins offered for CPLDs are [ ]
a. Higher b. Lower c. Less than FPGAs d. None
5. RTL description are captured using [ ]
a. hardware description language (HDL) b. software description language c. cathedral series d. micro controllers
6. The most detailed and accurate simulation technique is [ ]
a. gate level b. timing c. logic level d. circuit-level
7. In layout synthesis generally two phases are required they are [ ]
a. designing and minimizing b. placement and routing c. optimization of logic d. testing and verification
8. Many design systems generally used HDL because of [ ]
a. easy b. quickly understood c. small in size d. easily modified
9. The traditional method of capturing a digital system design is [ ]
a. schematic editor b. flow table c. ASIC design d. compiler
10. Simulations with delays are used to check the [ ]
a. timing problems b. DRC errors c. functionality d. speed of system
11. A design-rule-checker is used to [ ]
a. find DRC errors b. conforms the layout to the geometric design rules
c. verify the functionality of the geometric design rules d. verify the functionality of the design
12. The last step in the design process is [ ]
a. Layout extraction b. Back annotation c. Pattern Generation d. Design rule verification
13. For MOS circuits the dominant faults are due to [ ]
a. short circuits in diffusion layers b. open circuits in diffusion layer c. short circuits in interconnections d. none
14. Manufacturing tests are used to verify that [ ]
a. function of a chip as a whole b. every gate operates as expected c. function in the field d. none
15. VHDL, verilog hardware description languages are used for testing of [ ]
a. manufacturing tests b. functionality test c. Design testing d. chip testing
16. A FSM with 'n' possible i/ps to the combinational logic and 'm' elements then required test vectors are [ ]
a. m+n b. 2m c. 2nDocuments\LSI. d. none
17. Controllability in testing means [ ]
a. able to set known internal states b. able to generate all states c. able to generate all circuit states d. none
18. The faults occur due to thin-oxide shorts or metal-to metal shorts are called [ ]
a. stuck at zero faults b. short-circuit faults c. open-circuit faults d. bridge faults
19. The tests that are usually carried after chip is manufactured are called [ ]
a. functionality test b. design verification c. manufacturing test d. technology test
20. The layout is tested by using [ ]
a. Design rule checker b. simulator c. PROBE d. BILBO
 St. Johns College of Engineering & Technology
Yerrakota, Yemmiganur – 518 360, Kurnool (Dist) A.P.
II-Mid Term Examination [Theory Type] Academic Year 2010-11
Branch &
Year & Semester: III-B.Tech. II-Semester (R07) Section: EEE
Name of the Max. Marks: 20 Marks
Subject: VLSI DESIGN

Section: A
Answer any two questions from the following three questions 2 X 7 = 14 M

1. What are the advantages of PLAs? Give the sketch for AND matrixes used in PLAs and explain its functionality?

2. What are different design verification tools and explain them in brief?

3. Explain about
a. Chip level test technique b. System level test technique

Section: B
Answer any one question from the following two questions 1X6=6M

4. Explain about CMOS testing and mention test principle for testing?

5. Using block schematics explain the terms: a. CPLDs b. FPGAs

______________________________________________________________________________________________

St. Johns College of Engineering & Technology

Yerrakota, Yemmiganur – 518 360, Kurnool (Dist) A.P.
II-Mid Term Examination [Theory Type] Academic Year 2010-11
Branch &
Year & Semester: III-B.Tech. II-Semester (R07) Section: EEE
Name of the Max. Marks: 20 Marks
Subject: VLSI DESIGN

Section: A
Answer any two questions from the following three questions 2 X 7 = 14 M

1. What are the advantages of PLAs? Give the sketch for AND matrixes used in PLAs and explain its functionality?

2. What are different design verification tools and explain them in brief?

3. Explain about
a. Chip level test technique b. System level test technique

Section: B
Answer any one question from the following two questions 1X6=6M

4. Explain about CMOS testing and mention test principle for testing?

5. Using block schematics explain the terms: a. CPLDs b. FPGAs

______________________________________________________________________________________________