5 things to know about Very Deep Submicron Layout Written by Adrian O'Shaughnessy

5 things to know about Very Deep Submicron

Layout
Posted on January 14, 2011 by Adrian OShaughnessy

AS process technology scales beyond 32-nm feature sizes, for functional and high-yielding silicon,
layouts must be robust enough the meet the ever increasing demands and challenges due to
increased process variations, interconnect processing difficulties, and
other newly exacerbated physical effects.
Of the many layout challenges faced, I've picked five topics that are continually asked about on our
layout training courses:

Shallow Trench Isolation (STI)

Shallow trench Isolation (STI) introduces some effects into the silicon, which need to be considered
during design/layout. STI effect causes a degradation or variation in a devices expected
performance. Most extraction/simulation tools can simulate this effect, so expected final silicon
performance can be extracted and simulated. This performance variance is particularly important
whilst dealing with currents, more so than voltages. Hence it is essential that STI is taken into
account for example when laying out a current mirror. The degree of this effect is directly related to
the distance of the channel to the closest field oxide. This distance is commonly referred to as “Poly
To Active” distance. The greater the poly to active distance, the lesser the effect has on the device:
5 things to know about Very Deep Submicron Layout Written by Adrian O'Shaughnessy

Well Proximity Effect (WPE)

Doping of wells and well boundaries have never been uniform, however the non-uniformity was
always more prevalent at well edges. As N+ dopants strike the N-well and photoresist, the ideal
case would be for the photoresist to block all dopants not intended for the N-well and for the N-well
to absorb the remaining ones uniformly across it. However, due to scattering, the edges of the N-
well are normally more heavily doped than the center. The scattering also causes light N doping of
the P-well in regions adjacent to the N-well. On larger geometries, due to manufacturing design
rules, transistors were never allowed to be placed close to well edges and as such were not subjected
to these doping variations. As the technologies scale down, effects like WPE become more
prevalent and can have significant effect on device performance and matching:

Electromigration (EM)
The first step in ensuring the layout will not be prone to electromigration is being aware of the
current consumption in circuits. Schematics should be annotated to show current consumption of
circuits. Overall consumption is useful, but not enough. Portions of the circuit will have higher
current figures than others so conferring with the design engineer is essential. Once you are aware
of the current requirements, ensure that the metal interconnect is of correct width to carry the
desired current. Use real figures, not the magical “1µ per milliamp” and remember that it's not just
power and ground you need to be aware of when routing the correct width tracks.
5 things to know about Very Deep Submicron Layout Written by Adrian O'Shaughnessy

General guidelines include:

• Avoiding notches (increases risk of electromigration)
• Watching out for devices (resistors, capacitors) where they may not have enough contacts
for the current they need to carry
• The use of paralleled metals to increase current carrying capability

LATCH-UP
Latch-up occurs when a high current, low voltage connection forms between the positive supply rail
and the ground on a chip and effectively creates a short circuit between power and ground. It's the
worst case short circuit possible and all normal operation ceases. Latch-up is extremely difficult to
trace in a design and once a chip latches-up, normally it has to have the supply voltage removed to
force it to exit from the unstable state. In some cases, due to the high current, latching-up can cause
permanent damage to the chip.
From a layout point of view, it is important to understand and follow basic guidelines to ensure your
layout is free of potential latch-up issues. In order to do this, the relationship between latch-up and
well resistances, as well as some concept of the parasitic devices which occur between N and P-
wells needs to be understood:

The dominant factor in latch-up is well resistance (both P-well and N-well). It is good practice to
minimise the resistance of a well by ensuring a plentiful supply of bulk contacts. Usually design
rule checks will force the layout to abide by good practices which minimise the risk of latch-up.
The second factor influencing latch-up is that of parasitic bipolar devices. These devices occur at
the boundaries of N and P regions. The closer regions are to each other, the larger the parasitic
devices which are created. Simple methods exist to reduce the size and effect of these parasitic
elements such as try and separate NMOS and PMOS devices as far away from each other as
5 things to know about Very Deep Submicron Layout Written by Adrian O'Shaughnessy

possible, especially on larger devices which consume high current or switch at high speeds. Also try
to insert guard rings between devices of opposite type.

Yield
Yield is a measure of how many functional devices are produced during the manufacturing process.
Typically yield was managed by the foundry but now it has become a very much design/layout
issue. Layout quality has a dramatic effect on yield performance and poor quality layout in
conjunction with a challenging process node reduces yield even more.
Layout techniques need to be applied and checked so as to ensure manufacturability of the silicon is
optimal. Good layout guidelines should include:
• Avoiding non-rectangular line ends
• Avoid unnecessary notches
• Avoid zigzags
• Ensure a minimum 45 degree line length