European Journal of Scientific Research

ISSN 1450-216X Vol.29 No.4 (2009), pp. 461-470

© EuroJournals Publishing, Inc. 2009
http://www.eurojournals.com/ejsr.htm

Simulation of Fabrication Process VDMOSFET Transistor

Using Silvaco Software

H. Abdullah
Dept. of Electrical, Electronics and Systems Engineering, Faculty of Engineering
and Built Environment, Universiti Kebangsaan Malaysia
43600 Bangi Selangor, Malaysia
E-mail: huda@vlsi.eng.ukm.my
Tel: +603 8921 6310; Fax: +603 8921 6146

J. Jurait
Dept. of Electrical, Electronics and Systems Engineering, Faculty of Engineering
and Built Environment, Universiti Kebangsaan Malaysia
43600 Bangi Selangor, Malaysia

A. Lennie
Dept. of Electrical, Electronics and Systems Engineering, Faculty of Engineering
and Built Environment, Universiti Kebangsaan Malaysia
43600 Bangi Selangor, Malaysia

Z.M. Nopiah
Unit of Fundamental Engineering Studies, Faculty of Engineering & Built Environment
Universiti Kebangsaan Malaysia, 43600 Bangi Selangor, Malaysia

I. Ahmad
Department of Electronic and Communication Engineering
College of Engineering,Universiti Tenaga Malaysia
43009 Kajang, Selangor, Malaysia

Abstract

Taguchi Method is being applied in to find the sequence of dominance for factors
that determine the performance of a VDMOSFET power transistor. The main objective of
this project is to optimize the trench depth, trench width, epitaxial resistivity and thickness
in power VDMOSFET so as to obtain high breakdown voltage but low on-resistance.
Optimization of trench depth, trench width, epitaxial resistivity and epitaxial thickness are
based on L9 array. Taguchi Method was being applied to reduce development time and to
ensure that the products are in the acceptable quality range. The robust nature of Taguchi
Method pointed out the most dominant factors that will determine the performance and
characteristics of the power transistor. ATHENA and ATLAS module of SILVACO
software are the tools used in simulating the fabrication and also simulating the electrical
performance of the transistors. The parameters under investigation were the threshold
voltage (VTH), breakdown voltage (BV) and on-resistance (RON). The data produced from
the experiments were used to determine the sequence of dominance for the factors involved
Simulation of Fabrication Process VDMOSFET Transistor Using Silvaco Software 462

in the transistor’s characteristics. Taguchi suggests that to analyzing Signal-to-Noise ratios

(S/N) by using conceptual approach that involves graphing the effects and visually
identifying the factors that show to be significant. The slopes of the lines also show the
relative influence of the factor to the variability of results. The Pareto ANOVA method is
used to analyze the data for process optimization. This is a quick and easy method for
analyzing results of parameter design that does not require an ANOVA table and does not
use F-tests. This method enables the significance of factors to be evaluated by Pareto type
analysis. It also allows the optimal levels of factors to be obtained. From the experimental
results, the trench depth, epitaxial resistance, and epitaxial are significant factors toward
breakdown voltage and on-resistance in n-channel VDMOSFET.

Keywords: Taguchi Method, VDMOSFET, Silvaco, ANOVA, Pareto Principle

1. Introduction
Field Effect Transistor also called FET is a semiconductor device that function with bipolar transistor,
FET operated with a single charge only. Various application are using according to specific demand
like fast devices that use high voltage. The need for power devices is highly in demand with many
applications like drive power, multiplex bus system and motor drive. Power devices of Metal Oxide
Semiconductor Field Effect Transistor (MOSFET) had experienced technological changes due to the
using of integrated circuit to the switch power, which operated under 100V. By that, power devices
MOSFET become the choice for lower voltage switch power (Juang et al, 2004). This experiment is
aimed to examine the factors that influenced main features of power devices, which are threshold
voltage (VTH), breakdown voltage (BV) and on-resistance (RON). A systematic method is done to get
the optimum level for the value of breakdown voltage and on-resistance.
The experiment is intended to decrease the value of high voltage that lost and at the same time
to stabilize the decreasing value of voltage to the high value. The decreasing value and on-resistance
value are affected by the parameters that used in fabrication in power devices MOSFET that is the
trench depth will influence the ability in the ditch angle thus caused the voltage decreased. The trench
width will make the value of on-resistance is added and high epitaxial thickness will create high on-
resistance. Epitaxial resistivity from doping will make the silicon becomes hot and caused the voltage
decreased. Simulation of fabrication power devices VDMOSFET is done by using ATHENA module,
meanwhile the simulation for electrical examination is done by using ATLAS module from SILVACO
software. This experiment will focus to the four main factors that are trench depth, trench width,
epitaxial thickness and epitaxial resistance. All these optimum factors will lead to the differences in the
value of threshold voltage, breakdown voltage and on-resistance. Parameter for the trench depth is 0.32
μm to 0.34 μm while the parameter for the trench width is 2.85 μm to 3 μm and 6 μm to 7 μm is the
parameter for the thickness epitaxial and for epitaxial resistivity is doping 1.0 x 1013 cm-2 to 1.0 x 1016
cm-2. Optimization for these four factors are explained in Taguchi orthogonal L9 align method which is
making the experiment to investigate the result from four different factors that each of it has three
different value levels. Response of threshold voltage, breakdown voltage and on-resistance are getting
from simulation.

1.1. Power VDMOSFET Transistor

Vertical Double Diffused Metal Oxide Semiconductor Field Effect Transistor (VDMOSFET) is the
combination of LDMOS and VMOS concept. The design of VDMOSFET power transistor is absorbed
with epitaxial layer at various geometrical structures. The characteristics of electrical VDMOSFET
power transistor are threshold voltage, breakdown voltage and on-resistance. The outcomes of these
electrical features are connected to the changes of factors of trench depth, trench width, epitaxial
thickness and epitaxial resistivity. The threshold voltage is between 2V to 3V (Baliga et al, 1996). The
463 H. Abdullah, J. Jurait, A. Lennie, Z.M. Nopiah and I. Ahmad

fallen of BV voltage means the voltage is going down and devices flow are transmitted during the gate
in close. The barrier between terminal supply and the flow while the gate is in open is known as on-
resistance, RON (William et al, 1998). It is the parameter that controls the value of flowing and
spreading power within the devices during it is flow (Locker et al, 1998). According to Chen,
VDMOSFET devices, on-resistance as stated RON = VDS/IDS when the device is closed-circuit. Figure 1
shows all the on-resistance, RON for VDMOSFET devices including the on-resistance that has channel-
resistance, Rch, accumulation-resistance, Ra, JFET resistance, RFET and neck-resistance, REPI.

Figure 1: On-Resistance Transistor Component. a) VDMOSFET and b) UMOSFET (Morancho et al. 1996)

1.2. Optimum Factor Power VDMOSFET Transistor

Analysis on VDMOSFET power transistor is done in order to get high efficiency of devices in its
operation to decrease the power that lost and to maintain the breakdown voltage (BV) at the high scale.
Breakdown voltage value and RON value are influenced by the value factor chosen in the optimum
design with the value set. Many factors are influencing the breakdown voltage and on-resistance. To
get detained voltage 20V and lacking of 25 percent of on-resistance is by maximizing of trench depth,
trench width (Narazaki et al, 2003). Meanwhile, minimize on-resistance value and optimize the factors
for the doping concentration and the thickness of epitaxial layer (Ono et al, 2003). For the factors of
trench depth, the thickness of epitaxial and doping concentration of base-p is considering for the
optimum value of on-resistance (Juang et al, 2004). The epitaxial thickness and resistance in influenced
the effect of decreasing voltage and on-resistance can be related with Craig (2004). Literature review
found out that the trench width factor, the trench depth, the epitaxial thickness and epitaxial resistivity
are important in responded to the value of breakdown voltage and on-resistance.

1.3. Taguchi Ortogonal L9 Array Method

The method using an array set is known as Taguchi orthogonal L9 array method. It gives the
information about the effect of the factors that influence ability of parameters’ decision. The four
factors that were found are having three different value levels and L9 align is the best choice with the
assumption that each factor is not connected. By using S/N ratio and ANOVA Pareto to get the value
in order to know the impact of value set. All these will display the result either the parameter is
sensitively able to change the value level or not. By using ANOVA Pareto, it allows us to make
accurate conclusion for the experiment either the factor is giving dominant effect or minimum effect
(Gologlu and Nazim, 2008). The parameter’s design is important to create the best. Two important
things are using in the creation is S/N ratio to examine the performance factor of noise are:
Biggest the better
⎛1 1 ⎞
S / N = −10 log⎜⎜ ∑ 2 ⎟⎟ (1)
⎝n y ⎠
Smallest the better
Simulation of Fabrication Process VDMOSFET Transistor Using Silvaco Software 464

⎛1 ⎞
S / N = −10 log⎜⎜ ∑ y 2 ⎟⎟ (2)
⎝n ⎠
where y is the average data collected, s y2 is the variant for y, and n is the collected data.

2. Research Method
For this project, two Silvaco modules that used are ANTENA and ATLAS. ANTENA module is for
Deckbuild surrounding interaction and ATLAS module is using with the TonyPlot 1D/2D surrounding
interaction. Four factors the trench depth, trench width, the thickness of epitaxial and epitaxial
resistivity are examined in order to know how breakdown voltage and on-resistance happen. Thus, in
effort to tackle the best parameter of the VDMOSFET power devices, all four factors were used and
variants as shows in Table 1. The value for the variation is chosen according to the result of threshold
voltage value for VDMOSFET power transistor, which is 2V to 3V (Baliga et al, 1996).
Simulation for devices of VDMOSFET power transistor is done by writing fabrication recipe
and electrical simulation towards the environment. Deckbuild with the ANTENA and ATLAS module
are activated and called command “go athena” and “go atlas”. Using of Taguchi orthogonal L9 array
method, nine models are activated to change the parameter for the trench depth between 0.32 to
0.34μm, the trench width between 2.8 to 3 μm, epitaxial resistivity is doping 1.0 x 1013 cm-2 to 1.0 x
1016 cm-2 and for the thickness of epitaxial between 6 μm to 7 μm. The test for electrical feature is done
on devices n-channel and VDMOSFET power transistor, which is the test of threshold voltage,
breakdown voltage and to get on-resistance value. Table 1 shows the L9 array to be inserted into
Variant 4 Factor 3 level.

Table 1: Variant 4 Factor 3 stage of Taguchi method

Set Experiment array Width Depth Thickness Resistance

1 1 2.8 0.32 6 1 x 1016
2 2 2.8 0.33 6.5 1 x 1015
3 3 2.8 0.34 7 1 x 1013
4 4 2.9 0.32 6.5 1 x 1013
5 5 2.9 0.33 7 1 x 1016
6 6 2.9 0.34 6 1 x 1015
7 7 3 0.32 7 1 x 1015
8 8 3 0.33 6 1 x 1013
9 9 3 0.34 6.5 1 x 1016

3. Results and Discussion

In this section of paper discussed the fabrication result of set 1 to 9 that have been done by using
ATHENA module. The result obtained shows from fabrication process and electrical characteristics n-
channel VDMOSFET power transistor device. Beside that, this section also shows the optimization
result of n-channel VDMOSFET power transistor device by using Taguchi method design.

3.1. Result of Device Fabrication

The result from fabrication process to module the n-channel VDMOSFET power transistor device
already patterned by Silvaco (1998) is show in Figure 2. Figure 2 shows the cross-section of
VDMOSFET was used in first set design of Taguchi method L9 array in Table 1. The first set model of
n-channel VDMOSFET power transistor has trench width 2.8 μm, the trench depth 0.32 μm, the
thickness of epitaxial 6 μm and the epitaxial resistivity is doping 1.0 x 1016 cm-2. For threshold voltage
465 H. Abdullah, J. Jurait, A. Lennie, Z.M. Nopiah and I. Ahmad

experiment, the VTH value is taken from bias voltage when direct current is 0.1 V in drain electrode.
Then the gate bias increased around 0 V to 4 V with interval 0.2 V.

Figure 2: Ionization Impact of Breakdown Voltage

The threshold voltage (VTH) experiment have been done when the bias voltage was applied
when direct current at 0.1 V in drain electrode. Then the device has been increased the bias gate around
0 – 4 V with interval 0.2 V. For the simulation result of threshold voltage value displayed in ID –VG
graph below. Figure 3 illustrated the ID –VG graph for all 9 sets of VG value VDMOSFET power
transistor that has been simulated. Table 2 shows the result for VTH value after experiment has done for
all L9 array.

Figure 3: Graph of Threshold Voltage Value in L9 Experiment VDMOSFET

Simulation of Fabrication Process VDMOSFET Transistor Using Silvaco Software 466

The threshold voltage or VTH is a voltage between gate electrode with strong inverse on MOS
device. The VTH value is important to determine the best optimum bias gate value to develop n-type
capasitance in to drain. According to Baliga (1996), the power transistor for MOSFET is in range 2–3
V. Based on Fig. 3, the graph shows the VTH value is around 2 to 3 V, and this value fulfill as the
literiture of this transistor fabrication, and thus it is suitable for power transistor application.

Table 2: Threshold Voltage Value (VTH)

Set Width (µm) Depth (µm) Thickness (µm) Resistance (Ωm) VTH (V)
1 2.8 0.32 6 1 x 1016 2.37927
2 2.8 0.33 6.5 1 x 1015 2.43122
3 2.8 0.34 7 1 x 1013 2.08057
4 2.9 0.32 6.5 1 x 1013 2.25614
5 2.9 0.33 7 1 x 1016 2.43821
6 2.9 0.34 6 1 x 1015 2.57399
7 3 0.32 7 1 x 1015 2.84035
8 3 0.33 6 1 x 1013 2.66165
9 3 0.34 6.5 1 x 1016 2.86387

These complete set can be used to gain breakdown voltage and on-resistance value. For the
breakdown voltage value, it is the voltage that measure at devices that experience falling down and
flowing of electricity during the gate in close. The result of on-resistance is defined as on-resistance
that is the barrier between terminal supplies with the channel while the gate is open. Table 3 shows the
response value for the breakdown voltage, BV and on-resistance. To get RON value by using the
calculation from equation below, the calculation is done for all devices set.
WD
RON = = 5.93x 10-9 (BV)2.5 (3)
qμnNd

Table 3: Response Value for Breakdown Voltage (BV) and On-Resistance (RON)

RON (Ωcm2)
Set Width (µm) Depth (µm) Thickness (µm) Resistance (Ωm) BV (V)
(×10-4)
1 2.85 0.32 6 1 x 1016 55.9805 1.3904
2 2.85 0.33 6.5 1 x 1015 68.0625 2.2663
3 2.85 0.34 7 1 x 1013 71.5469 2.5676
4 2.88 0.32 6.5 1 x 1013 66.9375 2.1738
5 2.88 0.33 7 1 x 1016 65.4961 2.0587
6 2.88 0.34 6 1 x 1015 62.8735 1.8587
7 3.0 0.32 7 1 x 1015 74.0918 2.8020
8 3.0 0.33 6 1 x 1013 62.1406 1.8050
9 3.0 0.34 6.5 1 x 1016 60 1.6536

3.2. Analysis of Effect Factors to Breakdown Voltage Value (BV)

After nine experiments of L9 array have been done, the next step is to determine the required values for
selected factors, which are depth, width, thickness of epitaxial and epitaxial resistivity doping that gave
the effect to devices. Table 4 shows the S/N ratio value for breakdown voltage.
467 H. Abdullah, J. Jurait, A. Lennie, Z.M. Nopiah and I. Ahmad
Table 4: S/N Ratio Value for Breakdown Voltage (BV)

Exp. Design BV Value BV BV Value BV2 Total (BV)2 Average BV S/N Value BV
1 A0B0C0D0 55.981 3133.8164 3133.8164 55.98 44.503161
2 A0B1C1D1 68.063 4632.5039 4632.5039 68.06 46.200583
3 A0B2C2D2 71.547 5118.9589 5118.9589 71.55 46.634242
4 A1B0C1D2 66.938 4480.6289 4480.6289 66.94 46.055815
5 A1B1C2D0 65.496 4289.7391 4289.7391 65.50 45.866734
6 A1B2C0D1 62.874 3953.0770 3953.0770 62.87 45.511778
7 A2B0C2D1 74.092 5489.5948 5489.5948 74.09 46.937828
8 A2B1C0D2 62.141 3861.4542 3861.4542 62.14 45.409934
9 A2B2C1D0 60.000 3600.0000 3600.0000 60.00 45.105450

The S/N value is changing stage four factors with three times changes by using L9 array. This
value can be obtained from breakdown voltage value based on fourth factor. The calculation for S/N
average ratio breakdown voltage is taken and the average for S/N ratio effect using a specific
procedure based on the result. The calculation of S/N ratio for BV was determined by using Eq. 1
(Biggest the better).

3.3. Analysis of Effect Factors to On-Resistance Value (RON)

The next analysis for on-resistance respond toward nine experiments of L9 array have been done to
determine the required values for selected factors, which are depth, width, thickness of epitaxial, and
epitaxial resistivity doping that gave the effect to devices. For the result from calculation of effect
factor Taguchi method was shown in Table 5.

Table 5: S/N Ratio Values for On-Resistance (RON)

RON Value RON RON Value Total (RON)2 Average RON S/N Value
Exp. Design
(×10-4) (RON)2 (×10-8) (×10-8) (×10-4) RON
1 A0B0C0D0 1.39 1.93321 1.93321 1.3904 77.13720
2 A0B1C1D1 2.27 5.13612 5.13612 2.2663 72.89365
3 A0B2C2D2 2.57 6.59257 6.59257 2.5676 71.80945
4 A1B0C1D2 2.17 4.72541 4.72541 2.1738 73.2556
5 A1B1C2D0 2.06 4.23825 4.23825 2.0587 73.7281
6 A1B2C0D1 1.86 3.45477 3.45477 1.8587 74.61581
7 A2B0C2D1 2.80 7.8512 7.8512 2.802 71.05063
8 A2B1C0D2 1.81 -3.25803 3.25803 1.805 74.87045
9 A2B2C1D0 1.65 2.73439 2.73439 1.6536 75.63139

From Table 5, calculation for average ratio of S/N on-resistance taken from S/N average ratio is
according to the specific procedure based on the result table. The calculation of S/N ratio for BV was
determined by using Eq. 2 (Smallest the better)

3.4. Pareto ANOVA Analysis

Other method to analize data from optimum process is Pareto ANOVA (Park et al. 1996). Principle of
ANOVA method were used in this project is same as Pareto principle. Ths work become faster and
accurate when using this method to analize the result based on obtained data without using ANOVA
schedule or F-test. Here is calculation as an example for Pareto ANOVA for breakdown voltage.
From the data in Table 4, the Pareto ANOVA for breakdown has been determined and the
result can be summarized as shown in Table 6. The example of calculations is shown below.
Calculation for Pareto ANOVA for factor (A):
Sum at factor A level 0 = 44.503161 + 46.055815 + 46.937828 + … +
= 137.337985
Simulation of Fabrication Process VDMOSFET Transistor Using Silvaco Software 468

Sum at factor A level 1 = 46.055815 + 45.866734 + 45.511778 +…+

= 137.434327
Sum at factor A level 2 = 46.937828 + 45.409934 + 45.105450 +…+
= 137.453212
Sum of squares of, SA Difference;
= ( A0 − A1 ) + ( A0 − A2 ) + ( A1 − A2 )
2 2 2

= (137.338 - 137.434) + (137.338 - 137.453) + (137.434 - 137.453)

2 2 2

= 0.02292
Total Sum of squares, ST = SA + SB + SC + … + SAC
= 2593.63 + 14135.1 + 426.97 +…+ 475.55
= 41.58285
⎛S ⎞
Contribution ratio (%) = ⎜⎜ A ⎟⎟ x 100
⎝ ST ⎠
⎛ 0.02292 ⎞
⎜ ⎟ × 100
= ⎝ 41.58285 ⎠
= 58.142

Table 6: Pareto analysis ANOVA for breakdown voltage

Factor
Stage factor Total
A B C D
0 137.388 137.497 135.425 135.475
Sum of factor 1 137.434 137.477 137.362 138.65 412.2255
2 137.453 137.251 139.439 138.1
Sum of squares (SA) 0.02292 0.11155 24.1773 17.2711 41.58285
Contribution ratio (%) 0.055 0.268 58.142 41.534 100

From the data in Table 5, the Pareto ANOVA for on-resistance has been determined and the
result can be summarized as shown in Table 7. The examples of calculation were shown below.
Calculation for Pareto ANOVA for factor (A):
Sum at factor A level 0 = 77.137205 + 72.893652 + 71.809453 + …+
= 221.840310
Sum at factor A level 1 = 73.255608 + 73.728139 + 74.615814 +…+
= 221.599561
Sum at factor A level 2 = 71.050637 + 73.728139 + 74.631301 +…+
= 221.552484
Sum of squares of, SA Difference;
= ( A0 − A1 ) + ( A0 − A2 ) + ( A1 − A2 )
2 2 2

= (221.84 - 221.5995) + (221.8403 - 221.5524) + (221.5995 - 221.5524)

2 2 2

= 0.055
Total Sum of squares, ST = SA + SB + SC + … + SAC
= 0.1430 + 0.69696 + 151.1203 + 107.931
= 259.8918
⎛ SA ⎞
Contribution ratio (%) = ⎜⎜ ⎟⎟ x 100
⎝ T⎠
S
⎛ 0.14301 ⎞
=⎜ ⎟ × 100
⎝ 259.8918 ⎠
469 H. Abdullah, J. Jurait, A. Lennie, Z.M. Nopiah and I. Ahmad

= 58.147

Table 7: Pareto analysis ANOVA for on-resistance

Factor
Stage factor Total
A B C D
0 221.84 221.443 226.623 226.496
Sum of factor 1 221.5995 221.492 221.780 218.56 664.9924
2 221.5524 222.056 216.588 219.935
Sum of squares (SA) 0.14302 0.69696 151.12 107.931 259.8918
Contribution ratio (%) 0.055 0.268 58.147 41.529 100

Pareto ANOVA method is suitable for interaction factors condition for analized. Pareto
ANOVA for breakdown voltage and on-resistance can be calculated by using data in Table 4 and 5.
Figure 4 shows the overall result of Pareto ANOVA for breakdown voltage and on-resistance.It shows
that the factor explaining the area in figure Pareto ANOVA is important. We can see that the figure
Pareto ANOVA for breakdown voltage with factor C and D are bigger if we read from left to the right.
The distribution can be read until level 90% starting with C, following by D, B and A. The value
started with 58.142, then 41.534, 0.268 and 0.055. The level 90% is until B factor. Although factor A
and B is not significant for optimum value, but it is chosen based on economic and technical factor.
The optimum values chosen are A2 with value 137.453, B0 with value 137.497 and C2 with value
138.65 also D1 with value 138.65. Pareto ANOVA for breakdown voltage is shown and the result is
explained in table. Thus, the optimal combination of significant factor levels is A2B1C2D1.

Figure 4: Overall result of Pareto ANOVA for breakdown voltage and on-resistance

Pareto ANOVA Analysis forOn-Resistance Pareto ANOVA Analysis for Breakdown

(RON) Voltage (BV)

70 70
Contribution Ratio (%)

Contribution Ratio (%)

58.147 58.142
60 60
50 41.529 50 41.534
40 40
30 30
20 20
10 0.268 0.055 10 0.268 0.055
0 0
C D B A C D B A
Factor Factor

For figure Pareto ANOVA for on-resistance (RON) with factor C and D are bigger if we read
from left to the right. The distribution can be read until level 90% starting with C, following by D, B
and A. This values starting with 58.147, then 41529, 0.268 and lastly 0.055. Although factor A and B
is not significant for optimum value, but it is chosen based on economic and technical factor, The
optimum values chosen are A2 with value 221.552, B0 with value 221.443 and C2 with value 216.558
and D1 with value 218.56. The total result for Pareto ANOVA to show the on resistance value is
shown in table. Thus, the optimal combination of significant factor levels is A2B1C2D1.

4. Conclusion
Taguchi method design is used to develop a systematic design of experiment. This design method gave
9 set experiments. It has many variants that can be applied to modeling device and a lot of parameter
Simulation of Fabrication Process VDMOSFET Transistor Using Silvaco Software 470

can be used. Taguchi method already applied to get a robust and better design. It is proved on time
saving and the result is better according to objective and desired of project. It easily to do 9
experiments compared to 81 experiments that might develop from 4 factors for 3 stages. Then analysis
of Pareto ANOVA shows the factors of trench depth, thickness of epitaxial and epitaxial resistivity are
significant based on 90% confidence level towards breakdown voltage and on-resistance respond. So
that the breakdown value decreased follows the thickness of epitaxial and epitaxial doping. Pareto
ANOVA analysis proved the factors of trench depth, thickness of epitaxial and epitaxial resistivity are
significant towards breakdown voltage. For on-resistance also showed the factors of trench depth,
thickness of epitaxial and epitaxial resistivity are significant based on 90% of the result in Pareto
ANOVA figure. The on-resistance value increased follows the thickness of epitaxial and epitaxial
resistivity, but the on-resistance decreased when trench depth increased. Pareto ANOVA analysis also
proved the factors of epitaxial resistivity, thickness of epitaxial and trench depth are significant
towards on-resistance respond.

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