1.

Determine by means of a truth table the validity of DeMorgan's

theorem for three variables: (ABC)' = A' + B' + C'

A B C A’ B’ C’ A’+B’+C’ ABC (ABC)’

0 0 0 1 1 1 1 0 1
0 0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0 1
0 1 1 1 0 0 1 0 1
1 0 0 0 1 1 1 0 1
1 0 1 0 1 0 1 0 1
1 1 0 0 0 1 1 0 1
1 1 1 0 0 0 0 1 0

From the above truth table: (ABC)’=A’+B’+C’

2. Simplify the following expressions using Boolean algebra:

a. A + AB
b. AB + AB'
c. AB + A(CD + CD')

a.A+AB=A(1+B)=A.1=A

b.AB+AB’=A(B+B’)=A.1=A

C.AB+A(CD+CD’)=AB+A[C(D+D’)]=AB+A[C.1]=AB+A[C]=AB+AC=A(B+C)

3. Using DeMorgan's theorem or other techniques, show that:

a. (A + B)'(A' + B')' = 0
b. A + A'B + A'B' = 1

a.(A+B)’(A’+B’)’:

(A+B)’=A’B’, (A’+B’)’=(A’)’(B’)’=AB  (A+B)’(A’+B’)’=A’B’AB=(A’A)(B’B)=(0)(0)=0

b. A + A'B + A'B' =A+A’(B+B’)=A+A’(1)=A+A’=1

4. (3 pts) Given the Boolean function:

F = xy'z + x'y'z + xyz

a. List the truth table of the function

b. Draw the logic diagram using the original Boolean expression
c. Simplify the algebraic expression using Boolean algebra
d. List the truth table of the function from the simplified
expression and show that it is the same as the truth table in
part (a)
e. Draw the logic diagram from the simplied expression and
compare the total number of gates with the diagram of part (b)

a.

x y z xy'z x'y'z xyz F

0 0 0 0 0 0 0
0 0 1 0 1 0 1
0 1 0 0 0 0 0
0 1 1 0 0 0 0
1 0 0 0 0 0 0
1 0 1 1 0 0 1
1 1 0 0 0 0 0
1 1 1 0 0 1 1

b.

c.

F = xy'z + x'y'z + xyz=(x+x’)y’z+xyz=(1)y’z+xyz=y’z+xyz=(y’+xy)z

d.
 x y z y'z xyz F
0 0 0 0 0 0
0 0 1 1 0 1
0 1 0 0 0 0
0 1 1 0 0 0
1 0 0 0 0 0
1 0 1 1 0 1
1 1 0 0 0 0
1 1 1 0 1 1

Truth table values of F in 4.a and 4.d are the same, hence F = xy'z + x'y'z + xyz and F=y’z+xyz are the
same.

e.

Number of gates for the simplified F is 3 while for the original F was 4 (see 4.b). Therefore, for the
simplified F, there is one less gate.

5. (2 pts) Simplify the following Boolean functions using three-variable maps.

a. F(x,y,z) = sigma (0,1,5,7)
b. F(x,y,z) = sigma (1,2,3,6,7)

a.

three-variable maps approach:

yz: 00 yz: 01 yz: 11 yz: 10

x:0 1 1
x:1 1 1

From the above map, F(x,y,z) = sigma (0,1,5,7)=x’y’+xz

Boolean algebra approach:

x y z F
0 0 0 1
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
From the above truth table:

F=x’y’z’+x’y’z+xy’z+xyz=x’y’(z’+z)+x(y’+y)z=x’y’(1)+x(1)z=x’y’+xz

b.

three-variable maps approach:

yz: 00 yz: 01 yz: 11 yz: 10

x:0 1 1 1
x:1 1 1

From the above map, F(x,y,z) = sigma (1,2,3,6,7)=x’z+y

6. Simplify the following expression in (1) sum-of-

products form and
(2) product-of-sums form.

x'z' + y'z' + yz' + xy

a.

x y z x’z’ y'z’ yz’ xy F

0 0 0 1 1 0 0 1
0 0 1 0 1 0 0 1
0 1 0 1 0 1 0 1
0 1 1 0 0 0 0 0
1 0 0 0 0 0 0 0
1 0 1 0 0 0 0 0
1 1 0 0 0 1 1 1
1 1 1 0 0 0 1 1
F(x,y,z) = sigma (0,1,2,6,7)

b.

three-variable maps approach:

yz: 00 yz: 01 yz: 11 yz: 10

x:0 1 1 0 1
x:1 1 1

From the above map, F(x,y,z) = sigma (0,1,2,6,7)=x’y’+xy+yz’

7. Show that a JK flip-flop can be converted to a D flip-flop with

an inverter between the J and K inputs.

Excitation Table For a JK Flip Flop ("X" is "don't care")

Previous State -> Present State J K

0 -> 0 0 X

0 -> 1 1 X

1 -> 0 X 1

1 -> 1 X 0

Characteristic equation Q(t+1) = JQ' + K'Q

Excitation Table For a D Flip Flop

Previous State -> Present State D

0 -> 0 0 Characteristic equation Q(t+1) = D

0 -> 1 1 When there is a NOT gate between J and K inputs of a JK flip-flop,

we have J=K’. If J=K’ then the characteristic equation of the JK flip-
1 -> 0 0 flap becomes:

1 -> 1 1 Q(t+1) = JQ' + K'Q=JQ’+JQ=J(Q’+Q)=J(1)=J

This equation is the same characteristic equation of the D flip-flop.

Therefore, JK flip-flop can be converted to a D flip-flop with an inverter between the J and K inputs.

8. Using the information from the characteristic table of the JK flip-flop

listed in figure 1-21b of textbook, derive the excitation table for the JK
flip-flop and compare your answer with Table 1-3 of textbook.

From characteristic table:

J K Q(t+1)
0 0 Q(t)
0 0 0
0 1 1
0 1 Q(t)’

We derive the following excitation table:

Q(t) Q(t+1) J K
0 0 0 0,1 or X
0 0 1 0,1 or X
0 1 0,1 or X 1
0 1 0,1 or X 0

9. (2 pts) Design a 2-bit down counter. This is a sequential circuit with

two flip-flops and one input x. When x = 0, the state of the flip-flops
does not change. When x = 1, the state sequence is 11, 10, 01, 00, 11, and
repeat.

Q1 Q0 x Q1(t+1) Q0(t+1)
0 0 0 0 0
0 0 1 1 1
0 1 0 0 1
0 1 1 0 0
1 0 0 1 0
1 0 1 0 1
1 1 0 1 1
1 1 1 1 0

Q1(t+1):
 Q1Q0: 00 Q1Q0: 01 Q1Q0: 11 Q1Q0: 10
x:0 1 1
x:1 1 1

First D Flip-Flop: D1=Q1Q0+x’Q1+xQ1’Q0’

Q0(t+1):

Q1Q0: 00 Q1Q0: 01 Q1Q0: 11 Q1Q0: 10

x:0 1 1
x:1 1 1

Second D Flip-Flop: D0=x’Q0+xQ0’

 Q1

Q0

D PR Q Q1

CLK
Q1
CLR Q Q1'
2
1

X
Q1'
Q0'

Q0'

D PR Q Q0

CLK

Q0 CLR Q Q0'
CLK

10. Construct a 5-to-32 line decoder with four 3-to-8 line decoders with
enable and one 2-to-4 line decoder. Use block diagrams similar to figure 2-3
in textbook.
11. TTL SSI come mostly in 14-pin IC packages. Two pins are reserved for power
supply and the other pins are used for input and output terminals. How many
circuits are included in one such package if it contains the following type of
circuits? (a) inverters; (b) two-input exclusive-OR gates, (c) three-input OR
gates, (d) four-input AND gates.

(a)6

(b)4

(c) 3

(d)2

12. Modify the decoder of figure 2-2 of textbook so that the circuit is enabled
when E = 1 and disabled when E = 0. List the modified truth table.
You just need to eliminate the NOT gate from E input:

D0

A0 D1

D2

A1 D3

E A1 A0 D0 D1 D2 D3
1 0 0 0 1 1 1
1 0 1 1 0 1 1
1 1 0 1 1 0 1
1 1 1 1 1 1 0
0 x x 1 1 1 1

13. Construct a 16-to-1 line multiplexer with two 8-to-1 line multiplexers and
one 2-to-1 line multiplexer. Use block diagrams for the three multiplexers.
 A
B
C

D0
D1
D2 O
D3
D4
D5
D6
D7

1
A
Y
2
B
D

A
B
C

D8
D9
D10 O
D11
D12
D13
D14
D15

14. What is the purpose of the buffer gate in the clock input of the register of
figure 2-7 of textbook?

One clock signal provides needed clock of many gates, so that may not provide enough current for many
gates. To solve this problem and to increase the “fan-out”, a buffer gate is added behind the clock signal
of a couple of gates.

15. What is the difference between serial and parallel transfer? Using a shift
register with parallel load, explain how to convert serial input data to parallel
output and parallel input data to serial output.
In serial transfer, one bit per clock is transferred, while in parallel one, several bits with one clock are
transferred.

Serial-in, parallel-out (SIPO):

This configuration allows conversion from serial to parallel format. Data is input serially. Once the data
has been input, it may be either read off at each output simultaneously, or it can be shifted out and
replaced.

4-Bit SIPO Shift Register

Parallel-in, serial-out (PISO):

This configuration has the data input on lines D1 through D4 in parallel format. To write the data to the
register, the Write/Shift control line must be held LOW. To shift the data, the W/S control line is brought
HIGH and the registers are clocked. The arrangement now acts as a PISO shift register, with D1 as the
Data Input. However, as long as the number of clock cycles is not more than the length of the data-
string, the Data Output, Q, will be the parallel data read off in order.
4-Bit PISO Shift Register

16. Include a two-input AND gate with the register of figure 2-6 in textbook and
connect the gate output to the clock inputs of all the flip-flops. One input of the
AND gate receives the clock pulses from the clock pulse generator. The other input
of the AND gate provides a parallel load contral. Explain the operation of the
modified register.

The second input of the AND works as the enable pin of the register. When its 1 the input clock will be
accessible for the flip-flops and the four inputs can be loaded to the flip-flops.

17. The content of a 4-bit register is initially 1101. The register is shifted six
times to the right with the serial input being 101101. What is the content of the
register after each shift? 1011
101101

1 1 0 1

1 1 1 0
0 1 1 1
1 0 1 1
1 1 0 1

0 1 1 0
1 0 1 1