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2-Stage Operational Amplifier with RC Compensation

1.Content:
Please design a 2-stage OPAMP with RC compensation circuitry. The detailed
circuits are shown in Fig.1 and Fig.2.

VDD

RB Q3 Q4

M3 M4 Q8
Q6
Cc Q10 Vout
Q1 Q2
Vin- Vin+
Cstart Q11
CL=2pF

Vbias Q7 Q9
M1
Q5
M2

Vss

Fig.1 The circuit diagram of a 2-stage operational amplifier with RC compensation


circuitry and constant-gm current source. (CL =2pF)

Vin-

Vout

VIN+
CL=2pF

VSS

Fig.2 The function block for the operational amplifier shown in Fig.1

This OPAMP consists of an NMOS input differential pair Q1~Q5, followed by the
push-pull output stage Q6~Q9. To increase the phase margin, it is compensated by the
serial RCCC compensation circuit, where RC is formed by the complementary transistors
Q10 and Q11. Note that TSMC 0.35um 2P4M CMOS process, used in this contest, NMOS
is fabricated on the P-Substrate. That means the body of NMOS must be connected to
P-substrate, and NMOS may have body effect if its source is not connected to
P-substrate.
To avoid the effect of the power supply voltage variation, a supply-independent bias
circuitry is used. As shown in Fig.1, the constant-gm current source, which consists of
M1~M4 and RB, is used to bias the Q5 and Q7. This current source always requires a
startup circuit to stabilize the circuit and Cstart is the simple way to perform the startup. In
addition, the resistors RB must be implemented by poly-resistors for optimum accuracy.
The designer should design this OPAMP to achieve low power consumption and the
high performance. All components should be carefully optimized for the specification
which will be defined in the following sections.

2.Design requirement:

Please design this OPAMP and bias generator with the TSMC 0.35um 3.3V
2P4M CMOS process parameter. The device model is HSPICE Level 49.The
final results should include the net-list, the layout and all verification files
(DRC and LVS).
This OPAMP operates in the temperature 65℃, with the voltage supply
VDD=3V, VSS=0V and the output loading CL=2pF. The OPAMP should fit
the following specifications under the typical transistor

parameters:

1. The Specification for Open Loop Topology (CL, shown in Fig.1, should be
included during the simulation)
Assume that the common-mode DC level of the differential input signal is 1.5V.
Try to maximize the differential gain Av = Vout/Vin ≧ 60dB when Vout=1.5V.
(shown in the following figure)

+ Vout
Vin

Vcm=1.5V
CL
Vcm=1.5V

VSS

The common-mode gain Acm = Vout/Vic 0dB (shown in the following


figure)

Vic Vout

CL
Vcm=1.5V

VSS

DC gain ≧ 60dB
Phase margin ≧ 60°
Output swing: (VSS + 0.5) ≦ Vout ≦ (VDD - 0.5V)
Apply Vcm=1.5V, unity gain bandwidth ≧ 150MHz
The DC current≦2.5mA (with Vin+ =Vin- =1.5V)
Apply Vin+ =Vin- =1.5V, the input offset≦5mV

2. The Specification for Close Loop Topology (The close-loop topology is shown in the
following figure)

VIN-

Vout

VIN+
CL

VSS

Apply 1MHz sine waveform with amplitude 1V and DC 1.5V to the input Vin
with .FFT analysis command in HSPICE, find the total-harmonic-distortion
(THD) for this OPAMP.
Apply a pulse to the input Vin. The low voltage level of the pulse is 1V, and
the high voltage level is 2V. The transition time of the rising edge and falling
edge is 1ns. With .MEASURE analysis command in HSPICE, find the settling
time (both in rising edge and falling edge) when Vout settle to within 0.3% of
the final voltage.(ΔV≦0.003*(2V-1V)=0.003V).
Apply the above-mentioned pulse to the input with .MEASURE analysis
command in HSPICE, find the slew rate (both the rising edge and falling edge).
Vout

0.3%
2V
1ns 1nS ΔV≦0.003*1V

2V

1V
1V Settling Time

3. Summary the specifications, described above, to the following table:

Open Loop Characterization


Items Specification Pre- Post-
Simulation Simulation
Results Results
Differential Gain ≧ 60dB
Common-mode Gain ≦ 0dB
Phase Margin ≧ 60°
Output Swing (VSS+0.5)≦Vout≦(VDD-0.5V)
Unity Gain Bandwidth ≧ 150 MHz
Current Consumption ≦ 2.5 mA
Offset Voltage ≦ 5 mV
Unity Gain Close Loop Characterization
Items Specification Pre- Post-
Simulation Simulation
Results Results
THD ≦ 0.5 %
Settling Time to 0.3% ≦ 200 ns
Slew Rate ≧ 60 V/µs
Layout Area ≦ 6000(µm)2

To measure the performance correctly, the input and output pins should have the
following names:
Input : VINP,VINM
Output : VOUT
Power : VDD Ground : VSS
3.Contest Description:
This design doesn't include the I/O pad.
The capacitor CL is only for simulation purpose. It doesn’t need to be drawn in
the layout. However, both the compensation capacitor Cc and startup capacitor
Cstart are the components of the OPAMP, and they should be drawn in the
layout.
The performance of the OPAMP is measured with the result of the
post-simulation. We suggest the designers to reserve some design margin for
the specification in the pre-simulation. Probably, there will be no time to
re-simulate the circuit and modify the layout when the designer finds that the
performance of the post-simulation fails to meet the required specification.
以下說明請務必詳讀及遵守:

使用EDA說明:
A. Simulation : Hspice
B. Layout : Virtuoso or Laker
C. Verification : Calibre for DRC, LVS, and xCalibre for
PEX(寄生元件粹取僅需選用C,不需用RC或RCC)
上傳資料說明:
A. Netlist file :由xCalibre輸出含寄生電容之subckt格式Netlist檔,
檔名為opamp.cir,top cell名稱為opamp,輸入端節
點名稱必須為VINP、VINM,輸出端節點名稱為
VOUT,電源與接地為VDD!及VSS!(輸出端不含
CL)共五個節點,可參考以下範例:

.subckt opamp VINP VINM VOUT VDD! GND!


MM1 net1 net2 VDD! VDD! pch l=x w=y
…..
…..
.ends

B. Layout file :GDSII檔案格式之佈局結果輸出檔(opamp.gds),top


cell名稱為opamp
C. DRC結果檔:Calibre DRC結果檔,DRC不需做antenna check,
檔名必須為opamp.drc.summary且僅容許Vertex
Offgrid及Metal Density之error
D. LVS結果檔:Calibre LVS結果檔,檔名必須為opamp.lvs.report,
其結果需為error free
請 將 以 上 opamp.cir 、 opamp.gds 、 opamp.drc.summary 、
opamp.lvs.report及report.000等五個檔案tar成一個檔案,檔名為
grad_analog_xxx.tar(其中xxx為隊名),然後依據規定上傳至指
定ftp server。
National Taiwan University:iccftp.ee.ntu.edu.tw (140.112.20.85)
Chip Implementation Center:iccftp.cic.org.tw(140.126.24.6)
Chip Implementation Center (South region office): iccftp1.cic.org.tw(140.110.117.20)
National Cheng Kung University:iccftp.ee.ncku.edu.tw (140.116.156.55)

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