IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO.

7, JULY 2000 1039

A Family of Low-Power Truly Modular Programmable Dividers

in Standard 0.35-m CMOS Technology
Cicero S. Vaucher, Igor Ferencic, Matthias Locher, Sebastian Sedvallson, Urs Voegeli, and Zhenhua Wang

Abstract—A truly modular and power-scalable architecture for

low-power programmable frequency dividers is presented. The ar-
chitecture was used in the realization of a family of low-power fully
programmable divider circuits, which consists of a 17-bit UHF di-
vider, an 18-bit -band divider, and a 12-bit reference divider. Key
circuits of the architecture are 2/3 divider cells, which share the
same logic and the same circuit implementation. The current con-
sumption of each cell can be determined with a simple power opti-
mization procedure. The implementation of the 2/3 divider cells is
presented, the power optimization procedure is described, and the
input amplifiers are briefly discussed. The circuits were processed
in a standard 0.35 m bulk CMOS technology, and work with a
nominal supply voltage of 2.2 V. The power efficiency of the UHF
divider is 0.77 GHz/mW, and of the -band divider, 0.57 GHz/mW.
Fig. 1. Fully programmable divider based on a dual-modulus prescaler.
The measured input sensitivity is 10 mVrms for the UHF divider,
and 20 mVrms for the -band divider.
Index Terms—CMOS integrated circuits, current-mode logic, time-to-market demands architectures providing easy optimiza-
frequency synthesizers, phase-locked loop, programmable fre- tion of power dissipation, fast design time and simple layout
quency counter, programmable frequency divider. work. High reusability, in turn, requires an architecture which
provides easy adaptation of the input frequency range and of
I. INTRODUCTION the maximum and minimum division ratios of existing designs.
The choice of the divider architecture is therefore essential

T HE feasibility of RF functions implemented in CMOS

technology has been demonstrated by a.o. the work
presented in [1]–[3]. They show that the scaling of CMOS
technologies to deep submicron has made CMOS a technolog-
ical option for the low-gigahertz frequency range. However, for
CMOS to become a commercial option for RF building blocks
requires compliance to all trends of the consumer market:
miniaturization, low cost, high reliability and long battery
lifetime. Bulk CMOS technologies presently available satisfy
the low cost and reliability trends by standard design practice.
Complying to miniaturization and long battery lifetime, on the
other hand, demands CMOS building blocks with low-power
dissipation and good electromagnetic compatibility (EMC)
characteristics. A critical RF function in this context is the
frequency synthesizer, more particularly the programmable
frequency divider. The divider consists of logic gates which
operate at (or close to) the highest RF frequency. Due to the
divider’s complexity, high operation frequency normally leads
to high power dissipation.
Other crucial aspects of the present-day consumer electronics
industry are the short time available for the introduction of new
products in the market, and the short product lifetime. On top
of that, the lifespan of a given CMOS technology is also short,
due to the aggressive scaling of minimum feature sizes. Short
Manuscript received November 16, 1999; revised January 24, 2000.
C. S. Vaucher is with the Philips Research Laboratories, 5656AA Eindhoven,
The Netherlands.
I. Ferencic, M. Locher, S. Sedvallson, U. Voegeli, and Z. Wang are with
Philips Semiconductors Zurich, 8045 Zurich, Switzerland.
Publisher Item Identifier S 0018-9200(00)03878-6.
0018–9200/00$10.00 © 2000 IEEE
for achieving low-power dissipation, high design flexibility and
high reusability of existing building blocks. A modular architec-
ture complies with these requirements, as shall be demonstrated
in this paper. The focus of the paper is first on the truly modular
architecture and on the implementation of the circuits. Then the
power optimization procedure and the design of the input am-
plifier are briefly discussed. Finally, a collection of measured
data and the conclusions are presented.
II. PROGRAMMABLE DIVIDER ARCHITECTURES
A. Architecture Based on a Dual-Modulus Prescaler
Fig. 1 depicts the divider architecture based on a dual-mod-
ulus prescaler [4], [5]. The design of the dual-modulus prescaler
itself has been extensively treated in the literature [4], [6]–[10].
On the other hand, the architecture of Fig. 1 has some undesir-
able characteristics. One readily notices the lack of modularity
of the concept: besides the dual-modulus prescaler, the archi-
tecture requires two additional counters for the generation of a
given division ratio. The programmable counters—which are, in
fact, fully programmable dividers, albeit not operating at the full
RF frequency—represent a substantial load at the output of the
dual-modulus prescaler, so that power dissipation is increased.
Besides, the additional design and layout effort required for
the programmable counters increase the time-to-market of new
products. These properties led us to conclude that the dual-mod-
ulus-based architecture is not an interesting option for the real-
ization of building blocks with high reusability, high flexibility,
and short design time.

Authorized licensed use limited to: Liang-Hsuan Lu. Downloaded on January 11, 2009 at 22:18 from IEEE Xplore. Restrictions apply.
1040
(a)
(b)
Fig. 2. Programmable prescaler. (a) Basic architecture. (b) With extended division range.
B. Programmable Prescaler Architectures
The “basic” programmable prescaler architecture is depicted
in Fig. 2(a). The modular structure consists of a chain of 2/3 di-
vider cells connected like a ripple counter [11]. The structure
of Fig. 2(a) is characterized by the absence of long delay loops,
as feedback lines are only present between adjacent cells. This
“local feedback” enables simple optimization of power dissipa-
tion. Another advantage is that the topology of the different cells
in the prescaler is the same, therefore facilitating layout work.
The architecture of Fig. 2(a) resembles the one presented in [12],
which is also based on 2/3 divider cells. Yet there are two fun-
damental differences. First, in [12] all cells operate at the same
(high) current level. Second, the architecture of [12] relies on
a common strobe signal shared by all cells. This leads to high
power dissipation, because of high requirements on the slope of
the strobe signal, in combination with the high load presented
by all cells in parallel.
The programmable prescaler operates as follows. Once in a
division period, the last cell on the chain generates the signal
This signal then propagates “up” the chain, being re-
clocked by each cell along the way. An active mod signal en-
ables a cell to divide by 3 (once in a division cycle), provided
that its programming input is set to 1. Division by 3 adds one
extra period of each cell’s input signal to the period of the output
signal. Hence, a chain of 2/3 cells provides an output signal
with a period of
(1)
In (1), is the period of the input signal , and
are the binary programming values of the cells 1
to respectively. The equation shows that all integer division
ratios ranging from (if all = 0) to (if all = applications.
Authorized licensed use limited to: Liang-Hsuan Lu. Downloaded on January 11, 2009 at 22:18 from IEEE Xplore. Restrictions apply.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 7, JULY 2000
1) can be realized. The division range is thus rather limited,
amounting to roughly a factor two between maximum and
minimum division ratios.1 The division range can be extended
by combining the prescaler with a set-reset counter [13]. In that
case, however, the resulting architecture is no longer modular.
The divider implementation presented in Fig. 2(b) extends
the division range of the basic prescaler, whilst maintaining the
modularity of the basic architecture [14]. The operation of the
new architecture is based on the direct relation between the per-
formed division ratio and the bus programmed division word
Let us introduce the concept of effective
length of the chain. It is the number of divider cells that are
effectively influencing the division cycle. Deliberately setting
the mod input of a certain 2/3 cell to the active level overrules
the influence of all cells to the right of that cell. The divider
chain behaves as if it has been shortened. The required effective
length corresponds to the index of the most significative (and
active) bit of the programmed division word. Only a few extra
OR gates are required to adapt to the programmed division
word, as depicted on the right side of Fig. 2.
With the additional logic the division range becomes:
• minimum division ratio: ;
• maximum division ratio: .
We see that the minimum and maximum division ratios can be
set independently, by choice of and respectively. Subse-
quent changes in an optimized design can be realized with low
risk. A somewhat similar technique, applied to an asynchronous
programmable counter, is described in [9].
III. TRULY MODULAR PROGRAMMABLE DIVIDERS FAMILY
A. Realized Circuits
The modular architecture of Fig. 2(b) was applied in the re-
alization of a family of fully programmable frequency dividers.
1In principle, it is also possible to divide by 3 , but the gap between this
value and the continuous division range makes it useless in standard synthesizer
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 7, JULY 2000
Fig. 3. Family of truly modular programmable dividers, and corresponding division range of the different implementations.
Fig. 4. Functional blocks and logical implementation of a 2/3 divider cell.
Three circuits were implemented: an 18-bit -band divider, a
17-bit UHF divider, and a 12-bit reference divider. The architec-
ture and the division range of the dividers is presented in Fig. 3.
The -band divider was used as the basis for the UHF and for
the reference divider. The UHF divider consists of the same cir-
cuitry as the -band divider, except for the first 2/3 cell, which
was removed. The reference divider is simply the -band di-
vider stripped off its six high frequency cells.
B. Logic Implementation of the 2/3 Divider Cells
A 2/3 divider cell comprises two functional blocks, as de-
picted in Fig. 4. The prescaler logic block divides, upon control
by the end-of-cycle logic, the frequency of the input signal
either by 2 or by 3, and outputs the divided clock signal to the
next cell in the chain. The end-of-cycle logic determines the mo-
mentaneous division ratio of the cell, based on the state of the
and signals. The signal becomes active once
in a division cycle. At that moment, the state of the input is
checked, and if = 1, the end-of-cycle logic forces the prescaler
Authorized licensed use limited to: Liang-Hsuan Lu. Downloaded on January 11, 2009 at 22:18 from IEEE Xplore. Restrictions apply.
1041
Fig. 5. SCL implementation of an AND gate combined with a latch function.
to swallow one extra period of the input signal. In other words,
the cell divides by 3. If = 0, the cell stays in division by 2
mode. Regardless of the state of the input, the end-of-cycle
logic reclocks the signal, and outputs it to the preceding
cell in the chain signal).
C. Circuit Implementation of the 2/3 Divider Cells
The use of standard rail-to-rail CMOS logic techniques
makes the integration of digital functions with sensitive RF
signal processing blocks difficult, due to the generation of large
supply and substrate disturbances during logic transitions.
Source coupled logic (SCL), often referred to as MOS current
mode logic (MCML), has better EMC properties, because of
the constant supply current and differential voltage switching
operation [8]. Besides, SCL has lower power dissipation than
rail-to-rail logic, for (very) high input frequencies [15].
The logic functions of the 2/3 cells are implemented with the
SCL structure presented in Fig. 5. The logic tree combines an
AND gate with a latch function. Three AND_latch circuits are
1042
Fig. 6. Transient simulation of optimized L-band divider.
used to implement Dlatch1, Dlatch3, Dlatch4 and the AND gates
of the 2/3 cells (see Fig. 4). Therefore, six logic functions are
achieved, at the expense of three tail currents only. Dlatch2 is
implemented as a “normal” D latch (without the differential pair
connected to the b–bn inputs).
The nominal voltage swing is set to 500 mV in the high fre-
quency (and high current) cells, and to 300 mV in the low cur-
rent cells A). The voltage is generated by the tail
current, set by the current source and by the load resistances
D. Power Dissipation Optimization
The absence of long delay loops in the architecture of Fig. 2
enables fast and reliable optimization of power dissipation,
since simulation runs may be done for clusters of two cells
each time.
The critical point in the operation of the programmable
prescaler are the divide by 3 actions [11]. There is a maximum
delay between the mod and the clock signals in a given cell that
still allows properly timed division by 3. The maximum delay
is where is the period of the cell’s input
signal. The input frequency for each cell is scaled down by the
previous one. As a consequence, the maximum allowed delay
increases as one moves “down” the chain. As the delay in a cell
is inverse proportional to the cell’s current consumption (which
is a property of current mode logic circuits), the currents in the
cells may be scaled down as well.
The results of a transient simulation with the optimized high
frequency cells of the -band divider are presented in Fig. 6.
The influence of current consumption on the slope of the dig-
ital signals (and hence on the time delay) is clearly observed.
Table I presents the tail current and the resistance values of the
optimized divider cells. Layout optimization took about three
iteration cycles. Transient simulations, including extracted par-
asitics, showed that layout parasitics caused a decrease of about
30% in the highest operation frequency, when compared to the
original simulations.
E. Input Amplifiers
The input amplifier provides the required amplification of the
voltage-controlled oscillator (VCO) signal to “digital” levels,
determined by the sensitivity specifications and by the divider
Authorized licensed use limited to: Liang-Hsuan Lu. Downloaded on January 11, 2009 at 22:18 from IEEE Xplore. Restrictions apply.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 7, JULY 2000
TABLE I
SCALING OF CURRENTS IN THE 2/3 DIVIDER CELLS
circuitry. High input sensitivity enables the divider to be directly
coupled to a wide range of VCO’s, without the need for external
(discrete) buffers. In addition, the input amplifier performs other
important functions, which are listed below.
• It provides reverse isolation, to prevent the divider activity
from “kicking-back” and disturbing the VCO.
• It provides single-ended to differential conversion of the
(very often) single-ended VCO signal.
• It enables the VCO to be ac coupled to the divider func-
tion, and provides a signal to the first divider cell with the
proper dc level.
The required amplification of the UHF amplifier, set by sensi-
tivity requirements ( 20 dBm), has been split into two differen-
tial stages. Each differential pair operates with 50- A nominal
current, and has load resistances of 14 k The -band input
amplifier is a scaled version of the UHF input amplifier. The tail
currents were doubled, and the drain resistances were halved.
The nominal low frequency small signal gain of the UHF ampli-
fier is 26 dB; the gain of the -band amplifier is 23 dB. Negative
feedback from the output node to the input was implemented
with 50 k resistances. The feedback provides dc biasing to the
first stage, and allows AC coupling of the VCO signal to the first
differential pair.
IV. MEASUREMENTS
The control currents for the UHF and -band dividers can be
set externally, through input pins. The input amplifier current is
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 7, JULY 2000 1043

Fig. 7. Sensitivity of the UHF divider, for different divider current settings. Division ratio = 511, nominal current is I = 10 A.

Fig. 8. Sensitivity curves of the L-band divider, for a few divider and amplifier current settings. Division ratio = 1023.

Fig. 9. Maximum operation frequency of the UHF and L-band dividers, as Fig. 10. Minimum input level for correct division of the frequency dividers,
function of divider current consumption (excluding input amplifiers). as function of the input amplifiers consumption.

by a differential input signal, carried over printed circuit board

controlled by the input current and the 2/3 divider cell cur- (PCB) strip-lines with a characteristic impedance of 50 The
rents by input current The curves presented in this section strip-lines were terminated with discrete resistances of 50 to
were obtained with the nominal supply voltage of 2.2 V, except ground, which were set close to the input leads of the input am-
where otherwise noted. plifiers. The maximum operation frequencies of the UHF and
-band dividers, as function of the current consumption, are
A. Input Sensitivity and Maximum Operation Frequency plotted in Fig. 9. The effect of the input amplifiers current con-
Fig. 7 presents sensitivity curves of UHF divider, for different sumption on the input sensitivities is displayed Fig. 10. Setting
current settings of the control current The nominal value of the UHF amplifier current to 230 A yields a sensitivity value
is 10 A. Fig. 8 shows sensitivity curves of the -band di- in excess of 10 mVrms.
vider, for different current settings in the divider and input am- The influence of the supply voltage on the maximum oper-
plifier. Such as the UHF divider, the -band divider is highly ating frequency was found to be small ( 5% for decreased
sensitive over a large frequency range. The circuits were driven from 2.2 V down to 1.8 V). It is interesting to mention that

Authorized licensed use limited to: Liang-Hsuan Lu. Downloaded on January 11, 2009 at 22:18 from IEEE Xplore. Restrictions apply.
1044
Fig. 11. Phase noise of the reference and UHF divider, measured at 10 MHz. - - - Reference divider (I
— Reference divider (I = 10 , F = 20 MHz, 20 dBm). 0
Fig. 12. Comparison of power efficiency (GHz/mW).
MCML circuits have been demonstrated to operate with supply
voltages as low as 1.2 V [15], without significant loss of speed.
B. Phase Noise
The phase noise of the UHF and reference dividers was
measured with a dedicated phase noise measurement system.
We used coherent demodulation techniques (phase-locked
loop configuration), and employed a low-noise 10 MHz signal
source during the evaluation of the circuits. To facilitate the
measurements, we implemented signal taps on the output
of certain cells on the divider chain. The UHF divider was
provided with a tap on the output of its sixth cell; the
reference divider had the output of the first cell tapped.
Fig. 11 presents the phase noise of the UHF divider, with
nominal settings for the supply current. The straight lines rep-
resent measured phase noise of the reference divider. We see a
dependency of the noise floor of the reference divider on the
Authorized licensed use limited to: Liang-Hsuan Lu. Downloaded on January 11, 2009 at 22:18 from IEEE Xplore. Restrictions apply.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 7, JULY 2000
= 10 , F = 20 MHz, 010 dBm).
level of the 20-MHz input signal. For the UHF divider, how-
ever, no dependency of the noise floor on the level of the input
signal at 640 MHz was observed. An increase of 25% in current
led to a change in noise floor from 122 dBc/Hz (nominal bias,
= 10 A) to 124 dBc/Hz (with = 12.5 A). The noise
floor of the reference divider went from 127.5 dBc/Hz down
to 130 dBc/Hz, with increased bias. Fig. 11 shows that the
high frequency cells of the UHF divider (see Fig. 3) contribute
significantly to the phase noise, specially in the “ region.”
An increase of noise of about 15 dB is observed, compared
to the noise of the single reference divider’s cell.
C. Power Efficiency
Fig. 12 presents the power efficiency of the UHF and -band
dividers, in comparison to recently published data on low-power
dividers and tuning systems. Power efficiency is defined here as
the ratio of the divider’s maximum operation frequency to its
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 7, JULY 2000
power dissipation, with dimensions of GHz/mW. The authors
have found that (most of) the dividers presented in the literature
do not include an input amplifier. Therefore, only the current
consumption of the “core” divider circuits is taken in the calcu-
lations. This leads to a fair comparison of the available data.
Refs. [2] and [8] describe prescalers implemented in bulk
CMOS technology. Reference [16] proposes a new synthe-
sizer architecture, where the divider is “powered-down” after
lock has been achieved. Ref. [14] describes a fully pro-
grammable divider implemented in an ultrathin-film 0.25- m
CMOS/SIMOX process. The CMOS/SIMOX divider power
efficiency is about 30% higher than the -band divider’s. Our
divider, however, is implemented in a standard 0.35- m bulk
technology. The power efficiency of a bipolar dual-modulus
prescaler [6] included as well, for technology benchmarking.
Its power efficiency is similar to the power efficiency of
the CMOS/SIMOX divider. The fully programmable dividers
described here demonstrate that architectural choices and op-
timization procedures can take standard 0.35 m CMOS to
performance levels comparable to more expensive technolo-
gies, such as bipolar and CMOS/SIMOX processes.
V. CONCLUSION
This paper presented a truly modular and power-scalable
architecture for low-power fully programmable frequency
dividers. The flexibility and reusability properties of the
architecture were demonstrated with the realization of a
family of programmable divider circuits, consisting of the
UHF divider (17 bits), the -band divider (18 bits), and the
reference divider (12 bits). The UHF and reference divider
were implemented by simple removal of divider cells from
the -band circuitry. The implementation of the 2/3 divider
cells was presented, and the power dissipation optimization
procedure was described. To cope with EMC considerations,
the dividers were implemented in CMOS SCL (current mode
logic). The circuits were processed in a standard 0.35- m
bulk CMOS technology, and operate with a nominal supply
voltage of 2.2 V. The power efficiency of the UHF divider
is 0.77 GHz/mW, and of the -band divider, 0.57 GHz/mW.
The measured input sensitivity, including the input amplifiers,
is 10 mVrms for the UHF divider, and 20 mVrms for the
-band divider.
Authorized licensed use limited to: Liang-Hsuan Lu. Downloaded on January 11, 2009 at 22:18 from IEEE Xplore. Restrictions apply.
1045
ACKNOWLEDGMENT
The authors wish to thank G. van Veenendaal, of PS-Sys-
tems Laboratory, Eindhoven, The Netherlands, for evaluation
work done on the programmable dividers. Many thanks go to
D. Kasperkovitz and J. de Haas for the support provided during
the project.
REFERENCES
[1] S. Wu and B. Razavi, “A 900 MHz/1.8 GHz CMOS receiver for
dual-band applications,” IEEE J. Solid-State Circuits, vol. 33, pp.
2178–2185, Dec. 1998.
[2] J. Craninckx and M. Steyaert, “A fully integrated CMOS DCS-1800
frequency synthesizer,” IEEE J. Solid-State Circuits, vol. 33, pp.
2054–2065, Dec. 1998.
[3] Q. Huang et al., “GSM transceiver front-end circuits in 0.25-m
CMOS,” IEEE J. Solid-State Circuits, vol. 34, pp. 292–303, Mar. 1999.
[4] Y. Kado et al., “An ultralow power CMOS/SIMOX programmable
counter LSI,” IEEE J. Solid-State Circuits, vol. 32, pp. 1582–1587,
Oct. 1997.
[5] U. L. Rohde, RF and Microwave Digital Frequency Synthesizers. New
York, NY: Wiley, 1997.
[6] T. Seneff et al., “A sub-1 mA 1.6 GHz silicon bipolar dual modulus
prescaler,” IEEE J. Solid-State Circuits, vol. 29, pp. 1206–1211, Oct.
1994.
[7] J. Craninckx and M. Steyaert, “A 1.75 GHz/3 V dual-modulus di-
vide-by-128/129 prescalar in 0.7 m CMOS,” IEEE J. Solid-State
Circuits, vol. 31, pp. 890–897, July 1996.
[8] F. Piazza and Q. Huang, “A low power CMOS dual modulus prescaler
for frequency synthesizers,” IEICE Trans. Electron., vol. E80-C, pp.
314–319, Feb. 1997.
[9] P. Larsson, “High-speed architecture for a programmable frequency di-
vider and a dual-modulus prescaler,” IEEE J. Solid-State Circuits, vol.
31, pp. 744–748, May 1996.
[10] J. Navarro Soares, Jr. and W. A. M. Van Noije, “A 1.6 GHz dual-mod-
ulus prescaler using the extended true-single-phase-clock CMOS circuit
technique (E-TSPC),” IEEE J. Solid-State Circuits, vol. 34, pp. 97–102,
Jan. 1999.
[11] C. S. Vaucher and D. Kasperkovitz, “A wide-band tuning system for
fully integrated satellite receivers,” IEEE J. Solid-State Circuits, vol. 33,
pp. 987–998, July 1998.
[12] N. H. Sheng et al., “A high-speed multimodulus HBT prescaler for fre-
quency synthesizer applications,” IEEE J. Solid-State Circuits, vol. 26,
pp. 1362–1367, Oct. 1991.
[13] C. S. Vaucher, “An adaptive PLL tuning system architecture combining
high spectral purity and fast settling time,” IEEE J. Solid-State Circuits,
vol. 35, pp. 490–502, Apr. 2000.
[14] C. S. Vaucher and Z. Wang, “A low-power truly modular 1.8 GHz pro-
grammable divider in standard CMOS technology,” in Proc. 25th Eur.
Solid-State Circuits Conf., Sept. 1999, pp. 406–409.
[15] M. Mizuno et al., “A GHz MOS adaptive pipeline technique using MOS
current-mode logic,” IEEE J. Solid-State Circuits, pp. 784–791, June
1996.
[16] A. R. Shahani et al., “Low-power dividerless frequency synthesis using
aperture phase detection,” IEEE J. Solid-State Circuits, vol. 33, pp.
2232–2239, Dec. 1998.