SN54LVTH245A, SN74LVTH245A

3.3-V ABT OCTAL BUS TRANSCEIVERS

WITH 3-STATE OUTPUTS
SCBS130P – MAY 1992 – REVISED APRIL 1999

D State-of-the-Art Advanced BiCMOS SN54LVTH245A . . . J OR W PACKAGE

Technology (ABT) Design for 3.3-V SN74LVTH245A . . . DB, DW, OR PW PACKAGE
(TOP VIEW)
Operation and Low Static-Power
Dissipation
DIR 1 20 VCC
D Support Mixed-Mode Signal Operation (5-V A1 2 19 OE
Input and Output Voltages With 3.3-V VCC) A2 3 18 B1
D Support Unregulated Battery Operation A3 4 17 B2
Down to 2.7 V A4 5 16 B3
D Typical VOLP (Output Ground Bounce) A5 6 15 B4
< 0.8 V at VCC = 3.3 V, TA = 25°C A6 7 14 B5
D Ioff and Power-Up 3-State Support Hot A7 8 13 B6
Insertion A8 9 12 B7
D Bus Hold on Data Inputs Eliminates the
GND 10 11 B8
Need for External Pullup/Pulldown
Resistors SN54LVTH245A . . . FK PACKAGE
D Latch-Up Performance Exceeds 500 mA Per
(TOP VIEW)

VCC
JESD 17

DIR

OE
A2
A1
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V 3 2 1 20 19
Using Machine Model (C = 200 pF, R = 0) A3 4 18 B1

D Package Options Include Plastic

A4
A5
5
6
17
16
B2
B3
Small-Outline (DW), Shrink Small-Outline
A6 7 15 B4
(DB), and Thin Shrink Small-Outline (PW)
A7 8 14 B5
Packages, Ceramic Chip Carriers (FK), 9 10 11 12 13
Ceramic Flat (W) Packages, and Ceramic

A8

B8
B7
B6
GND
(J) DIPs

description
These octal bus transceivers are designed specifically for low-voltage (3.3-V) VCC operation, but with the
capability to provide a TTL interface to a 5-V system environment.
These devices are designed for asynchronous communication between data buses. They transmit data from
the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR)
input. The output-enable (OE) input can be used to disable the devices so the buses are effectively isolated.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
The SN54LVTH245A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVTH245A is characterized for operation from –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Copyright  1999, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments On products compliant to MIL-PRF-38535, all parameters are tested
standard warranty. Production processing does not necessarily include unless otherwise noted. On all other products, production
testing of all parameters. processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

SN54LVTH245A, SN74LVTH245A
3.3-V ABT OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS130P – MAY 1992 – REVISED APRIL 1999

FUNCTION TABLE
INPUTS
OPERATION
OE DIR
L L B data to A bus
L H A data to B bus
H X Isolation

logic symbol†

19
OE G3
1
DIR 3EN1[BA]
3EN2[AB]

2 18
A1 1 B1
2
3 17
A2 B2
4 16
A3 B3
5 15
A4 B4
6 14
A5 B5
7 13
A6 B6
8 12
A7 B7
9 11
A8 B8

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

logic diagram (positive logic)

1
DIR

19
OE

2
A1

18
B1

To Seven Other Channels

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 SN54LVTH245A, SN74LVTH245A
3.3-V ABT OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS130P – MAY 1992 – REVISED APRIL 1999

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Voltage range applied to any output in the high-impedance
or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Voltage range applied to any output in the high state, VO (see Note 1) . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Current into any output in the low state, IO: SN54LVTH245A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74LVTH245A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Current into any output in the high state, IO (see Note 2): SN54LVTH245A . . . . . . . . . . . . . . . . . . . . . . 48 mA
SN74LVTH245A . . . . . . . . . . . . . . . . . . . . . . 64 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance, θJA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51.

recommended operating conditions (see Note 4)

SN54LVTH245A SN74LVTH245A
UNIT
MIN MAX MIN MAX
VCC Supply voltage 2.7 3.6 2.7 3.6 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
VI Input voltage 5.5 5.5 V
IOH High-level output current –24 –32 mA
IOL Low-level output current 48 64 mA
∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
∆t/∆VCC Power-up ramp rate 200 200 µs/V
TA Operating free-air temperature –55 125 –40 85 °C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

SN54LVTH245A, SN74LVTH245A
3.3-V ABT OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS130P – MAY 1992 – REVISED APRIL 1999

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
SN54LVTH245A SN74LVTH245A
PARAMETER TEST CONDITIONS UNIT
MIN TYP† MAX MIN TYP† MAX
VIK VCC = 2.7 V, II = –18 mA –1.2 –1.2 V
VCC = 2.7 V to 3.6 V, IOH = –100 µA VCC–0.2 VCC–0.2
VCC = 2.7 V, IOH = –8 mA 2.4 2.4
VOH V
IOH = –24 mA 2
VCC = 3 V
IOH = –32 mA 2
IOL = 100 µA 0.2 0.2
VCC = 2
2.7
7V
IOL = 24 mA 0.5 0.5
IOL = 16 mA 0.4 0.4
VOL V
IOL = 32 mA 0.5 0.5
VCC = 3 V
IOL = 48 mA 0.55
IOL = 64 mA 0.55
VCC = 3.6 V, VI = VCC or GND ±1 ±1
Control inputs
VCC = 0 or 3.6 V, VI = 5.5 V 10 10
II VI = 5.5 V 20 20 µA
A or B ports‡ VCC = 3.6 V VI = VCC 1 1
VI = 0 –5 –5
Ioff VCC = 0, VI or VO = 0 to 4.5 V ±100 µA
VI = 0.8 V 75 75
VCC = 3 V
VI = 2 V –75 –75
II(hold) A or B ports
orts µA
500
VCC = 3.6 V§, VI = 0 to 3.6 V
–750
VCC = 0 to 1.5 V, VO = 0.5 V to 3 V,
IOZPU ±100∗ ±100 µA
OE = don’t care
VCC = 1.5 V to 0, VO = 0.5 V to 3 V,
IOZPD ±100∗ ±100 µA
OE = don’t care

VCC = 3.6 V, Outputs high 0.19 0.19

ICC IO = 0, Outputs low 5 5 mA
VI = VCC or GND Outputs disabled 0.19 0.19
VCC = 3 V to 3.6 V, One input at VCC – 0.6 V,
∆ICC¶ 0.2 0.2 mA
Other inputs at VCC or GND
Ci VI = 3 V or 0 4 4 pF
Cio VO = 3 V or 0 9 9 pF
∗ On products compliant to MIL-PRF-38535, this parameter is not production tested.
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ Unused terminals are at VCC or GND.
§ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 SN54LVTH245A, SN74LVTH245A
3.3-V ABT OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS130P – MAY 1992 – REVISED APRIL 1999

switching characteristics over recommended operating free-air temperature range, CL = 50 pF

(unless otherwise noted) (see Figure 1)
SN54LVTH245A SN74LVTH245A
FROM TO VCC = 3.3 V VCC = 3.3 V
PARAMETER VCC = 2.7 V VCC = 2.7 V UNIT
(INPUT) (OUTPUT) ± 0.3 V ± 0.3 V
MIN MAX MIN MAX MIN TYP† MAX MIN MAX
tPLH 0.7 3.7 4.2 1.2 2.3 3.5 4
A or B B or A ns
tPHL 0.7 3.7 4.2 1.2 2.1 3.5 4
tPZH 1.2 5.7 7.4 1.3 3.2 5.5 7.1
OE A or B ns
tPZL 1.6 5.7 6.8 1.7 3.4 5.5 6.5
tPHZ 1.8 6.2 6.8 2.2 3.5 5.9 6.5
OE A or B ns
tPLZ 1.8 5.3 5.5 2.2 3.4 5 5.1
† All typical values are at VCC = 3.3 V, TA = 25°C.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

SN54LVTH245A, SN74LVTH245A
3.3-V ABT OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS130P – MAY 1992 – REVISED APRIL 1999

PARAMETER MEASUREMENT INFORMATION

6V
TEST S1
From Output 500 Ω S1 Open
tPLH/tPHL Open
Under Test GND tPLZ/tPZL 6V
CL = 50 pF tPHZ/tPZH GND
(see Note A) 500 Ω

2.7 V
LOAD CIRCUIT Timing Input 1.5 V
0V
tw
tsu th
2.7 V
2.7 V
Input 1.5 V 1.5 V Data Input 1.5 V 1.5 V
0V 0V

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

PULSE DURATION SETUP AND HOLD TIMES

2.7 V 2.7 V
Output 1.5 V 1.5 V
Input 1.5 V 1.5 V
Control
0V 0V

tPLH tPHL tPZL tPLZ

VOH Output 3V
1.5 V 1.5 V Waveform 1 1.5 V
Output VOL + 0.3 V
S1 at 6 V VOL
VOL
(see Note B)
tPHL tPLH tPZH tPHZ
Output VOH
VOH
Waveform 2 VOH – 0.3 V
1.5 V 1.5 V 1.5 V
Output S1 at GND
VOL ≈0V
(see Note B)
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright  1999, Texas Instruments Incorporated

This datasheet has been downloaded from:

www.DatasheetCatalog.com

Datasheets for electronic components.