Robert Rhodes

5/9/2010
Lab report 4

Description:
This lab served to introduce synchronous logic. To this end, I designed a 16 bit counter and then implemented it on the fpga board. The counter used two of the
push buttons for input: one button caused the counter to make a single increment per push while the second button caused continuous incrementing . After the
highest 16 bit number appeared as output on the 4 seven segment displays, an led indicated this terminal count. The device could then be reset. The major tasks
involved were the construction of the counter with control logic, a circuit for synchronizing input with the clock, and once again display logic. I began with the
counter and associated logic.
COUNTER
I began with the truth table for a 4 bit counter. The table is more like a state transition table as it displays the number in the counting sequence given the current
number, the clock value, and the user input to the counter module. I used 4 D flip flops and necessary logic to implement each of the 4 bit counters that I later cascaded
to create the 16 bit counter. To finish the 4 bit counter, I used simple logic that enabled the more significant bits to become 1s only after preceding bits were
simultaneously 1s. This was what proved necessary to implement the 4 bit counter and a similar scheme applied to the count enables of the cascaded 4 bit counters
lead to the 16 bit counter’s success.
If the user pushed btn 0, the device continuously counted as the logic was created to force the counter’s enable high under this condition. Otherwise, if the user pressed
btn 1, the device counted a single number and then waited for both the next high clock pulse and button push. The case for input from btn 1 was handled in the edge
detector module which is described in the next part.
EDGEDETECTOR
This module allowed the counter to define separate button pushes. It also ensured that each button push ( an output of 1) would be transferred to the count enable
synchronously. To do this, the circuit basically produced a 1 output for the push button input sequence 0,0,1.The module contained logic to produce a 1 for a
combination of a button push and high clock edge. Also, a D flip flop served as the memory element.
DISPLAY
Unlike the last lab, this lab made use of a single selector which cycled through the 4 bit vectors that made up the displayed 16 bit number. The selector displayed a 4
bit number on the active 7 segment display similarly to the last lab however in order to display 4 numbers, a new element called a ring counter had to be introduced.
The ring counter has 4 outputs only 1 of which may be 1 for a given clock cycle. Since the anodes are active low, I inverted the ring counter’s output so that only 1 of
the module’s pins output a logic low. The single 16 to 4 decoder ( made with muxes) took a 16 bit bus and a 4 bit bus from the ring counter as input. As the schematic
for the decoder shows, the output of the ring counter is fed to gate logic attached to the selector lines of each of the decoder’s 4 internal 4 to 1 muxes. Based on the
ring counter output, either the high, mid, second lowest ,or lowest bits of the 16 bit number will be fed to the 4 to 7 decoder. The 4 to 7 decoder is the same as it was in
previous labs.

As a final addition to the project, I added a global reset so that the device could be reset as mentioned earlier.