Salendra.Govindarajulu et al.

/ (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES

Vol No. 5, Issue No. 2, 319 - 331

Energy-Efficient Domino VLSI Circuits and their

Performance with PVT Variations in DSM
Technology
Salendra.Govindarajulu1, Dr.T.Jayachandra Prasad2, Chimakurthy.Sreelakshmi3, C.H.Balaji4,
1
Associate Professor, ECE, RGMCET, Nandyal, JNTU, A.P.State, India, Email: rajulusg06@yahoo.co.in
2
Principal, RGMCET, Nandyal, JNTU, A.P.State, India, Email: jp.talari@gmail.com
3
PG Student, ECE, RGMCET, Nandyal, JNTU, A.P.State, India, Email: sreelakshmi0718@gmail.com
4
UG Student, KLU, Vijayawada.

Abstract— Compared to static CMOS logic, dynamic logic offers
good performance. Wide fan-in dynamic logic such as domino is
often used in performance critical paths, to achieve high speeds
where static CMOS fails to meet performance objectives.
However, domino gates typically consume higher dynamic
II. DUAL-RAIL DOMINO FOOTLESS CIRCUIT WITH
SELF- TIMED PRECHARGE SCHEME (DRDFSTP):
Conventional domino circuits:
In this section, several conventional domino circuits with

T
switching and leakage power and display weaker noise immunity
as compared to static CMOS gates. Keeping in view of the above their own clocking schemes are briefly reviewed.
stated problems in previous existing designs, novel energy-
efficient domino circuit techniques are proposed. The proposed A. Dynamic DCVSL Footed Circuit (DDCVSLF):
circuit techniques reduced the dynamic switching power
consumption; short-circuit current overhead, idle mode leakage Fig.1 shows AND/NAND dynamic DCVSL Footed
power consumption and enhanced evaluation speed and noise circuit. One of the disadvantages of this kind of domino
ES
immunity in domino logic circuits. Also regarding performance,
these techniques minimize the power-delay product (PDP) as
compared to the standard full-swing circuits in deep sub micron
CMOS technology.
Also the effect of the Process, Voltage and Temperature
circuit is that the existence foot transistor slows the gates
somewhat, as it presents an extra series resistance. Moreover,
simultaneous precharge may cause an unacceptable IR-drop
noise.
(PVT) variations on the performance of the CMOS Domino
circuits with various techniques are analyzed.

Key words: Dynamic, Domino, Noise Margin, Deep submicron

technology (DSM), High speed, Power consumption, Power delay
product (PDP), PVT variations, Reduced dynamic swing.

I. INTRODUCTION
A
Dynamic domino logic circuits are widely used in modern
digital VLSI circuits. These dynamic circuits are often
Fig.1. Dynamic DCVSL AND/NAND Footed gate
favoured in high performance designs because of the speed
advantage offered over static CMOS logic circuits. The main
B. Dynamic DCVSL Footless Circuit (DDCVSLFL):
drawbacks of dynamic logic are a lack of design automation,
a decreased tolerance to noise and increased power
IJ

dissipation. However, domino gates typically consume higher Fig.2 shows AND/NAND dynamic DCVSL Footless
dynamic switching and leakage power and display weaker circuit. Two benefits come from the usage of footless domino
gates: improved pull-down speed and reduced precharge
noise immunity as compared to static CMOS logic circuits. In
signal load. Main disadvantage is simultaneous precharge will
this paper novel energy-efficient domino circuit techniques
are proposed. cause short-circuit current.
This paper is organized as follows. In section II, Dual-rail
domino circuit with self-timed precharge scheme is proposed.
The Reduced dynamic swing domino logic is presented in
section III. Section IV describes performance evaluation
results of energy-efficient dynamic node low voltage swing
with dual supply, dual grounds and dual-Vt domino logic.
Section V describes the effect of PVT variations on domino
logic presented in section II, III, IV. Then conclusions are Fig. 2. Dynamic DCVSL AND/NAND Footless gate
presented in section VI.

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Vol No. 5, Issue No. 2, 319 - 331

C. Delayed-Reset Domino Circuit (DRDC):
Fig.3 illustrates the delayed-reset domino AND/NAND
circuit [3]. However, the use of delay elements, together with
the need of both footed and footless cell libraries tends to
increase design complexity.
self-timed precharge scheme. The self-timed precharge control
logic consists of static CMOS inverter whose source of NMOS
transistors are tied to input signals, which generate sub-
precharge signals (PC1-PC4) from precharge signal P in cases
of the corresponding input signals are zero. The PMOS
precharge tree above the pull down network (PDN) is used for
precharging the corresponding gate.

Fig:3. The delayed-reset domino AND/NAND circuit Fig:5. Dual-rail footless domino AND/NAND gate with self-

T
timed precharge scheme.
D. Dual-Rail Data-Driven Dynamic Logic (D4L):
Simulation results:
D4L circuit uses input signals instead of precharge signal
for correct precharge and evaluation sequencing [5]. In this work, we have implemented a Dynamic DCVSL
Correspondingly, clock-buffering and clock-distribution circuit, Dual-Rail Data-Driven Dynamic Logic and a proposed
ES
problems can be eliminated. Furthermore, the foot transistor
can be eliminated without causing a short-circuit problem. A
D4L two-input AND/NAND gate is shown in Fig.4.
circuit Dual-Rail Domino Footless Circuit with Self-Timed
Precharge Scheme. The results of simulation are shown in the
below TABLES1-3.

Table1. AND/NAND GATE

Technique Power Critical PDP Area

(µw) Delay (10-15 w- (µ.sqm)
(ns) s)
A
DDCVSLF 7.6 0.088 0.6688 69.62
DDCVSLF 152 0.025 3.8 65.41
L
Fig.4. Dual-Rail Data-Driven Dynamic AND/NAND Logic ( DRDC 205 0.137 28.085 252.9
D4L)

Dual-Rail Domino Footless Circuit with Self- Timed D4L 72.555 0.111 8.053606 93.3
IJ

Precharge Scheme (DRDFSTP):

DRDFSTP 7.676 0.042 0.322392 177.6
The presence of the foot transistor in the conventional
dynamic DCVSL circuit shows the gate somewhat, as it
presents an extra series resistance. To safely remove the
transistor, two constraints must be met: (1) gate changes to
evaluation phase before valid input come; (2) gate changes to
precharge phase only after inputs change to zero. We propose
a footless duail-rail domino circuit with self-timed precharge
scheme to realize a high performance footless domino circuit
while meeting the constraints mentioned above. It is expected
that the peak of precharge current could be reduced due to the
self-timed precharge scheme. Fig. 9 shows the AND/NAND
gate of the proposed footless dual-rail domino circuit with

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Vol No. 5, Issue No. 2, 319 - 331

B. Reduced–Swing Domino with Single supply (RSSLS):

Table2. OR/NOR GATE
The RSDLS circuit shown above is simplified by replacing
Technique Power Critical PDP Area the extra supply voltages with transistors providing the desired
(µw) Delay (10-15 w- (µ.sqm) threshold voltage drops. The configuration is shown in fig.7.
(ns) s)
DDCVSLF 7.58 0.087 0.65946 74.82
DDCVSLF 145 0.090 13.05 66.59
L
DRDC 220 0.403 88.66 290

D4L 10.163 0.112 1.138256 78.48

Fig.7.Reduced – Swing Domino with Single supply
DRDFSTP 7.583 0.042 0.318486 130.18
C. Reduced Swing Mirror Domino (RSMRD):
This is one of the alternative approaches for having
Table3. XOR/XNOR GATE reduced swing, which is shown in fig.8. This is an
arrangement in which the precharge and footer transistors are

T
exchanged with an NMOS and PMOS transistor respectively.
Technique Power Critical PDP Area
(µw) Delay (10-15 w- (µ.sqm)
(ns) s)
DDCVSLF 11.7 0.032 0.3744 99.2
DDCVSLF 99.023 0.032 3.1687 92.17
L
DRDC

D4L
231

16.802
0.091

0.029
21.021

0.487258
ES 391.9

100.5
Fig.8.Reduced Swing with Mirror Domino

This arrangement dictates that the precharge and evaluate

DRDFSTP 11.642 0.04 0.46568 200.13
cycles be reversed with regard to clock. That is, clock begins
high corresponding to precharge and clock goes low
corresponding to the evaluate cycle. Given this arrangement,
III. REDUCED DYNAMIC SWING DOMINO (RDS- the voltage swing of the internal dynamic node is limited by
DOMINO): the transistor thresholds. The supply voltage and the
input/output signals all remain unmodified.
A. Reduced–Swing Domino with Dual supply (RSDLS):
A
Simulation results:
The first circuit configuration proposed to reduce the The benchmark circuits using the stated four techniques are
dynamic node voltage swing is obtained by simply altering the implemented. The figures of merits used to compare these
appropriate supply voltages of the standard domino gates as techniques are power consumption, propagation delay and
shown in fig.6. power delay product (PDP). The benchmark circuits
implemented are OR2 gate, AND2 gate, XOR2 gate, 16-bit
Full adder, 16-bit Comparator , D-flip flop and 4-bit LFSR
IJ

(Linear Feedback Shift Register).

Fig.6. Reduced–Swing Domino with Dual Supply

This circuit is here after referred to as a reduced–swing

(RSDLS) domino gate with dull supply.

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Vol No. 5, Issue No. 2, 319 - 331

Table8. Optimum values of different techniques for 16-bit

Table4. Optimum values of different techniques of 2-input OR comparator
Gate Power Delay
Power Power Product
Techniques Power(µ Delay
Watts) Delay(ns) Product (m Delay (*10 -12 Watt-
(*10-15 Techniques Watts) (ns) Sec)
Watt-Sec)
RSDLS 65nm 0.007 0.032 0.0000224 RSDLS 65nm 1.053 0.069 0.072657
RSSLS 65nm 17.094 0.023 0.393162 RSSLS 65nm 1.07 0.058 0.06206
RSMRD 65nm 0.0322 0.016 0.0005152
Std- RSMRD 65nm 6.901 0.041 0.282941
Domino 65nm 0.433 0.054 0.023382 STD-
DOMINO 65nm 0.833 0.033 0.027489
Table5. Optimum values of different techniques of 2-input
AND Gate
Power Delay
Product Table9. Optimum values of different techniques for D-Flip

T
Power(µ Delay (*10-15 Watt- flop
Techniques watts) (ns) Sec)
RSDLS 65nm 21.635 0.026 0.56251
RSSLS 65nm 32.102 0.017 0.545734 Power
RSMRD 65nm 0.355 0.044 0.01562 Delay
Std- Power Product
Domino 65nm 0.506 0.102 0.051612 (m (*10-12
Techniques Watts) Delay(ns) Watt-Sec)
ES
Table6. Optimum values of different techniques of 2-input
XOR Gate
RSDLS

RSSLS
65nm

65nm
0.01925

0.115
0.118

0.083
0.0022715

0.009545

Power RSMRD 65nm 0.118 0.075 0.00885

Delay STD-
Power Product DOMINO 65nm 0.05964 0.270 0.0161028
(µ (*10-15
TECHNIQUES Watts) Delay(ns) Watt-Sec)
RSDLS 65nm 22.881 0.046 1.052526 Table10. Optimum values of different techniques for 4-bit
RSSLS 65nm 23.002 0.067 1.541134 LFSR
RSMRD 65nm 1.592 0.067 0.106664
A
Std- Power Delay
Domino 65nm 1.711 0.102 0.174522 Power Product
(m Delay (*10-12Watt-
Techniques Watts) (ns) Sec)
Table7. Optimum values of different techniques of 16-bit 0.01
RSDLS 65nm 0.0244 0.780 9032
adder 0.18
IJ

RSSLS 65nm 0.683 0.275 7825

Power
Delay 0.08
Power Product RSMRD 65nm 0.293 0.299 7607
(µ (*10-15 STD- 3.13
Techniques Watts) Delay(ns) Watt-Sec) DOMINO 65nm 1.455 2.156 698
RSDLS 65nm 0.15 0.025 0.00375
RSSLS 65nm 0.649 0.073 0.009735
RSMRD 65nm 1.909 1.682 0.03818
Std-
Domino 65nm 0.586 24.825 0.015236

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Vol No. 5, Issue No. 2, 319 - 331

IV. DYNAMIC NODE LOW VOLTAGE SWING DOMINO B.Single Vt domino logic circuit with dual power
LOGIC CIRCUITS WITH DUAL POWERS, GROUNDS supply, dual ground: (DUAL SUPPLY)
AND DUAL VT:
The single Vt domino logic circuit with dual power supply,
This section discusses several dual threshold voltage dual ground is shown in Fig.11.
domino circuit design techniques to reduce the power
dissipation of domino logic while simultaneously improving
noise immunity. The benefits are achieved by limiting the
voltage swing of the internal dynamic node in a typical
domino gate. This dynamic storage node is the node connected
to the input of the output inverter of a domino gate as shown
in fig.9.

T
Fig.11. The dynamic node low voltage swing domino circuit
technique with dual power supplies and ground voltages
VDDL<VDD , VgndH>Vgnd

C. Dual Vt Domino Logic circuit With Dual power

ES
Fig.9. Dynamic node low voltage swing domino logic circuit
The above circuit is used to reduce the voltage swing at the
dynamic node of a domino gate. A complete analysis of the
effects of the reduced swing at the dynamic node on both noise
tolerance and propagation delay is presented with respect to
specific circuit configurations below.
A. Single Vt domino logic circuit with keeper: (NORMAL)
supply,Dual Ground(N1 High Threshold): (DUAL N1)
The dual Vt domino logic circuit with dual power supply,
dual ground (N1 high threshold) is shown in Fig.12. The
NMOS transistor in the output inverter has high Vt. Short
circuit current is therefore reduced only in the evaluation
phase if the inputs are high. Hence evaluation speed of the
circuit is higher as compared to N1, P1 high threshold
technique.

The single Vt domino logic circuit with keeper is shown in

A
Fig.10. Keeper circuit is used to maintain the voltage level at
dynamic node which also increases the noise immunity. The
voltage at the dynamic node should be VDD but gets
diminished due to several reasons, by using the keeper in the
above circuit with P2, N2 transistors pair forming inverter
turns ON Pk transistor which pulls dynamic node to VDD.
IJ

Fig.12. The dynamic node low voltage swing domino circuit

technique with dual power supplies and ground voltages
VDDL<VDD , VgndH>Vgnd and with N1 high threshold

D. Dual Vt domino logic circuit with dual power supply,

dual ground (N2 ground):

The dual Vt domino logic circuit with dual power supply,

Fig.10. Domino logic circuit with keeper. dual ground (N1 high threshold) is shown in Fig.13. N2 FET

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Vol No. 5, Issue No. 2, 319 - 331

is grounded; these modifications are made to the basic circuit modifications are made to the basic circuit in order to analyze
in order to analyze the variations in the parameters like power, the variations in the parameters like power, delay, area, power
delay, area, power delay product (PDP) and to find the delay product (PDP) and to find the efficient technique.
efficient technique.

Fig.15. dynamic node low voltage swing domino circuit

technique with dual power supplies and ground voltages
VDDL<VDD , VgndH>Vgnd and with N1, P2, Pk high thresholds
Fig.13. The dynamic node low voltage swing domino circuit

T
technique with dual power supplies and ground voltages
VDDL<VDD , VgndH>Vgnd and with N2 Ground G. Dual Vt domino logic circuit with dual power supply,
dual ground (P11,PK,P1 high threshold):
E. Dual Vt domino logic circuit with dual power supply,
dual ground (N1, P1 high threshold): (DUAL N1,P1) The dual Vt domino logic circuit with dual power supply,
dual ground (P11, PK, P1 High threshold) is shown in fig.16.
ES
The dual Vt domino logic circuit with dual power supply,
dual ground (N1, P1 High Threshold) is shown in Fig.14. The
short circuit current produced by the output inverter is
suppressed during both the precharge and evaluation phases of
P11, Pk, P2 FETs threshold voltages are increased, these
modifications are made to the basic circuit in order to analyze
the variations in the parameters like power, delay, area, power
delay product (PDP) and to find the efficient technique.
operation, since the NMOS and PMOS transistors in the
output inverter have high Vt. However, evaluation speed is
also degraded due to the weaker pull-up strength of high Vt
PMOS transistor.
A
IJ

Fig.16. dynamic node low voltage swing domino circuit

Fig.14. The dynamic node low voltage swing domino circuit
technique with dual power supplies and ground voltages
VDDL<VDD , VgndH>Vgnd and with N1, P1 high thresholds
F. Dual Vt domino logic circuit with dual power supply,
dual ground (Pk, P2, N1 high threshold):
The dual Vt domino logic circuit with dual power supply,
dual ground (Pk, P2, N1 high threshold) is shown in Fig15.
P2, N1 FETs threshold voltages are increased, these
technique with dual power supplies and ground voltages
VDDL<VDD , VgndH>Vgnd and with Pk, P1, P11 High thresholds
Simulation results:
In this work, the benchmark circuits using the stated seven
techniques are implemented. The benchmark circuits
implemented are OR2, AND2, XOR2, 16-bit Full Adder, 16-
bit Comparator, D-Latch, 4-bit LFSR. Here the results are
given for 16-bit Full Adder, 16-bit Comparator, D-Latch, 4-bit
LFSR.

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Vol No. 5, Issue No. 2, 319 - 331

Table13. Optimum values of different techniques for 4-bit

Table11. Optimum values of different techniques for 16-bit
adder LFSR
PDP(10-12 Area(mic
S.N TECHNIQU POWER(m DELAY( w-s) ro PDP(10-
12
w-s) Area(mic
o ES w) ns) sq.meter) TECHNIQU POWER(m DELAY( ro
1405.7589 S.NO ES w) ns) sq.meter)
1 NORMAL 11.062 127.081 6 12809.5
N2 1087.2308 31.1778
2 GROUND 10.958 99.218 44 12826.9 1 NORMAL 4.587 6.797 39 2255.05
DUAL
POWER 1147.3832 N2 24.5371
3 SUPPLY 11.402 100.63 6 13782 2 GROUND 2.976 8.245 2 2493.05
DUAL
4 PK ,P11, P1 12.088 61.160 739.30208 12159.48 POWER 21.4247
3 SUPPLY 2.882 7.434 88 2472.36
5 PK ,P2, N1 20.15 42.118 848.6777 15409.67
16.7428
DUAL P1, 2210.8500 4 PK ,P11, P1 3.08 5.436 8 2468.4

T
6 N1 21.88 100.633 4 15269
931.34221 15.9689
7 DUAL N1 10.245 90.907 5 10371 5 PK ,P2, N1 2.929 5.452 08 2482.7

DUAL P1, 15.6266

6 N1 2.889 5.409 01 2463.3

16.0390

comparator
ES
Table12. Optimum values of different techniques for 16-bit

PDP(10-12 Area(mic
7 DUAL N1 2.968 5.404 72

Table 14. Optimum values of different techniques for D-Latch

2483.34

PDP(10 Area(mic
S.N TECHNIQU POWER(m DELAY( w-s) ro S.N TECHNIQU POWER(m DELAY(n -12
w-s) ro
O ES w) ns) sq.meter) O ES w) s) sq.meter)
0.09037
1 NORMAL 0.158 0.572 6 215.56
1 NORMAL 10.475 104.86 1098.4085 18914
N2 0.07530
N2 1287.3798
2 GROUND 0.163 0.467 6 254.92
2 GROUND 8.204 156.921 84 19316
DUAL
A
DUAL
POWER POWER
3 SUPPLY 7.795 209.5 1633.0525 18329.6 3 SUPPLY 0.22 0.535 0.1177 261.41
1271.1885
0.06506
4 PK ,P11, P1 8.457 150.312 8 18369.4
4 PK ,P11, P1 0.169 0.385 5 258.69
1265.0123
0.06472
5 PK ,P2, N1 8.506 148.72 2 20240.6
IJ

5 PK ,P2, N1 0.169 0.383 7 262.885

DUAL P1, 105.00109
DUAL P1, 0.06219
6 N1 10.432 119.209 31 18453
6 N1 0.169 0.368 2 256.11
1279.5316
0.06050
7 DUAL N1 8.56 149.478 8 18840
7 DUAL N1 0.169 0.358 2 262.59

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Vol No. 5, Issue No. 2, 319 - 331

(Oxide layer thickness) and UO (carrier mobility). The

V. PROCESS, VOLTAGE AND TEMPERATURE
VARIATIONS (PVT) ON THE PERFORMANCE OF
DOMINO LOGIC:
- The PVT variances

The effect of PVT variations on the domino logic circuit on the domino logic in sections II, III, IV are given in below

techniques which are explained in sections II, III, IV are Tables15-23.

studied and analyzed in this section. The process variations

considered are VTHO (Threshold voltage at zero bias), TOXE

PVT Variations for section II:

Table15.PROCESS VARIATIONS (V AND T CONSTANT)

T
BENCHMARK AND/NAND OR/NOR XOR/XNOR
CIRCUITS

VTHO= VTHO= VTHO= VTHO= VTHO= VTHO= VTHO= VTHO= VTHO=

0.3 0.35 0.4 0.3 0.35 0.4 0.3 0.35 0.4
TOXE= TOXE= TOXE= TOXE= TOXE= TOXE= TOXE= TOXE= TOXE=
0.7
UO=0.0
30
ES 1.1
UO=0.0
55
1.6
U0=0.08
0.7
UO=0.0
30
1.1
UO=0.0
55
1.6
U0=0.08
0.7
UO=0.0
30
1.1
UO=0.0
55
1.6
U0=0.08

Dynamic 7.520 7.6 7.623 7.565 7.58 7.45 11.330 11.7 11.23
DCVSL POWER
Footed DISSIPATIO
N
(µW)
ION 0.120 0.250 0.358 0.120 0.250 0.358 0.120 0.250 0.358
(ma)
A
IOFF 2 0 0 2 0 0 2 0 0
(na)

Dynamic 100 152 153 102 145 161 98.427 99.023 99.400
DCVSL POWER
Footless DISSIPATIO
IJ

N
(µW)
ION 0.120 0.250 0.358 0.120 0.250 0.358 0.120 0.250 0.358
(ma)

IOFF 2 0 0 2 0 0 2 0 0
(na)

Delay Reset 201.872 205 204.347 94.254 220 221.392 230.013 231 231.925
Domino POWER
Circuit DISSIPATIO
N
(µW)
ION 0.051 0.107 0.153 0.051 0.107 0.105 0.051 0.107 0.105
(ma)

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IOFF 1 0 0 1 0 0 1 0 0
(na)

Duail-Rail 48.316 72.555 85.268 8.846 10.163 10.475 13.914 16.802 13.85
Data Driven POWER
Dynamic DISSIPATIO
Logic N
(µW)
ION 0.120 0.250 0.358 0.120 0.250 0.358 0.12 0.250 0.358
(ma)

IOFF 2 0 0 2 0 0 2 0 0
(na)

Foot Less 7.446 7.676 7.765 7.400 7.583 7.773 11.61 11.642 10.007
Duail-Rail POWER
Domino DISSIPATIO
Circuit with N
Self Timed (µW)
Precharge ION 0.120 0.205 0.358 0.120 0.205 0.358 0.120 0.250 0.247
Scheme (ma)
Logic

T
IOFF 2 0 0 2 0 0 2 0 0
(na)

BENCHMARK
CIRCUITS
ES
Table16.VOLTAGE VARIATIONS (P AND T CONSTANT)
AND/NAND OR/NOR XOR/XNOR

VDD=0.7 VDD=0. VDD=1 VDD=0. VDD=0. VDD=1 VDD=0. VDD=0. VDD=1

8 7 8 7 8
A
Dynami 7.152 7.153 7.6 7.141 7.524 7.58 9.345 11.809 11.7
c POWER
DCVS DISSIPATION(µ
L W)
Footed ION(ma) 0.131 0.171 0.250 0.131 0.171 0.250 0.131 0.171 0.250
IJ

IOFF(na) 0 0 0 0 0 0 0 0 0

Dynami 100.714 101.621 152 102.185 145.317 145 98.264 99.821 99.023
c POWER
DCVS DISSIPATION(µ
L W)
Footles ION(ma) 0.131 0.171 0.250 0.131 0.171 0.250 0.131 0.171 0.250
s

IOFF(na) 0 0 0 0 0 0 0 0 0

Delay 67.053 102 205 94.217 94.712 220 220.013 230.983 231
Reset POWER
Domin DISSIPATION(µ
o W)

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Vol No. 5, Issue No. 2, 319 - 331

Circuit ION(ma) 0.131 0.171 0.107 0.131 0.171 0.107 0.131 0.171 0.107

IOFF(na) 0 0 0 0 0 0 0 0 0

Duail- 54.187 72.868 72.555 9.127 9.217 10.163 14.717 16.504 16.802
Rail POWER
Data DISSIPATION(µ
Driven W)
Dynami ION(ma) 0.131 0.171 0.250 0.131 0.171 0.250 0.131 0.171 0.250
c Logic

IOFF(na) 0 0 0 0 0 0 0 0 0

Foot 7.885 7.278 7.676 7.317 7.155 7.583 11.521 11.504 11.642
Less POWER
Duail- DISSIPATION(µ
Rail W)
Domin ION(ma) 0.131 0.171 0.250 0.131 0.171 0.250 0.131 0.171 0.250
o
Circuit
with IOFF(na) 0 0 0 0 0 0 0 0 0
Self

T
Timed
Prechar
ge
Scheme
Logic

BENCHMARK
CIRCUITS
ES
Table17.TEMPERATURE VARATIONS (P AND V CONSTANT)
AND/NAND OR/NOR XOR/XNOR

-73 27 127 -73 27 127 -73 27 127

A
Dynamic 7.503 7.6 7.768 7.425 7.58 8.025 11.369 11.7 11.691
DCVSL POWER
Footed DISSIPATION(µ
W)
ION(ma) 0.445 0.250 0.163 0.445 0.250 0.163 0.445 0.250 0.163
IJ

IOFF(na) 0 0 27 0 0 27 0 0 27

Dynamic 246 152 108 247 145 112 169 99.023 77.078
DCVSL POWER
Footless DISSIPATION(µ
W)
ION(ma) 0.445 0.250 0.163 0.445 0.250 0.163 0.445 0.250 0.163

IOFF(na) 0 0 27 0 0 27 0 0 27

Delay 208.507 205 217.451 162 220 72.266 116 231 248.93
Reset POWER 7
Domino DISSIPATION(µ
Circuit W)
ION(ma) 0.190 0.107 0.069 0.190 0.107 0.069 0.107 0.107 0.069

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Salendra.Govindarajulu et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES
Vol No. 5, Issue No. 2, 319 - 331

IOFF(na) 0 0 11 0 0 11 0 0 11

Duail-Rail 94.835 72.555 59.951 4.072 10.163 11.788 5.767 16.802 22.507
Data POWER
Driven DISSIPATION(µ
Dynamic W)
Logic ION(ma) 0.445 0.250 0.163 0.445 0.250 0.163 0.445 0.250 0.163

IOFF(na) 0 0 27 0 0 27 0 0 27

Foot Less 7.555 7.676 8.355 7.408 7.583 8.358 9.024 11.642 13.708
Duail-Rail POWER
Domino DISSIPATION(µ
Circuit W)
with Self ION(ma) 0.445 0.250 0.163 0.445 0.250 0.163 0.445 0.250 0.163
Timed
Precharge
Scheme IOFF(na) 0 0 27 0 0 27 0 0 27
Logic

T
PVT Variations for section III:

Table18.PROCESS VARIATIONS (V AND T CONSTANT)

BENCHMARKCIRCUI
TS
AND2
ES OR2 XOR2 D-LATCH 4-BITLFSR

VTHO VTHO VTHO VTHO VTHO=0. VTHO=0. VTHO= VTHO VTHO= VTHO=
=0.3 =0.4 =0.3 =0.4 3 4 0.3 =0.4 0.3 0.4
TOXE TOXE= TOXE= TOXE= TOXE=0.7 TOXE=1. TOXE=0 TOXE TOXE= TOXE=
=0.7 1.6 0.7 1.6 UO=0.030 6 .7 =1.6 0.7 1.6
UO=0. U0=0.8 UO=0. U0=0.8 U0=0.8 UO=0.0 U0=0.8 UO=0.0 U0=0.8
030 030 30 30
A
STD 6.238 18.390 15.099 0.846 11.264 31.786 31.281 89.351 157 451
DOMINO POWER
DISSIPAT
ION(µW)
ION(ma) 0.120 0.358 0.051 0.153 0.120 0.358 0.051 0.183 0.051 0.153
IJ

IOFF(na) 2 0 1 0 2 0 1 0 1 0

RSSLS 11.958 17.044 11.325 15.834 15.910 22.471 54.203 76.475 264 389
POWER
DISSIPAT
ION(µW)
ION(ma) 0.051 0.139 0.120 0.358 0.51 0.153 0.051 0.139 0.051 0.153

IOFF(na) 1 0 2 0 1 0 0 0 1 0

RSDLS 7.90 3.604 0.004 0.004 29.521 4.719 37.451 34.612 778 393
POWER
DISSIPAT
ION(µW)
ION(ma) 0.449 0.438 0.304 0.280 2.794 0.438 7.012 0.449 2.794 7.012

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Salendra.Govindarajulu et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES
Vol No. 5, Issue No. 2, 319 - 331

IOFF(na) 6 1 2 0 37 1 9 6 37 9

RSMRD 8.109 13.437 0.234 0.227 7.254 12.033 30.259 49.151 284 0.591
POWER
DISSIPAT
ION(µW)
ION(ma) 0.120 0.358 0.120 0.358 0.12 0.358 0.120 0.358 0.120 0.358

IOFF(na) 2 0 2 0 2 0 2 0 2 0

Table19.VOLTAGE VARIATIONS (P AND T CONSTANT):

BENCHMARKCIRCUITS AND2 OR2 XOR2 D-LATCH 4-BITLFSR

VDD=0. VDD=0. VDD=0 VDD=0. VDD=0. VDD=0. VDD=0. VDD=0. VDD=0. VDD=0.
7 8 .7 8 7 8 7 8 7 8

T
STD 11.878 12.263 0.558 26.48 15.438 18.255 38.655 47.105 361 348
DOMINO POWER
DISSIPATION(
µW)
ION(ma)

IOFF(na)
0.250

0
ES
0.250

0
0.250

0
0.107

0
0.250

0
0.250

0
0.107

0
0.107

0
0.107

0
0.107

2.598 6.081 6.824 11.221 0.7 6.97 8.108 26.114 41.306 125
RSSLS POWER
DISSIPATION(
µW)
ION(ma) 0.107 0.107 0.107 0.107 0.958 0.107 0.107 0.107 1.337 0.107

IOFF(na) 0 0 0 0 0 0 0 0 0 0
A
RSDLS 1.464 2.431 0.003 0.003 1.167 4.329 5.743 14.256 54.152 156
POWER
DISSIPATION(
µW)
ION(ma) 1.337 1.337 0.446 0.446 1.337 1.337 1.337 1.337 1.337 1.337

IOFF(na) 0 0 0 0 0 0 0 0 0 0
IJ

RSMRD
0.171 0.375 0.152 0.176 0.737 0.889 0.942 2.410 2,737
POWER 0.788
DISSIPATION(
µW)
ION(ma) 0.120 0.120 0.594 0.594 0.594 0.594

IOFF(na) 2 2 0 0 0 0

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Salendra.Govindarajulu et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES
Vol No. 5, Issue No. 2, 319 - 331

Table20.TEMPERATURE VARATIONS (P AND V CONSTANT)

BENCHMARKCIRCUITS AND2 OR2 XOR2 D-LATCH 4-BITLFSR

127 -73 127 -73 127 -73 127 -73 127 -73

STD DOMINO 8.550 54.746 20.057 138 16.108 92.667 365 112 184 564
POWER 2
DISSIPATION

T
(µW)
ION(µA) 0.163 1.193 0.069 0.530 0.069 1.193 0.655 0.190 0.65 0.190
5

IOFF(nA) 27 0 11 0 11 0 0 0 0 0

RSSLS 10.166 17.435 9.406 18.880 18.206 6.690 58.01 17.873 299 114
POWER 8
DISSIPATION(µW)
ION
(µA)
IOFF(nA)
0.266

3762
ES 0.586

0
0.266

3762
0.586

0
0.266

3762
0.586

0
0.266

3762
0.586

0
0.586

RSDLS 14.136 0.128 0.004 0.004 30.618 0.714 16.39 1.782 24.4 267
POWER 7 20
DISSIPATION
(µW)
ION 0.234 0.320 0.169 0.184 0.234 0.320 1.470 1.193 1.19 1.474
(µA) 3
IOFF 196 0 54 0 186 0 0 0 0 0
A
RSMRD POWER 9.715 12.585 0.302 0.233 7.392 13.922 28.35 63.166 270 504
DISSIPATION 2
(µW)
ION 0.266 0.586 0.266 0.586 0.266 0.586 0.266 0.586 0.26 0.586
(µA) 6
IOFF(nA) 3762 0 3762 0 3762 0 3762 0 376 0
IJ

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Salendra.Govindarajulu et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES
Vol No. 5, Issue No. 2, 319 - 331

PVT Variations for section III:

Table21.PROCESS VARIATIONS (V AND T CONSTANT):

BENCHMARKCIRCUIT AND2 OR2 XOR2 D-LATCH 4-BITLFSR
S

VTHO VTHO VTHO VTHO VTHO=0.3 VTHO=0. VTHO= VTHO VTHO= VTHO=
=0.3 =0.4 =0.3 =0.4 TOXE=0.7 4 0.3 =0.4 0.3 0.4
TOXE= TOXE= TOXE= TOXE= UO=0.030 TOXE=1.6 TOXE=0 TOXE TOXE=0 TOXE=1
0.7 1.6 0.7 1.6 U0=0.8 .7 =1.6 .7 .6
UO=0.0 U0=0.8 UO=0.0 U0=0.8 UO=0.03 U0=0.8 UO=0.03 U0=0.8
30 30 0 0

DSTDK 0.397 0.369 7.270 1.134 11.292 33.026 126 322 464 1260
POWER

T
DISSIPAT
ION(µW)
ION(ma) 0.120 0.358 0.120 0.358 0.120 0.358 0.051 0.153 0.051 0.153

IOFF(na) 2 0 2 0 2 0 1 0 1 0

DDSDG
POWER
DISSIPAT
ION(µW)
ION(ma)
0.207

0.120
0.155

0.358
ES
41.559

0.120
1.167

0.358
13.181

0.120
38.672

0.358
107

0.051
303

0.153
513

0.051
1412

0.153

IOFF(na) 2 0 2 0 2 0 1 0 1 0

DN1HVT 25.752 26.708 40.951 1.182 16.784 43.690 107 303 513 1412
POWER
DISSIPAT
ION(µW)
ION(ma) 0.030 0.099 0.120 0.358 0.120 0.358 0.051 0.153 0.051 0.153
A
IOFF(na) 0 0 2 0 2 0 1 0 1 0

DN2GD 0.030 0.030 41.359 15.148 16.762 46.690 108 303 485 1350
POWER
DISSIPAT
ION(µW)
IJ

ION(ma) 0.120 0.358 0.120 0.358 0.120 0.358 0.051 0.153 0.051 0.153

IOFF(na) 2 0 2 0 2 0 1 0 1 0

DN1P1HV 23.576 26.875 40.977 1.350 16.823 43.733 107 303 513 1412
T POWER
DISSIPAT
ION(µW)
ION(ma) 0.030 0.099 0.120 0.358 0.120 0.358 0.051 0.153 0.051 0.153

IOFF(na) 0 0 2 0 2 0 1 0 1 0

DN1PKP2 0.042 0.04 0.105 0.104 1.121 2.31 108 303 513 1412
POWER
DISSIPAT

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Salendra.Govindarajulu et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES
Vol No. 5, Issue No. 2, 319 - 331

ION(µW)

ION(ma) 0.03 0.099 0.120 0.358 0.120 0.358 0.051 0.153 0.051 0.153

IOFF(na) 0 0 2 0 2 0 1 0 1 0

DP11PKP 0.038 0.036 0.16 1.167 0.188 1.039 107 303 513 1412
1 POWER
DISSIPAT
ION(µW)
ION(ma) 0.120 0.358 0.120 0.358 0.120 0.358 0.051 0.153 0.051 0.153

IOFF(na) 2 0 2 0 2 0 1 0 1 0

T
Table 22.VOLTAGE VARIATIONS (P AND T CONSTANT):
BENCHMARKCIRCUITS AND2 OR2 XOR2 D-LATCH 4-BITLFSR

VDD=0. VDD=0. VDD= VDD=0. VDD=0. VDD=0. VDD=0. VDD=0. VDD=0. VDD=0.

DSTDK
7

0.321
8
ES
0.160
0.7

0.590
8

1.221
7 8

17.155
7

123
8

159
7

444
8

545
POWER 4.032
DISSIPATION(µ
W)
ION(ma) 0.267 0.250 0.267 0.250 0.107 0.107 0.107 0.107 0.107 0.107

IOFF(na) 1 0 1 0 0 0 0 0 0 0

DDSDG 0.148 0.167 0.665 1.637 3.790 1.882 176 191 728 829
A
POWER
DISSIPATION(µ
W)
ION(ma) 0.267 0.250 0.267 0.250 0.250 0.250 0.107 0.107 0.107 0.107

IOFF(na) 1 0 1 0 0 0 0 0 0 0

DN1HVT 20.942 11.441 0.837 4.661 22.251 176 191 728 829
IJ

POWER 0.676
DISSIPATION(µ
W)
ION(ma) 0.177 0.065 0.267 0.250 0.250 0.250 0.107 0.107 0.107 0.107

IOFF(na) 0 0 1 0 0 0 0 0 0 0

0.033 46.685 0.898 8.877 16.823 22.963 176 191 730 830
POWER
DN2GD DISSIPATION(µ
W)
ION(ma) 0.267 0.0250 0.267 0.250 0.250 0.250 0.107 0.107 0.107 0.107

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Salendra.Govindarajulu et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES
Vol No. 5, Issue No. 2, 319 - 331

IOFF(na) 1 0 1 0 0 0 0 0 0 0

21.271 0.006 0.735 0.943 4.799 22.282 176 191 728 829
DN1P1H POWER
VT DISSIPATION(µ
W)
ION(ma) 0.177 0.065 0.267 0.250 0.250 0.107 0.107 0.107 0.107
0.250

IOFF(na) 0 0 1 0 0 0 0 0 0 0

DN1PKP2 0.048 0.039 0.105 0.091 1.263 1.474 176 191 728 829
POWER
DISSIPATION(µ
W)
ION(ma) 0.177 0.065 0.267 0.250 0.250 0.250 0.107 0.107 0.107 0.107

IOFF(na) 0 0 1 0 0 0 0 0 0 0

DP11PK 0.044 0.128 0.137 82.172 0.803 0.924 176 191 728 829

T
P1 POWER
DISSIPATION(µ
W)
ION(ma) 0.267 0.250 0.267 0.250 0.250 0.250 0.107 0.107 0.107 0.107

IOFF(na) 1
ES
0 1 0 0 0 0 0 0 0

Table23.TEMPERATURE VARATIONS (P AND V CONSTANT)

BENCHMARKCIRCUITS AND2 OR2 XOR2 D-LATCH 4-BITLFSR

127 -73 127 -73 127 -73 127 -73 127 -73
A
DSTDK 0.538 0.392 7.027 25.626 16.495 38.504 273 673 658 1515
POWER
DISSIPATION
(µW)
ION(µA) 0.266 0.445 0.266 0.445 0.266 0.190 0.266 0.586 1.82 1.996
0
IJ

IOFF(nA) 0 0 3762 0 3762 0 3762 0 0 0

DDSDG 0.619 0.149 9.725 16.85 21.230 54.302 160 364 758 1677
POWER
DISSIPATION(µW)
ION 0.266 0.445 0.266 0.445 0.266 0.190 0.266 0.586 1.82 1.996
(µA) 0

IOFF(nA) 0 0 3762 0 3762 0 3762 0 0 0

DN1HVT 33.272 0.05 7.742 15.907 22.845 54.347 160 364 758 1677
POWER
DISSIPATION
(µW)
ION 0.098 0.133 0.266 0.445 0.266 0.190 0.266 0.586 1.82 1.996
(µA) 0

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Salendra.Govindarajulu et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES
Vol No. 5, Issue No. 2, 319 - 331

IOFF 1 0 3762 0 3762 0 3762 0 0 0

DN2GD 0.030 10.236 68.123 0.137 25.864 23.145 160 364 730 1685
POWER
DISSIPATION
(µW)
ION 0.266 0.445 0.266 0.445 0.266 0.190 0.266 0.586 1.82 1.996
(µA) 0
IOFF(nA) 3762 0 3762 0 3762 0 3762 0 0 0

DN1P1HV 33.269 76.778 7.850 16.035 22.878 54.378 160 364 758 1677
T POWER
DISSIPATION
(µW)
ION 0.098 0.133 0.266 0.445 0.266 0.190 0.266 0.586 1.82 1.996
(µA) 0
IOFF(nA) 1 0 3762 0 3762 0 3762 0 0 0

DN1PKP2 0.049 0.058 0.111 0.04 16.02 1.876 160 364 756 1677
POWER
DISSIPATION(µW)
ION(µA) 0.098 0.133 0.266 0.445 0.266 0.190 0.266 0.586 1.82 1.996

T
0
IOFF(nA) 1 0 3762 0 3762 0 3762 0 0 0

DPKP11P 0.045 0.157 0.171 0.164 1.124 1.174 160 364 75 167
1 POWER 8 9
DISSIPATION(µW)
ION(µA) 0.266 0.445 0.266 0.445 0.266 0.190 0.26 0.586 1. 1.99

IOFF(nA) 3762
ES 0 3762 0 3762 0
6

3762 0
82
0
0
6

V. CONCLUSIONS
This work consists of four different parts. In section II, the
circuits Dynamic DCVSL footed circuit, Dynamic DCVSL
footless circuit; Dual-Rail Data-Driven Dynamic Logic and
A
Dual-rail Footless domino gate with self-timed precharge
scheme are successfully implemented using CMOS domino
logic. The proposed circuits have offered an improved
performance in power dissipation, speed and noise tolerance
when compared with standard domino circuit.
In section III, an attempt has been made to simulate the
IJ
domino circuits and also to increase the noise immunity. The
benchmark circuits AND2, OR2, XOR2, 16-bit full adder, 16-
bit comparator, D-flip-flop, 4-bit LFSR are simulated with the
proposed different energy efficient domino logic circuit
techniques in 65nm technology. From the results, it is
observed that the proposed logic technique which is dual
threshold, dual ground and dual supply voltage with N2 high
threshold shows good performance when compared to single
threshold (vt) domino logic techniques. Hence, it is concluded
that the proposed designs will provide a platform for designing
high performance and low power digital circuits and high

benchmark circuits AND2, OR2, XOR2, 16-bit full adder, 16-
bit comparator, D-flip-flop, 4-bit LFSR by the three reduced
swing domino logic circuits. The proposed circuits have
offered an improved performance in power dissipation, speed
and noise tolerance when compared with standard domino
circuit. As it is observed from the results, of all the three
reduced swing circuits, reduced swing domino with dual
supply has low power dissipation, PDP and more tolerance to
noise.
In section IV, the circuit techniques employing dual
thresholds, dual voltages, and dual grounds are presented for
simultaneously reducing power dissipation and delay in
noise immune digital circuits such as, processors and
multipliers.
In section V, an attempt has been made to study the effect
of the PVT variations on the domino circuits with different
techniques given in sections II, III, IV. As it is observed from
the results, when process variations decrease power
dissipation increases, and vice versa. When temperature
variations increase, power dissipation increases and vice versa.
When voltage variations decrease power dissipation decreases.

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Salendra.Govindarajulu et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES
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AUTHORS BIODATA:
1
Salendra.Govindarajulu:- He is working as an Associate Professor in
the Dept. of Electronics & Communication Engg. at RGMCET, Nandyal,
Andhra Pradesh, India. He presented more than 25 International/National
Technical Papers. He is a Life Member of ISTE, New Delhi. He is a member
of IAENG. His interest includes Low Power VLSI CMOS design.
A
IJ
ISSN: 2230-7818 @ 2011 http://www.ijaest.iserp.org. All rights Reserved.
Vol No. 5, Issue No. 2, 319 - 331
Domino Logic Circuits, Proceedings of the IEEE Great Lakes
Symposium on VLSI, pp. 108-112, February 1998.
[11] G. Balamurugan and N. R. Shanbhag, .Energy-efficient
Dynamic Circuit Design in the Presence of Crosstalk Noise,.
Proceedings of the IEEE International Symposium on Low
Power Electronics and Design, pp. 24-29, August 1999.
[12]. S.Govindarajulu, Dr.T.Jayachandra Prasad “Design of High
Performance Dynamic CMOS Circuits in Deep submicron
Technology” International Journal of Engineering Science and
Technology, Vol.2 (7), 2010, pp.2903-2917, ISSN:0975-5462
[13]. S.Govindarajulu, Dr.T.Jayachandra Prasad et.al.
“Low Power, Reduced Dynamic Voltage Swing Domino Logic
Circuits” Indian Journal of Computer Science and Engineering,
2010 pp.74-81, ISSN:0976-5166.
[14]. S.Govindarajulu, Dr.T.Jayachandra Prasad “Energy efficient
Reduced Swing Domino Logic Circuits in 65 nm Technology”
International Journal of Engineering Science and Technology,
Vol.2 (6), 2010, pp.2248-2257, ISSN:0975-5462.
[15]. S.Govindarajulu, Dr.T.Jayachandra Prasad et.al. “Design of
High Performance Arithmetic and Logic Circuits in DSM
Technology”International Journal of Engineering and
Technology, Vol.2 (4), 2010, pp.285-291, ISSN:0975-4024.
[16]. S.Govindarajulu, Dr.T.Jayachandra Prasad et.al. “High
Performance VLSI Design Using Body Biasing in Domino
T
Logic Circuits” International Journal of Computer Science and
Engineering, Vol.2, No.5, 2010 pp.1741-1745, ISSN:0975-
3397.
[17]. S.Govindarajulu, Dr.T.Jayachandra Prasad et.al. “Design of
Low Power, High Speed, Dual Threshold Voltage CMOS
Domino Logic Circuits with PVT Variations” International
Journal of Electronic and Engineering Research, Vol.2,
No.5, 2010 pp.619- 629, ISSN:0975-6450.
2
Dr.T.Jayachandra Prasad:- He is working as a Principal and Professor
in the Dept. of Electronics & Communication Engg. at RGMCET, Nandyal
Andhra Pradesh, India. He presented more than 50 International/National
Technical Papers. He is Life Member in IE (I), CALCUTTA, Life Member in
ISTE, NEW DELHI, Life Member in NAFEN, NEW DELHI, and IEEE
Member. His interest includes Digital Signal Processing.
Page 336
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Vol No. 5, Issue No. 2, 319 - 331

T
ES
A
IJ

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