Proceedings of 11th International Conference on Computer and Information Technology (ICCIT 2008)

25-27 December, 2008, Khulna, Bangladesh

Design and Construction of Direct Sequence Spread Spectrum

CDMA Transmitter and Receiver
M. Habib Ullah, Akhmad Unggul Priantoro, M. Jasim Uddin,
Department of Electrical and Computer Engineering
International Islamic University Malaysia
habib_ctg@yahoo.com
Abstract - Spread Spectrum Communication to process signals that are carried far into the noise,
techniques have been widely accepted in mobile and offer a potential for shared spectrum use with
wireless communications. They have very beneficial existing Systems on a non-interference basis.
and tempting features, like Antijam, security, and Finally, Spread spectrum systems could be useful
multiple accesses. It is the purpose of this paper to
in applications to control multi path interference
describe the features of Spread Spectrum systems. The
[1].
emphasis will be on the Direct Sequence Spread
Spectrum (DS-SS) scheme, Pseudo Noise signals (PN),
Modulators and Demodulators, Hardware II. CDMA OVERVIEW
implementation and illustrate some of the DS-SS Spread Spectrum communication techniques
system features. provide a new method of multiple access, known
Index Terms - CDMA, PN Code, Modulation, as CDMA (Code Division Multiple Access) that is
Demodulation, DS-SS. proposed as an interesting alternative with respect
to the traditional methods, i.e.: the well-known
I. INTRODUCTION TDMA (Time Division Multiple Access) and
Spread Spectrum Communications is one of the FDMA (Frequency Division Multiple Access) [2].
widely used data communication schemes The main parameter in spread spectrum systems is
nowadays. It has many features that make it suitable the processing gain the ratio of transmission and
for secure, multiple accesses, and many other bandwidth has shown in equation 1.
properties that are needed in a communication BW i (1)
G =
system. Spread Spectrum is defined as: Spread p
BW i
Spectrum is a means of transmission in which the The processing gain determines the number of
signal occupies a bandwidth in excess of the users that can be allowed in a system, the amount
minimum necessary to send the information. The of multi-path effect reduction, the difficulty to jam
band spread is accomplished by means of a code, or detect a signal etc. For spread spectrum systems
which is independent of the data, and synchronized it is advantageous to have a processing gain as
reception with the code at the receiver is used for high as possible. A PNcode is a sequence of chips
dispreading, and subsequently data recovery. valued -1 and 1 (polar) or 0 and 1 (non-polar) and
Basically spread spectrum is a coding technique for has noise like properties. This results in low cross-
digital transmission. It was originally developed for correlation values among the codes and the
the military under a veil of secrecy. The purpose of difficulty to jam or detect a data message. Several
coding is to transform an information signal so that families of binary PNcode exist, they are addressed
it looks more like noise. In the receiver, the in another. A usual way to create a PNcode is by
incoming signal is decoded, and the decoding means of at least one shift-register. When the
operation provides resistance to interference and length of such a shift-register is n, the following
multi path fading. The spreading or dilution of equation 2 can be said about the period of the
energy in spread spectrum systems over a wide above mentioned code-families:
bandwidth results in several possible advantages, N DS = 2 n − 1 (2)
short-range interferences-free overlays on their
emissions, and resistance to interference, from other In direct-sequence systems the length of the code is
emissions, and low detestability. The low spectral the same as the spreading-factor with the
density needed for spread spectrum communication consequence has shown in equation 3:
systems, as well as ability of some of these systems

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 G p ( DS ) = N NS
This can also be seen from figure 1, where it shows
how the PNcode is combined with the data signal
(NDS=7). The bandwidth of the data signal is now
multiplied by a factor NDS. The power contents
however stay the same, with the result that the power
spectral density lowers.
Figure 1: direct-sequence spreading
The generation of PN codes is a number of shift-
registers are all that is required. For this reason it is
easy to introduce a large processing-gain in Direct-
Sequence systems. The main problem with applying
Direct Sequence spreading is the so-called Near-Far
effect. This effect is present when an interfering
transmitter is much closer to the receiver than the
intended transmitter. Although the cross-correlation
between codes A and B is low, the correlation
between the received signal from the interfering
transmitter and code A can be higher than the
correlation between the received signal from the
intended transmitter and code.
A. General model of a spread spectrum digital
communication
The input is fed into a channel encoder that produces
an analog signal with a relatively narrow bandwidth
around some center frequency. This signal is further
modulated using the sequence of digits known as
spreading code or spreading sequence. Typically, but
not always, the spreading code is generated by
pseudo noise or pseudo random number, generator.
Figure 2 shows General model of a spread spectrum
digital communication [1].
Figure 2: General model of a spread spectrum digital
communication
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(3) The effect of this modulation is to significantly
increase the bandwidth (spread the spectrum) of
the signal to be transmitted. On the receiving end,
the same digit sequence is used to demodulate the
spread spectrum signal. Finally, the signal is fed in
to a channel decoder to recover the data. Spread
spectrum uses wide band, noise-like signals.
Because spread spectrum signals are noisy they are
hard to detect. Spread spectrum signals are also
hard to intercept or demodulate. Further spread
spectrum signals are harder to jam (interfere with)
than narrow band signals due to the increased
bandwidth. To qualify as a spread spectrum signal,
two criteria should be met:
1. The transmitted signal bandwidth is much
greater than the information bandwidth.
2. Some function other than information being
transmitted is employed to determine the resultant
transmitted bandwidth.
B. Pseudo-Random Noise Codes:
A PNcode used for DS-spreading exists of NDS
units called chips, these chips can have 2 values: -
1/1 (polar) or 0/1. As we combine every data
symbol with a complete PNcode, the DS
processing gain is equal to the code-length.
The sequences must be building from 2-leveled
numbers. The codes must have a sharp (1-chip
wide) autocorrelation peak to enable code
synchronization. The codes must have a low cross-
correlation value, the lower this cross correlation,
the more users we can allow in the system. This
holds for both full-code correlation and partial-
code correlation. The latter because in most
situations there will not be a full-period correlation
of two codes, it is more likely that codes will only
correlate partially (due to random-access
nature).The codes should be ``balanced'': the
difference between ones and zeros in the code may
only be 1. This last requirement stands for good
spectral density properties (equally spreading the
energy over the whole frequency-band).
C. Direct Sequence-spread Spectrum Transmitter
and Receiver
In Direct Sequence-Spread Spectrum the baseband
waveform is multiplied by the PN sequence. The
PN is produced using a PN generator. Frequency
of the PN is higher than the Data signal. This
generator consists of a shift register, and a logic
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 circuit that determines the PN signal. After
spreading, the signal is modulated and transmitted.
The most widely modulation scheme is BPSK
(Binary Phase Shift Keying) [10]. Figure 3 shows the
PN Generator Block Diagram.
Figure 3: PN Generator Block Diagram
The equation 4 represents this DS-SS signal.
2 Es (4)
Sn = m(t ) p (t ) cos(2Π f ct + θ )
Ts
where m(t) is the data sequence, p(t) is the PN
spreading sequence, fC is the carrier frequency, and
θ is the carrier phase angle at t=0. Each symbol in
m(t) represents a data symbol and has a duration of
Ts. Each pulse in p(t) represents a chip, and has a
duration of Tc. The transitions of the data symbols
and chips coincide such that the ratio Ts to Tc is an
integer. The waveforms m(t) and p(t) are shown in
fig. 5. Here we notice the higher frequency of the
spreading signal p(t). The resulting spread signal is
then modulated using the BPSK scheme. The carrier
frequency fc should have a frequency at least 5 times
the chip frequency p(t). In the demodulator section,
there has been simply done reverse the process. We
Demodulate the BPSK signal first, Low Pass Filter
the signal, and then despread the filtered signal, to
obtain the original message. The process has shown
in equation 2.1. In the demodulator section, we
simply reverse the process. Demodulate the BPSK
signal first, Low Pass Filter the signal, and then
despread the filtered signal, to obtain the original
message. The process has been described in equation
5 [3].
m(t ) = sss (t ) × cos(2Π f ct ) + θ
Figure 4: DS-SS Transmitter Block Diagram
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Figure 5: m(t) and p(t) for a Maximum Length PN
m (t ) =
2 Ei 1
m ( t ) p ( t ) [1 + cos( 4 Π f c t + 2θ )]
(6)
Ti 2
As shown in equation 5 and 6 when we multiply
two cosine signals together, we will obtain two
expressions, one of which has twice the frequency
of the original message. And this part can be
removed by a LPF. The output is m ss ( t ) as
shown in figure 5. This design is based on
Coherent Detection BPSK, so we don’t have to
worry about carrier synchronization issues.
Basically we have tried to construct the modulated
part in our project. But for receiving data we have
designed the Demodulator circuit by the software
of ‘Electronic Workbench’. As for the PN
sequence in the receiver, we mentioned earlier that
it should be an exact replica of the one used in the
transmitter, with no delays, because this might
cause severe errors in the incoming messages.
Again, my design is based on the idea that PN
sequences are matched, and actually we are going
to use the same generator for both to ease the
design. There are various techniques that deals
with PN delay problems and mismatches, but we
are not going to encounter any in this design [ 4 ] .
After the signal gets multiplied with the PN
sequence, the signal dispreads, and we obtain the
original bit signal m(t), that was transmitted. The
block diagram of the receiver is shown in figure 6
[5].
(5)
Fi g ur e 6 : D S -S S r e c e i ve r
This simple straightforward description of DS-SS
systems, will allow us to design the Modulator
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 circuits with some ease. We are going to take
advantage of the block diagrams for each one of
them.
D. The Direct sequence spread spectrum
Modulator Design:
In this chapter, we are going to illustrate the circuit Figure 8: The PN Signal
design and show the simulation of the DS-SS
F. The Input Word Generator Design:
Modulator (Transmitter). Simulations were
conducted using the EWB (Electronics workbench) The Word Generator Circuit design is based on the
software and also Hardware. Ideal components were one designed and illustrated in equation 6. The
used for the ease of the design, and to try to avoid Word Generator consists of two ICs, an Inverter, a
other factors, that might directly affect the Clock signal with frequency of 6.666KHz, and a
performance of the system. And since we are going DC supply. The 74163 IC is a TTL 4-bit binary
to design a simple circuit for educational purposes, counter, and the 74166 is a TTL 8-bit Parallel-
we decided to use the ideal components offered In/Serial-Out Shift Register. The Clock signal
inside the software although I constructed it in feeds both ICs as shown in 9. The shift register
hardware[ 9 ] . loads the levels on its inputs when the Parallel
Load signal is activated. Then it starts to shift the
E. The PN Gener ator Design data, and sends them serially. The Parallel Load
The design of the PN generator is based on the block signal is taken from a 4-bit binary counter, so that
diagram shown in figure 7. Here we are going to after the counter finishes its count cycle, it will
need 4 D–Flip–Flops (FFs), a XNOR gate, and a issue the RCO 1 signal, which is used to trigger the
Clock source. Since we are using 4 FFs, m=4 and shift counter to activate the Parallel Load function.
the PN signal will repeat every 15 clock cycles. We There would be obtaining a controllable 8-bit
have chosen the CLK frequency, fCLK=100 KHz. periodic Word Generator signal. The Signal
The period of the PN chip is TPNchip = 1/100k =10- obtained is shown is figure 10. The 8-bit Word is
5
seconds. The total period of the PN sequence TPN then multiplied by the PN signal. In the block
= 15*TPN = 15 *10 −5 seconds. The period of the diagram there has been used a NRZE 2 to adjust
Binary Input signal (per bit) is going to be Tb = the Word level voltages. Now, assuming that we
−5 are using the NRZE, the output of the multiplier
TPN=15*10 seconds, that is a frequency fb=
given the word signal shown in figure 10.
6.6667 KHz. The Clock signal was taken from an
external source (a Function Generator) [ 6 , 7 ] . We
can design a clock using an oscillator. But we are
not going to go into that. The Circuit that resembles
this PN is now easily understood. It is shown in
figure 7. In our project we used only PN without
data. We can let PN is the data. From this design, the
output level from the PN is not 1,-1 as was indicated
in the signal diagram of p(t). The output PN
sequence is shown in figure 8.
Figure 9: The 8-bit Generator Circuit diagram with a
data rate (period of one bit)of 6.666 KHz

Figure 10: The 8-bit word signal.

Figure 7: The PN Generator Circuit Diagram.
There has been seen the PN signal affects the
incoming word signal that is 1/15 of its frequency.

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 When a • 5 is multiplied with a +5 the result is • 25.
And when a • 5 is multiplied by a • 5 the result is a
+25. I mentioned in the previous section that the
output of the PN is a 0–5 volts, not a • 5–5 level.
Also, the Word levels are 0–5 not • 5–5. This means
that i can’t use the multiplication procedure here,
because a 0 * 0 is not equal to 1. To overcome this
problem, and to eliminate the use of a NRZE for the
word signal, i substituted the Multiplier with a
XNOR gate.
G. The BPSK Modulator Design:
This section illustrates the design of the BPSK
modulator. The design is directly based on the block
diagram shown in figure 9. Figure 11 shown in
BPSK Modulator circuit. The design and simulations
are based on the use of ideal components. The BPSK
Modulator is based on the idea of changing the
phase of the carrier signal whenever the incoming
Bit changes its state, for example, if the incoming
message changes its state from 0–1, the carrier
changes its phase by +180°, and if it changes its state
from 1–0 the carrier changes its phase by -180°.
data. The input carrier frequency used in this
design is 5 times fpn chip, which is 500 kHz. But
in our circuit implementation we used carrier of
100 kHz if we give more as like simulation, it is
difficult to find out the phase shift in the oscillator.
Though one can rise the frequency of the signal in
wireless applications to end up with a shorter
antenna for the devices. Anyway, this isn’t our
concern in this report. The modulation process, we
finally get the Sss(t) which is the signal obtained
from the output of the Modulator circuit. The
output of the DS-SS Modulator is shown in figure
12 and precise mode figure 13. Here, a couple of
the bits from Sss(t) has illustrate the output signal.
Figure 12: s ss (t ) The DS-SS signal coming out

Figure 13: s ss (t ) The DS-SS signal coming out of of

the Modulator (Precise mode).
Figure 11: The BPSK Modulator circuit

For the design of BPSK modulator we used two H. Bandwidth consideration of BPSK:
inverting OP-AMP with the gain 1 and also two
A balance modulator is a product modulator, the
analogue switch and one inverter. At operation of
output signal is the product of the two input signal.
the BPSK, the carrier signals are entered into the
In a BPSK modulator, the circuit output signal is
OP-AMPs through the analog switches which are
multiplied by the binary data. If +1V is assigned to
active at the positive pulse. So switches are
a logic 1 and -1V is assigned to a logic 0, the input
controlled by the data. When PN is +ve, the switch
carrier (sin ωct) is multiplied by either a +1 or -1.
one is on and the signal pass and enter into the 1st
Consequently, the output signal is either +1sin ωct
OP-AMP it inverts this signal [8]. At the same time
or -1sin ωct [ 9 , 1 0 ] . This paper described the
2nd switch remains off because it is connected with
design of the modulation technique of direct
an inverter. When this signal cross 2nd OP-AMP the
sequence-spread spectrum with its hardware
signal is inverted again and comes to the original
implementation. It also describes the
position. On the other hand the 2nd switch will be on
characteristics of BPSK modulator. There has been
when the PN is –ve and it will enter into only the
found the circuit’s output characteristics and the
2nd OP-AMP and invert. In this way it transmits
BPSK modulated signal’s characteristic is same

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 although a fault was found in our circuit’s OP-AMP III. Conclusion
(at BPSK modulator circuit). As in obvious form the
observed out put and simulated out put there is same This paper demonstrated the design of a simplified
anomaly. The amplitude of the observed output (fig Direct Sequence Spread Spectrum CDMA system.
14) is not uniform all along. There are sudden jumps Design of 8-bit word generator is given. Spreading
in the output wave shape. The cause of these jumps technique is clearly implemented. Finally, original
may be manufacturing non uniformly of the data are recovered by dispreading in receiver.
integrated circuits.
REFERENCES

[ 1 ] “ An I ntr o d u c t io n to Dir e c t - Se q ue n c e
Spread -Sp ectr u m Co mmuni ca tio ns” .
ht tp : // www. c s. c l e ms o n.e d u/ ~ we s ta ll /8 5 1 /
sp r e a d -sp ec tr u m.p d f
[ 2 ] Si mo n Ha yk i n , “ Co m mu n i c atio n
S ys te ms ” , fo ur t h ed i ti o n, p ub l is h ed b y
J OH AN W I LEY & S ON S, I N C.
[ 3 ] “ Di g ita l d o wn c o n v e r te r /d e sp r e ad e r fo r
Figure 14: Circuit’s output direc t seq ue n ce sp r ead sp e ctr um C D M A
co m mu n ic at io n s s ys te m ”.
In the physical structure, it has been used available ht tp : // www. p a te n t sto r m. u s/p ate n t s/6 1 4 1 3
components. Firstly there has been first designed it 7 2 -d e s c r ip tio n. h t ml
by the simulation software named EWB (Electronics [4] “Acq ui si tio n o f Dir ect Seq u e nce Spre ad
Workbench). There also has been designed the Sp ec tr u m Aco u st ic Co m mu n i ca tio n
Demodulator circuit with the software and it works Si g n a l s” .
successfully. ht tp : // www. mi t. ed u/ ~ mi lli t sa /r e so ur ce s /p
d f s/ a c q . p d f
[5 ] Sa mu e l C., Ya n y, “C DM A RF S ys t e m
E n g i neer i n g”, F ir st ed i ti o n
[ 6 ] “ S up p le me n t a l T ex t B o o k o f CD M A- O ne
B as ic T echno lo gi e s” T r ai ni ng te xt boo k-
FUJ I T S U, J ul y 2 0 0 0 .
[7] “C DM A T echno lo gy Re so ur c es : W el co me
to t h e wo r ld o f C D M A: Co m mo n air
in ter f a c e ” 2 0 0 3 CD M A De v e lo p me n t
gr o up
ht tp : // www. c d g.o r g/ tec h no l o g y/i nd e x.a sp
).
Figure 15: DS-SS receiver circuit diagram [ 8 ] “ C OF DM a s a mo d u la t io n t ec h n iq ue o f
wi re le s s t ele co mmuni cat io n wi t h a
Figure 14 shows the diagram of the filter (the Sallen- CD M A co mp ari so n” T h es is -Erc La wr e y-
Key second order active filter) and figure 15 shows 1997
the full diagram of the demodulator circuit. One who [9] J .K. T ho ma c y “Di gi ta l co mmuni cat io n
s ys te m”.
is interested as for Multiplier (Balance Modulator)
[10] S.L. Gupta & Dr. V. Kumar “Handbook of
he can use MC1496 IC. Here all equipments are electronics”, 31st revised and enlarged edition.
common and available. Finally, hope that this report
has supplied you with some new information,
techniques, and ideas. Again, it is intended to be as
an educational supplement for any advanced
communications course, where the student wants to
see a practical application on what is studying.

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