Digital Electronics Assignment Sample Solutions

Q1. (a) (i) Determine the truth table of a half adder

A B Sum Cout
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

(ii) Implement the half adder by using 74153, dual 4-to-1 multiplexer. Hint: one
multiplexer for Sum and the other for Cout.
74153
B 14 0 0
2 G3
A 1
+5v
1 EN MUX
R1 6 0
5 1 7 Sum
1k 4 2
3 3
15
10
11 9 Cout
12
13

(b) Write the logic expression of F in terms of W, X, Y and Z for the following circuit.
Convert it into standard SOP. D is the MSB and A is the LSB.
+5v

24
VCC
Y0 1
74154 Y1 2
Y2 3
Z 23 A0 Y3 4
Y 22 A1 Y4 5
21 6 7420
X A2 Y5 1
W 20 A3 Y6 7
2
Y7 8 6 F
4
18 E1 Y8 9
5
19 E2 Y9 10
Y10 11
Y11 13
Y12 14
Y13 15
Y14 16
Y15 17
GND

12

1
 Since F = Y 0 ⋅ Y 3 ⋅ Y 6 ⋅ Y 13
And as Y 0 = W ⋅ X ⋅ Y ⋅ Z and Y 3 = W ⋅ X ⋅ Y ⋅ Z
Y 6 = W ⋅ X ⋅ Y ⋅ Z and Y 13 = W ⋅ X ⋅ Y ⋅ Z

Thus F = (W ⋅ X ⋅ Y ⋅ Z ) ⋅ (W ⋅ X ⋅ Y ⋅ Z ) ⋅ (W ⋅ X ⋅ Y ⋅ Z ) ⋅ (W ⋅ X ⋅ Y ⋅ Z )

= W ⋅ X ⋅Y ⋅ Z + W ⋅ X ⋅Y ⋅ Z + W ⋅ X ⋅Y ⋅ Z + W ⋅ X ⋅Y ⋅ Z

(c) Construct a 1-of-24 address decoder using several 74138. The input are (MSB) A4 A3
A2 A1 A0 (LSB) and the output are Q23 … Q0. The A input of the 74138 is the MSB
and C input is the LSB.
Since 74138 is a 1-of-8 address decoder, thus to implement a 1-of-24 address decoder
we need three 74138 ICs.

Q2 (a) Construct an asynchronous ripple counter for counting from 0 to 6 (MOD-7) in

ascending order. Input is CLOCK and outputs are (MSB) Q2, Q1 and Q0 (LSB).
Implement by using 7473 negative-edge trigger JK Flip-Flops

+5v U1a Q0 +5v U1b Q1 +5v U2a

Q2
7473 7473 7473
14 J Q 12 7 J Q 9 14 J Q 12

Clock 1 5 1

3 K 13 10 K 8 3 K 13
CLR Q CLR Q CLR Q
2 6 2

7410
1
12 U3a 2
13

2
 Implement by using 7474 positive-edge trigger D type Flip-Flops
+5v Q0 +5v Q1 +5v Q2

4 U1a 13 U1b 4 U2a

2 D S Q 5 11 D S Q 9 2 D S Q 5
7474 7474 7474
Clock 3 12 3

6 8 6
R Q R Q R Q
1 10 1

1
12 U3a 2
13
7410

(b) Sketch the output waveforms of Q0, Q1, and Q2.

Output waveform when implemented by 7473 negative-edge trigger JK Flip-Flops

Output waveform when implemented by 7474 positive-edge trigger D Flip-Flops

3
 (c) Construct an asynchronous counter for counting from 7 to 3 in descending order. Input
is CLOCK and outputs are (MSB) Q2, Q1 and Q0 (LSB). (Hints: use positive-edge
triggered JK flip-flops and initially preset to ONE.)

7432
3 U3a 1
2

+5v +5v +5v

U1a 2 Q0 U1b 7 U2a 2 Q2
Q1
4 J S Q 15 9 J S Q 11 4 J S Q 15
7476 7476 7476
Clock 1 6 1

16 K 14 12 K 10 16 K 14
R Q R Q R Q
3 8 3

+5v +5v +5v

(d) Sketch the output waveforms of Q0, Q1, and Q2.

Output waveform when implemented by the above circuit.

Q3. (a) A logic family has a supply voltage of 3.3V, ICCH = 5mA and ICCL = 50mA. Find the
power dissipation?
The average power dissipation PD is equal to PD = VCC × ICC = VCC × (ICCH + ICCL)/2
⇒ PD = 3.3 × (5 + 50) / 2 = 3.3 × 27.5 mW = 90.75 mW
(b) What is the key factor to compare the overall performance of different logic families?
Speed-Power Product
(c) The following is an interconnection of two NAND gates.

4
 7400 Interconnection 7400
1 4
Low 3 6 Low
2 U1a 5 U1b

Determine whether the interconnection is "current-source" or "current-sink".

These terms are connected with current direction. If current flows from integrated
circuit to the load, we have source, and circuit output goes high (positive). In the
opposite case, when current flows from the load to integrated circuit we have a
sink and circuit output goes low.

Based on the above summary, we can conclude that the interconnection is current
source.

(d) The following four gates have totem-pole outputs. Reduce the number of gates to three
but keep the same Boolean expression.
7408
A 1
3
2 U1a
B
7408 7427
1
4
6 2 U2a 12
C 5 U1b F
13
7408
9
8
10 U1c

Since F = A ⋅ B + B ⋅ C + A ⋅ C
= A⋅ B • B ⋅C • A⋅C
Therefore, we can reduce the number of gate by using open collector output by taking
the advantage of wired-AND logic
+5v

R1
1k
7401
A 1
3
2 U3a
B
7401
4
6
C 5 U3b

7401
9
8
10 U3c

5
(e) Briefly explain why tri-state output is more suitable to connect to common data bus.
During tri-state, the output impedance of a device is set to very high so as not to affect
the other outputs connected to the common bus. It is essential to common data bus
system since the bus will be shared by different devices in a time division multiplexed
method. The devices which are not activated should turn their outputs to tri-state.

END