A-1 Appendix A: Digital Logic

Principles of Computer Architecture

Miles Murdocca and Vincent Heuring

Appendix A: Digital Logic

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-2 Appendix A: Digital Logic

Chapter Contents
A.1 Introduction
A.2 Combinational Logic
A.3 Truth Tables
A.4 Logic Gates
A.5 Properties of Boolean Algebra
A.6 The Sum-of-Products Form, and Logic Diagrams
A.7 The Product-of-Sums Form
A.8 Positive vs. Negative Logic
A.9 The Data Sheet
A.10 Digital Components
A.11 Sequential Logic
A.12 Design of Finite State Machines
A.13 Mealy vs. Moore Machines
A.14 Registers
A.15 Counters

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-3 Appendix A: Digital Logic

Some Definitions
• Combinational logic: a digital logic circuit in which logical deci-
sions are made based only on combinations of the inputs. e.g. an
adder.
• Sequential logic: a circuit in which decisions are made based on
combinations of the current inputs as well as the past history of
inputs. e.g. a memory unit.
• Finite state machine: a circuit which has an internal state, and
whose outputs are functions of both current inputs and its inter-
nal state. e.g. a vending machine controller.

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-4 Appendix A: Digital Logic

The Combinational Logic Unit

• Translates a set of inputs into a set of outputs according to one or
more mapping functions.
• Inputs and outputs for a CLU normally have two distinct (binary)
values: high and low, 1 and 0, 0 and 1, or 5 V and 0 V for example.
• The outputs of a CLU are strictly functions of the inputs, and the
outputs are updated immediately after the inputs change. A set of
inputs i0 – in are presented to the CLU, which produces a set of
outputs according to mapping functions f0 – fm.

i0 f0 (i0, i1)
i1 Combinational f1 (i1, i3, i4)
...

logic unit ...

in fm(i9, in)
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-5 Appendix A: Digital Logic

A Truth Table
• Developed in 1854 by George Boole.
• Further developed by Claude Shannon (Bell Labs).
• Outputs are computed for all possible input combinations (how
many input combinations are there?)
• Consider a room with two light switches. How must they work?

Inputs Output
GND
Light Z A B Z
“Hot”
0 0 0
0 1 1
1 0 1
1 1 0
Switch A Switch B

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-6 Appendix A: Digital Logic

Alternate Assignment of Outputs to

Switch Settings
• We can make the assignment of output values to input combi-
nations any way that we want to achieve the desired input-out-
put behavior.
Inputs Output

A B Z

0 0 1
0 1 0
1 0 0
1 1 1

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-7 Appendix A: Digital Logic

Truth Tables Showing All Possible

Functions of Two Binary Variables
Inputs Outputs
A B False AND AB A AB B XOR OR
• The more fre-
quently used func- 0 0 0 0 0 0 0 0 0 0
tions have names: 0 1 0 0 0 0 1 1 1 1
AND, XOR, OR, 1 0 0 0 1 1 0 0 1 1
NOR, XOR, and 1 1 0 1 0 1 0 1 0 1
NAND. (Always
use upper case Inputs Outputs
spelling.) A B NOR XNOR B A+B A A + B NAND True

0 0 1 1 1 1 1 1 1 1
0 1 0 0 0 0 1 1 1 1
1 0 0 0 1 1 0 0 1 1
1 1 0 1 0 1 0 1 0 1

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-8 Appendix A: Digital Logic

Logic Gates and Their Symbols

• Logic symbols A B F A B F
0 0 0 0 0 0
shown for AND, OR, 0 1 0 0 1 1
buffer, and NOT 1 0 0 1 0 1
Boolean functions. 1 1 1 1 1 1

• Note the use of the A A

F=AB F=A+B
“inversion bubble.” B B
AND OR
• (Be careful about
the “nose” of the
gate when drawing A F A F
AND vs. OR.) 0 0 0 1
1 1 1 0

A F=A A F= A

Buffer NOT (Inverter)

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-9 Appendix A: Digital Logic

Logic Gates and their Symbols (cont’)

A B F A B F
0 0 1 0 0 1
0 1 1 0 1 0
1 0 1 1 0 0
1 1 0 1 1 0

A A
F= A B F= A + B
B B

NAND NOR

A B F A B F
0 0 0 0 0 1
0 1 1 0 1 0
1 0 1 1 0 0
1 1 0 1 1 1

A A
F=A⊕B F = A ⊕. B
B B

Exclusive-OR (XOR) Exclusive-NOR (XNOR)

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-10 Appendix A: Digital Logic

Variations of Logic Gate Symbols

A A
B F = ABC F = A+ B
C B

(a) (b)

A A+ B
B A+ B

(c)

(a) 3 inputs (b) A Negated input (c) Complementary outputs

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-11 Appendix A: Digital Logic

Transistor Operation of Inverter

OUTPUT VOLTAGE vs. INPUT VOLTAGE
4.0

3.5 V CC = 5 V
VCC
R L = 400 Ω

V O –Output Voltage–V
3.0

2.5
VCC = +5 V RL
VCC 2.0
Vout
A 1.5
A A Vin
Collector 1.0
Base Emitter A
0.5
GND = 0 V 0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
V I–Input Voltage–V

(a) (b) (c) (d)

(a) Inverter showing power terminals; (b) transistor symbol; (c) tran-
sistor configured as an inverter; (d) inverter transfer function.

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-12 Appendix A: Digital Logic

Assignments of 0 and 1 to Voltages

+5 V +5 V

Logical 1 Logical 1

2.4 V
2.0 V
Forbidden Range Forbidden Range
0.8 V
0.4 V Logical 0
0V Logical 0 0V
(a) (b)
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-13 Appendix A: Digital Logic

Transistor Operation of Logic Gates

VCC
(a) NAND; (b) NOR

VCC
Vout
AB
V1
A Vout
A+B

V2 V1 V2
B A B

(a) (b)

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-14 Appendix A: Digital Logic

Tri-State Buffers
• Outputs can be 0, 1, or “electrically disconnected.”

C A F C A F
0 0 ø 0 0 0
0 1 ø 0 1 1
1 0 0 1 0 ø
1 1 1 1 1 ø

A F=AC A F = AC
or or
C C
F=ø F=ø
Tri-state buffer Tri-state buffer, inverted control

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-15 Appendix A: Digital Logic

Properties of Boolean Algebra

Relationship Dual Property
• Principle of
AB = BA A+B = B+A Commutative
duality: The
dual of a Postulates A (B + C) = A B + A C A + B C = (A + B) (A + C) Distributive

Boolean 1A=A 0+A = A Identity

function is AA = 0 A+A = 1 Complement

obtained by 0A = 0 1+A = 1 Zero and one theorems
replacing AA =A A+A = A Idempotence
AND with OR
A (B C) = (A B) C A + (B + C) = (A + B) + C Associative
and OR with
Theorems

A = A Involution
AND, 1s with
AB= A+ B A+ B = A B DeMorgan’s Theorem
0s, and 0s
with 1s. AB + AC + BC ( A + B )( A + C )( B +C) Consensus Theorem
= AB + AC = ( A + B)(A + C )
A (A + B) = A A+AB = A Absorption Theorem

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-16 Appendix A: Digital Logic

DeMorgan’s Theorem
A B AB = A + B A + B = AB

0 0 1 1 1 1
0 1 1 1 0 0
1 0 1 1 0 0
1 1 0 0 0 0

DeMorgan’s theorem: A+B = A+B = AB

A A
F=A+B F=AB
B B

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-17 Appendix A: Digital Logic

All-NAND Implementation of OR
• NAND alone implements all other Boolean logic gates.

A
A
A+B A+ B
B
B

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-18 Appendix A: Digital Logic

Sum-of-Products Form: The Majority

Function
• The SOP form for the 3-input majority function is:
M = ABC + ABC + ABC + ABC = m3 + m5 + m6 + m7 = Σ (3, 5, 6, 7).
• Each of the 2n terms are called minterms, ranging from 0 to 2n - 1.
• Note relationship between minterm number and boolean value.

Minterm A B C F
Index 1
0 0 0 0 0
1 0 0 1 0 0 0
2 0 1 0 0 0-side 1-side
3 0 1 1 1
4 1 0 0 0
5 1 0 1 1
6 1 1 0 1 A balance tips to the left or
right depending on whether
7 1 1 1 1 there are more 0’s or 1’s.
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-19 Appendix A: Digital Logic

AND-OR Implementation of Majority

A B C

• Gate count is
8, gate input
count is 19.
ABC

ABC

AB C

ABC

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-20 Appendix A: Digital Logic

Notation Used at Circuit Intersections

Connection No connection

Connection No connection
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-21 Appendix A: Digital Logic

OR-AND Implementation of Majority

A B C

A+ B+ C

A+ B+C

A+ B+ C

A+ B+ C

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-22 Appendix A: Digital Logic

Positive/Negative Logic Assignments

• Positive logic: logic 1 is represented by high voltage; logic 0 is
represented by low voltage.
• Negative logic: logic 0 is represented by high voltage; logic 1 is
represented by low voltage.
Gate Logic: Positive vs. Negative Logic
Normal Convention: Postive Logic/Active High
Low Voltage = 0; High Voltage = 1

Alternative Convention sometimes used: Negative Logic/Active Low

Voltage Truth T able Positive Logic Negative Logic

A B F A B F A B F
low low low 0 0 0 1 1 1
low high low 0 1 0 1 0 1
high low low 1 0 0 0 1 1
high high high 1 1 1 0 0 0

Behavior in terms Two Alternative Interpretations

of Electrical Levels
Positive Logic AND
Negative Logic OR

Dual Operations
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-23 Appendix A: Digital Logic

Positive/Negative Logic Assignments

(Cont’)
Voltage Levels Positive Logic Levels Negative Logic Levels
A B F A B F A B F
low low low 0 0 0 1 1 1
low high low 0 1 0 1 0 1
high low low 1 0 0 0 1 1
high high high 1 1 1 0 0 0

A Physical A A
F F=AB F=A+B
B AND gate B B

Voltage Levels Positive Logic Levels Negative Logic Levels

A B F A B F A B F
low low high 0 0 1 1 1 0
low high high 0 1 1 1 0 0
high low high 1 0 1 0 1 0
high high low 1 1 0 0 0 1

A Physical
F A A
B NAND gate F= A B F = A + B
B B

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-24 Appendix A: Digital Logic

Bubble Matching

Positive logic x0 Positive Negative logic x0 Negative

Positive logic x1 Logic Negative logic x1 Logic

(a) (b)
x0 Bubble match
Negative logic
Negative logic x0 Negative Negative
Negative logic x1 Logic Logic
Negative logic
Bubble mismatch x1 Bubble match
(c) (d)

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-25 Appendix A: Digital Logic
SN7400 QUADRUPLE 2-INPUT POSITIVE-NAND GATES

description
These devices contain four independent schematic (each gate)
2-input NAND gates. V CC

Example function table (each gate)

INPUTS
A B
OUTPUT
Y
package (top view)

1A
1B
1
2
14
13
VCC
4B
4 kΩ 1.6 kΩ 130 Ω

Data Sheet
1Y 3 12 4A
H H L 4 11 A
2A 4Y
L X H 2B 5 10 3B B
2Y 6 9 3A
X L H GND 7 8 3Y
Y

absolute maximum ratings

Supply voltage, VCC 7V
Input voltage: 5.5 V 1 kΩ
Operating free-air temperature range: 0 ˚C to 70 ˚C
Storage temperature range – 65 ˚ C to 150 ˚C GND

• Simplified data recommended operating conditions

MIN NOM MAX UNIT
sheet for 7400 logic diagram (positive logic)
1A
1Y
V CC Supply voltage 4.75 5 5.25 V
1B

NAND gate, 2A
2B
3A
2Y
V IH
V IL
High-level input voltage
Low-level input voltage
2

0.8
V

V
3Y

adapted from Texas 3B

4A
4B
4Y
IOH
IOL
High-level output current
Low-level output current
– 0.4

16
mA

mA

Instruments TTL Y = AB TA Operating free-air temperature 0 70 ˚C

electrical characteristics over recommended operating free-air temperature range

Databook [Texas MIN TYP MAX UNIT
V OH V CC = MIN, V IL = 0.8 V, IOH = – 0.4 mA
Instruments, 1988] V OL V CC = MIN, V IH = 2 V, IOL = 16 mA
2.4 3.4
0.2 0.4
V
V
IIH V CC = MAX, V I = 2.4 V 40 µA
IIL V CC = MAX, V I = 0.4 V – 1.6 mA
ICCH V CC = MAX, V I = 0 V 4 8 mA
ICCL V CC = MAX, V I = 4.5 V 12 22 mA

switching characteristics, V CC = 5 V, T A = 25˚ C

PARAMETER FROM (input) TO (output) TEST CONDITIONS MIN TYP MAX UNIT
tPLH R L = 400 Ω 11 22 ns
A or B Y
tPHL C L = 15 pF
7 15 ns

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-26 Appendix A: Digital Logic

Digital Components
• High level digital circuit designs are normally created using col-
lections of logic gates referred to as components, rather than us-
ing individual logic gates.
• Levels of integration (numbers of gates) in an integrated circuit
(IC) can roughly be considered as:
• Small scale integration (SSI): 10-100 gates.
• Medium scale integration (MSI): 100 to 1000 gates.
• Large scale integration (LSI): 1000-10,000 logic gates.
• Very large scale integration (VLSI): 10,000-upward logic
gates.
• These levels are approximate, but the distinctions are useful
in comparing the relative complexity of circuits.

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-27 Appendix A: Digital Logic

Multiplexer

D0 00
Data Inputs

A B F
D1 01
F
D2 10 0 0 D0
D3 11 0 1 D1
1 0 D2
1 1 D3
A B
Control Inputs

F = A B D0 + A B D1 + A B D2 + A B D3

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-28 Appendix A: Digital Logic

AND-OR Implementation of MUX

D0

D1

F
D2

D3

A B

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-29 Appendix A: Digital Logic

MUX Implementation of Majority

• Principle: Use the 3 MUX control inputs to select (one at a time)
the 8 data inputs.

0 000
A B C M 0 001
0 0 0 0 0 010
0 0 1 0 1 011
F
0 1 0 0 0 100
0 1 1 1 1 101
1 0 0 0 1 110
1 0 1 1 1 111
1 1 0 1
1 1 1 1
A B C
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-30 Appendix A: Digital Logic

4-to-1 MUX Implements 3-Var Function

• Principle: Use the A and B inputs to select a pair of minterms.
The value applied to the MUX data input is selected from {0, 1,
C, C} to achieve the desired behavior of the minterm pair.

A B C F

0 0 0 0 0 00
0 0 1 0 0
1 01
F
0 1 0 1 C 10
1
0 1 1 1 C 11
1 0 0 0
C
1 0 1 1
1 1 0 1 A B
C
1 1 1 0

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-31 Appendix A: Digital Logic

Demultiplexer

00 F0 D A B F0 F1 F2 F3
01 F1
D 0 0 0 0 0 0 0
10 F2
0 0 1 0 0 0 0
11 F3
0 1 0 0 0 0 0
0 1 1 0 0 0 0
A B 1 0 0 1 0 0 0
1 0 1 0 1 0 0
F0 = D A B F2 = D A B 1 1 0 0 0 1 0
1 1 1 0 0 0 1
F1 = D A B F3 = D A B

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-32 Appendix A: Digital Logic

Gate-Level Implementation of DEMUX

F0

F1
D
F2

F3

A B
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-33 Appendix A: Digital Logic

Decoder

Enable = 1 Enable = 0

A B D 0 D1 D2 D3 A B D0 D 1 D 2 D 3
00 D0
A 01 D1 0 0 1 0 0 0 0 0 0 0 0 0
B 10 D2 0 1 0 1 0 0 0 1 0 0 0 0
1 0 0 0 1 0 1 0 0 0 0 0
Enable 11 D3
1 1 0 0 0 1 1 1 0 0 0 0

D0 = A B D1 = A B D2 = A B D3 = A B

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-34 Appendix A: Digital Logic

Gate-Level Implementation of Decoder

D0

D1

A
D2
B

D3

Enable

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-35 Appendix A: Digital Logic

Decoder Implementation of Majority

Function

• Note that the en- 000

able input is not
001
always present.
We use it when 010
A
discussing de- 011
B M
coders for 100
memory. C
101
110
111

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-36 Appendix A: Digital Logic

Priority Encoder
• An encoder translates a set of inputs into a binary encoding.
• Can be thought of as the converse of a decoder.
• A priority encoder imposes an order on the inputs.
• Ai has a higher priority than Ai+1
A0 A1 A2 A3 F0 F1

0 0 0 0 0 0
0 0 0 1 1 1
A0 00 0 0 1 0 1 0
A1 01 F0 0 0 1 1 1 0
0 1 0 0 0 1
A2 10 F1
0 1 0 1 0 1
A3 11 0 1 1 0 0 1
0 1 1 1 0 1
1 0 0 0 0 0
1 0 0 1 0 0
F0 = A0 A1 A3 + A0 A1 A2 1 0 1 0 0 0
F1 = A0 A2 A3 + A0 A1 1 0 1 1 0 0
1 1 0 0 0 0
1 1 0 1 0 0
1 1 1 0 0 0
1 1 1 1 0 0

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-37 Appendix A: Digital Logic

AND-OR Implementation of Priority

Encoder
A0

F0
A1

A2

F1
A3

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 A-38 A B C Appendix A: Digital Logic

Programmable OR matrix

Logic Array

• A PLA is a
customizable AND
matrix followed by
a customizable
OR matrix.
• Black box view of
PLA:

A F0 Fuses
B PLA
C F1
AND matrix

F0 F1
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-39 A B C Appendix A: Digital Logic

Simplified ABC

Representation AB C

of PLA ABC

Implementation ABC

of Majority
Function

F0 F1
(Majority) (Unused)
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-40 Appendix A: Digital Logic

Example: Ripple-Carry Addition

Carry In 0 0 0 0 1 1 1 1
Operand A 0 0 1 1 0 0 1 1
Operand B + 0 + 1 + 0 + 1 + 0 + 1 + 0 + 1
0 0 0 1 0 1 1 0 0 1 1 0 1 0 1 1

Carry Sum Example:

Out Carry 1 0 0 0
Operand A 0 1 0 0
Operand B + 0 1 1 0
Sum 1 0 1 0

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-41 Appendix A: Digital Logic

Full Adder

Ai Bi Ci Si Ci+1
Bi Ai
0 0 0 0 0 Ci
0 0 1 1 0
0 1 0 1 0 Full
0 1 1 0 1 adder
1 0 0 1 0
1 0 1 0 1 Ci+1
1 1 0 0 1 Si
1 1 1 1 1

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-42 Appendix A: Digital Logic

Four-Bit Ripple-Carry Adder

• Four full adders connected in a ripple-carry chain form a four-bit
ripple-carry adder.

b3 a3 b2 a2 b1 a1 b0 a0
c3 c2 c1 c0
0

Full Full Full Full

adder adder adder adder

c4

s3 s2 s1 s0

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-43 Appendix A: Digital Logic
A B Cin

PLA Realization
of Full Adder

Sum Cout

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-44 Appendix A: Digital Logic

Sequential Logic
• The combinational logic circuits we have been studying so far
have no memory. The outputs always follow the inputs.
• There is a need for circuits with memory, which behave differ-
ently depending upon their previous state.
• An example is a vending machine, which must remember how
many and what kinds of coins have been inserted. The machine
should behave according to not only the current coin inserted,
but also upon how many and what kinds of coins have been in-
serted previously.
• These are referred to as finite state machines, because they can
have at most a finite number of states.

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-45 Appendix A: Digital Logic

Classical Model of a Finite State

Machine
• An FSM is com-
posed of a com- io fo

...

...
Inputs Outputs
binational logic ik Combinational fm
unit and delay logic unit

...

...
elements (called
flip-flops) in a
feedback path, State bits
which maintains Q0 D0
state informa- s0

tion.

...
Qn Dn
sn
Synchronization
signal
Delay elements (one per state bit)

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-46 Appendix A: Digital Logic

NOR Gate with Lumped Delay

1
A
0

1
A B
∆τ A+ B 0
B
1
A+ B 0

∆τ
Timing Behavior

• The delay between input and output (which is lumped at the out-
put for the purpose of analysis) is at the basis of the functioning
of an important memory element, the flip-flop.

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-47 Appendix A: Digital Logic

S-R Flip-Flop
• The S-R flip-flop is an active high (positive logic) device.

Qt St Rt Qi+1 S

S 0 0 0 0 R
Q 0 0 1 0
0 1 0 1
Q
0 1 1 (disallowed)
1 0 0 1
R Q Q
1 0 1 0
1 1 0 1 ∆τ ∆τ
1 1 1 (disallowed) 2∆τ 2∆τ
Timing Behavior

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-48 Appendix A: Digital Logic

NAND Implementation of S-R Flip-Flop

S S S R
Q Q Q Q

R Q R Q R Q S Q

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-49 Appendix A: Digital Logic

A Hazard
A

AB
Glitch caused by
C S a hazard
S
Q
B ∆τ
A AB R

R Q Q

Q
∆τ

2∆τ
Timing Behavior

• It is desirable to be able to “turn off” the flip-flop so it does not

respond to such hazards.
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-50 Appendix A: Digital Logic

A Clock Waveform: The Clock Paces

the System
Amplitude

Time

Cycle time = 25ns

• In a positive logic system, the “action” happens when the clock is

high, or positive. The low part of the clock cycle allows propaga-
tion between subcircuits, so their inputs settle at the correct value
when the clock next goes high.

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-51 Appendix A: Digital Logic

Scientific Prefixes
• For computer memory, 1K = 210 = 1024. For everything else, like
clock speeds, 1K = 1000, and likewise for 1M, 1G, etc.

Prefix Abbrev. Quantity Prefix Abbrev. Quantity

milli m 10–3 Kilo K 103
micro µ 10–6 Mega M 106
nano n 10–9 Giga G 109
pico p 10–12 Tera T 1012
femto f 10–15 Peta P 1015
atto a 10–18 Exa E 1018

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-52 Appendix A: Digital Logic

Clocked S-R Flip-Flop

S

S R
Q
CLK
CLK

Q Q
R
Q
∆τ
2∆τ
Timing Behavior

• The clock signal, CLK, enables the S and R inputs to the flip-flop.

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-53 Appendix A: Digital Logic

Clocked D Flip-Flop
• The clocked D flip-flop, sometimes called a latch, has a potential
problem: If D changes while the clock is high, the output will also
change. The Master-Slave flip-flop (next slide) addresses this prob-
lem.

D D
Q
CLK
CLK
Circuit

Q Q

Q
∆τ ∆τ
D Q
2∆τ 2∆τ
Symbol
C Q Timing Behavior

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-54 Appendix A: Digital Logic

Master-Slave Flip-Flop
• The rising edge of the clock loads new data into the master,
while the slave continues to hold previous data. The falling
edge of the clock loads the new master data into the slave.

Master Slave D

D D QM D QS
CLK
Circuit
CLK C C QS QM

QS

QS
D Q
∆τ ∆τ
Symbol
Q 3∆τ 2∆τ 2∆τ 2∆τ
Timing Behavior

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-55 Appendix A: Digital Logic

Clocked J-K Flip-Flop

• The J-K flip-flop eliminates the disallowed S=R=1 problem of the S-R
flip-flop, because Q enables J while Q’ disables K, and vice-versa.
• However, there is still a problem. If J goes momentarily to 1 and
then back to 0 while the flip-flop is active and in the reset state, the
flip-flop will “catch” the 1. This is referred to as “1’s catching.”
• The J-K Master-Slave flip-flop (next slide) addresses this problem.

J
Q
J Q
CLK
K Q
Q
K

Symbol
Circuit
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-56 Appendix A: Digital Logic

Master-Slave J-K Flip-Flop

J
Q
J Q
CLK
K Q
Q
K

Symbol
Circuit

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-57 Appendix A: Digital Logic

Clocked T Flip-Flop
• The presence of a constant 1 at J and K means that the flip-flop
will change its state from 0 to 1 or 1 to 0 each time it is clocked
by the T (Toggle) input.

1 J Q Q
T T
K Q Q

Circuit Symbol

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-58 Appendix A: Digital Logic

Negative Edge-Triggered D Flip-Flop

• When the clock is Stores D
high, the two input
latches output 0, so
the Main latch re-
mains in its previous
state, regardless of R

changes in D. Q

• When the clock goes CLK

high-to-low, values in Q
the two input latches S
will affect the state of
Main latch
the Main latch.
• While the clock is D
low, D cannot affect
Stores D
the Main latch.

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-59 Appendix A: Digital Logic

Example: Modulo-4 Counter

• Counter has a clock input (CLK) and a RESET input.
• Counter has two output lines, which take on values of 00, 01, 10,
and 11 on subsequent clock cycles.
Time (t) 4 3 2 1 0 4 3 2 1 0 Time (t)
00001 RESET q0 01100
3-bit q1 01010
Synchronous
s0
Counter D Q
s1 s0
D Q
Q
s1
CLK Q

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-60 Appendix A: Digital Logic

Output 00 Output 01
state state
RESET 0/01
State
1/00 A B
Transition q1 q0
1/00
Diagram for
Mod-4 1/00
0/10
Counter 0/00
1/00

C D
0/11

Output 10 Output 11
state state

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-61 Appendix A: Digital Logic

State Table for Mod-4 Counter

Input RESET
Present state 0 1
A B/01 A/00
B C/10 A/00
C D/11 A/00
D A/00 A/00

Next state Output

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-62 Appendix A: Digital Logic

State Assignment for Mod-4 Counter

Input RESET
Present
state (St) 0 1
A:00 01/01 00/00
B:01 10/10 00/00
C:10 11/11 00/00
D:11 00/00 00/00

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-63 Appendix A: Digital Logic

Truth Table for Mod-4 Counter

RESET s1 (t) s0 (t) s1 s0 (t+1) q1 q0 (t+1)

r(t)

0 0 0 01 01 s0 (t+1) = r(t)s1 (t)s0 (t) + r(t)s1 (t)s0 (t)

0 0 1 10 10
s1 (t+1) = r(t)s1 (t)s0 (t) + r(t)s1 (t)s0 (t)
0 1 0 11 11
0 1 1 00 00 q0 (t+1) = r(t)s1 (t)s0 (t) + r(t)s1 (t)s0 (t)
1 0 0 00 00
q1 (t+1) = r(t)s1 (t)s0 (t) + r(t)s1 (t)s0 (t)
1 0 1 00 00
1 1 0 00 00
1 1 1 00 00

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-64 Appendix A: Digital Logic

Logic Design for Mod-4 Counter

RESET

DQ
s1 q1
CLK Q

DQ
s0 q0
Q

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-65 Appendix A: Digital Logic

Example: A Sequence Detector

• Example: Design a machine that outputs a 1 when exactly two of
the last three inputs are 1.
• e.g. input sequence of 011011100 produces an output sequence
of 001111010.
• Assume input is a 1-bit serial line.
• Use D flip-flops and 8-to-1 Multiplexers.
• Start by constructing a state transition diagram (next slide).

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-66 Appendix A: Digital Logic

Sequence Detector State Transition

Diagram 0/0
0/0
• Design a machine that D
outputs a 1 when ex-
actly two of the last B 1/0

three inputs are 1. 0/0 0/0

E
1/0

A 1/1 0/0

0/0
F 1/1
1/0
C 0/1

G
1/0
1/0
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-67 Appendix A: Digital Logic

Sequence Detector State Table

Input X
Present state 0 1

A B/0 C/0
B D/0 E/0
C F/0 G/0
D D/0 E/0
E F/0 G/1
F D/0 E/1
G F/1 G/0

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-68 Appendix A: Digital Logic

Sequence Detector State Assignment

Input and Next state
state at and output at
time t time t+1
s 2 s1 s 0 x s2 s1 s0 z
Input X
0 0 0 0 0 0 1 0
Present state 0 1 0 0 0 1 0 1 0 0
S 2S 1S 0 S 2S 1S 0Z S 2S 1S 0Z
0 0 1 0 0 1 1 0
A: 000 001/0 010/0 0 0 1 1 1 0 0 0
B: 001 011/0 100/0 0 1 0 0 1 0 1 0
0 1 0 1 1 1 0 0
C: 010 101/0 110/0 0 1 1 0 0 1 1 0
D: 011 011/0 100/0 0 1 1 1 1 0 0 0
E: 100 101/0 110/1 1 0 0 0 1 0 1 0
F: 101 011/0 100/1 1 0 0 1 1 1 0 1
G: 110 101/1 110/0 1 0 1 0 0 1 1 0
1 0 1 1 1 0 0 1
(a) 1 1 0 0 1 0 1 1
1 1 0 1 1 1 0 0
1 1 1 0 d d d d
1 1 1 1 d d d d

(b)
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-69 Appendix A: Digital Logic

Sequence Detector Logic Diagram

0 000 x 000 x 000 0 000

x 001 x 001 x 001 0 001
1 010 x 010 x 010 0 010
x 011 x 011 x 011 0 011
D Q D Q D Q Z
1 100 S2 x 100 S1 x 100 S0 x 100
x 101 Q x 101 Q x 101 Q x 101
1 110 x 110 x 110 x 110
0 111 0 111 0 111 0 111

CLK

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-70 Appendix A: Digital Logic

Example: A Vending Machine

Controller
• Example: Design a finite state machine for a vending machine
controller that accepts nickels (5 cents each), dimes (10 cents
each), and quarters (25 cents each). When the value of the money
inserted equals or exceeds twenty cents, the machine vends the
item and returns change if any, and waits for next transaction.
• Implement with PLA and D flip-flops.

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-71 Appendix A: Digital Logic

Vending Machine State Transition

Diagram
1/0 = Dispense/Do not
dispense merchandise
A dime is 1/0 = Return/Do not return
inserted a nickel in change
Q/110 1/0 = Return/Do not
N/100 D/110 return a dime in change
N/000
A B D/000 D
0¢ Q/101 5¢ 15 ¢
Q/111
N/000
D/000 N/000
N = Nickel
Q/111 D = Dime
D/100 Q = Quarter
C
10 ¢
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-72 Appendix A: Digital Logic

Vending Machine State Table and

State Assignment

Input N D Q Input N D Q
x1 x0 x1 x0 x1 x0
P.S. 00 01 10 P.S. 00 01 10
A B/000 C/000 A/110 s 1 s0 s 1 s0 / z 2 z 1 z 0
B C/000 D/000 A/101 A:00 01/000 10/000 00/110
C D/000 A/100 A/111 B:01 10/000 11/000 00/101
D A/100 A/110 B/111 C:10 11/000 00/100 00/111
D:11 00/100 00/110 01/111
(a)
(b)

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-73 Appendix A: Digital Logic

PLA Vending Machine Controller

s1 s0 x1 x0
x1 z2
x0 5×5 z1
PLA z0

Q D
s0 0
(a) CLK
1
Q D
s1 2

P resent N ext
D ispense 5
R eturn nickel
state C oin state R eturn dim e

B ase 10
6
equivalent
s1 s0 x1 x0 s1 s 0 z 2 z 1 z 0
8
0 0 0 0 0 0 1 0 0 0
1 0 0 0 1 1 0 0 0 0
2 0 0 1 0 0 0 1 1 0 9
3 0 0 1 1 d d d d d
4 0 1 0 0 1 0 0 0 0 10
5 0 1 0 1 1 1 0 0 0
6 0 1 1 0 0 0 1 0 1 12
7 0 1 1 1 d d d d d
8 1 0 0 0 1 1 0 0 0
13
9 1 0 0 1 0 0 1 0 0
10 1 0 1 0 0 0 1 1 1
11 1 0 1 1 d d d d d 14
12 1 1 0 0 0 0 1 0 0
13 1 1 0 1 0 0 1 1 0
14 1 1 1 0 0 1 1 1 1
15 1 1 1 1 d d d d d
(b) (c)
s1 s0 z2 z1 z0

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-74 Appendix A: Digital Logic

Moore Counter
• Mealy Model: Outputs are functions of Inputs and Present State.
• Previous FSM designs were Mealy Machines, in which next state
was computed from present state and inputs.
• Moore Model: Outputs are functions of Present State only.
0 00
0 z0 z1 0 x 01 4-to-1
D Q z0
1 1 10 MUX S0
00 01 11 Q

1 1

00
01 4-to-1 z1
D Q
11 10 MUX
10 S1
1 11 Q
0 0

CLK
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-75 Appendix A: Digital Logic

Four-Bit Register
• Makes use of tri-state buffers so that multiple registers can gang
their outputs to common output lines.
D3 D2 D1 D0

D Q D Q D Q D Q
Write (WR)
CLK
Enable (EN)

Q3 Q2 Q1 Q0
WR D3 D2 D1 D0

EN Q3 Q2 Q1 Q0

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-76 Appendix A: Digital Logic

Left-Right
Shift c1

c0

Register Shift left output

D3 D2 D1 D0
Shift right
input

with
Shift right input

Parallel
Read and c0
D Q D Q D Q D Q
Shift right
output

Write c1 CLK
Enable (EN)

Q3 Q2 Q1 Q0

Control Function
c1 c0
Shift right input D3 D2 D1 D0
0 0 No change Shift left output Shift right output
0 1 Shift left c Shift right input
1 0 Shift right c01 Q 3 Q2 Q1 Q 0
1 1 Parallel load

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-77 Appendix A: Digital Logic

Modulo-8 Counter
• Note the use of the T flip-flops, implemented as J-K’s. They are
used to toggle the input of the next flip-flop when its output is 1.

1 J Q 1 J Q 1 J Q
K K K
CLK
Enable (EN)

RESET

Q2 Q1 Q0

CLK

ENABLE Q0
MOD(8) COUNTER
RESET Q2 Q1 Q0 Q1

Q2

Timing Behavior

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring