Professional Documents
Culture Documents
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TRR ENGINEERING COLLEGE
(AFFILIATED TO J.N.T.U HYDERABAD)
Inole (V) Patancheru (M) Medak (Dist)
HYDERABAD
CERTIFICATE
This is to certify that the project work entitled “PC BASED
ROBO” was being submitted by RAMAKRISHNA RAJU.M
(08D15A0409), RAVI CHANDRA REDDY.B (07D11A04A3), SAI
VARMA.A (07D11A0463) SREENIVASULU.S.T (07D11A0472), in
partial fulfillment of the requirement for the award of degree of bachelor
of Technology in Electronics and Communication Engineering from
Jawaharlal Nehru Technology University – Hyderabad. The results
embodied in this project have not been submitted to any other University
or Institution of the award of any Degree or Diploma.
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ACKNOWLEDGEMENT
Our heartfelt thanks to our principal Prof. Dr. ANIL KUMAR for having
provided us the necessary infrastructure required for the successful completion of our
project.
Our sincere thanks to all of the teaching and non – teaching staff for extending
their support and cooperation for the completion of our project.
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A PROJECT REPORT ON
BACHELOR OF TECHNOLOGY
IN
By
COMMUNICATION ENGINEERING
HYDERABAD
2007 - 2011
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TRR ENGINEERING COLLEGE
(AFFILIATED TO J.N.T.U HYDERABAD)
Inole (V) Patancheru (M) Medak (Dist)
HYDERABAD
CERTIFICATE
This is to certify that the project work entitled “PC BASED
ROBO” was being submitted by RAMAKRISHNA RAJU.M
(08D15A0409), in partial fulfillment of the requirement for the award of
degree of bachelor of Technology in Electronics and Communication
Engineering from Jawaharlal Nehru Technology University – Hyderabad.
The results embodied in this project have not been submitted to any other
University or Institution of the award of any Degree or Diploma.
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CONTENTS
ABSTRACT
CHAPTER-1-------------------------------------------------------------------1-2
CHAPTER-II--------------------------------------------------------------------3-7
2.1 MICROCONTROLLER VERSUS MICROPROCESSOR
CHAPTER-
3------------------------------------------------------------------8-22
MICROCONTROLLER PIN CONFIGURATION
3.1 The ATmega8 provides the following prominent features
3.3RESET
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CHAPTER – 4----------------------------------------------------23-25
4.1 POWER SUPPLY DIAGRAM:
4.2 CIRCUIT FEATURES
4.3 BLOCK DIAGRAM
4.4 EXAMPLE CIRCUIT DIAGRAM
CHAPTER-5-----------------------------------------------------26-31
CHAPTER-
6-------------------------------------------------------------32-34
CHAPTER-7------------------------------------------------------35-40
CODING
CHAPTER-8----------------------------------------------------------------
41-41
RESULT
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ACKNOWLEDGEMENT
Our heartfelt thanks to our principal Prof. Dr. ANIL KUMAR for having
provided us the necessary infrastructure required for the successful completion of our
project.
and encouragement.
Our sincere thanks to all of the teaching and non – teaching staff for extending
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ABSTRACT:
A serial peripheral interface (SPI) is an interface that enables the serial (one
bit at a time) exchange of data between two devices, one called a master and the other
called a slave. An SPI operates in full duplex mode. This means that data can be
transferred in both directions at the same time. The SPI is most often employed in
systems for communication between the central processing unit (CPU) and peripheral
devices. It is also possible to connect two microprocessors by means of SPI. The
Block diagram has been depicted below
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CHAPTER-1
Introduction to Embedded Systems
An embedded system is a special-purpose computer system designed to perform
a dedicated function. Unlike a general-purpose computer, such as a personal
computer, an embedded system performs one or a few pre-defined tasks, usually with
very specific requirements, and often includes task-specific hardware and mechanical
parts not usually found in a general-purpose computer. Since the system is dedicated
to specific tasks, design engineers can optimize it, reducing the size and cost of the
product. Embedded systems are often mass-produced, benefiting from economies of
scale.
Physically, embedded systems range from portable devices such as digital
watches and MP3 players, to large stationary installations like traffic lights, factory
controllers, or the systems controlling nuclear power plants. In terms of complexity
embedded systems run from simple, with a single microcontroller chip, to very
complex with multiple units, peripherals and networks mounted inside a large chassis
or enclosure.
Mobile phones or handheld computers share some elements with embedded
systems, such as the operating systems and microprocessors which power them, but
are not truly embedded systems themselves because they tend to be more general
purpose, allowing different applications to be loaded and peripherals to be connected.
Network managers will need to manage more and more embedded systems
devices, ranging from printers to scanners, to handheld computing devices, to cell
phones. All of these have a need to connect with other devices, either directly or
through a wireless or direct-connect network. Most will have custom operating
systems or variations of existing operating systems (e.g., Microsoft Windows CE).
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It's easy to picture nearly every electronic device as having an embedded
system. For example, refrigerators, washing machines, and even coffee brewers will
benefit in some way from embedded systems. A critical feature of an embedded
system is its ability to communicate, so embedded systems support Ethernet,
Bluetooth (wireless), infrared, or other technologies.
If the weather station is connected to the Internet, it may have its own IP
address and, ideally, will provide information to anyone that accesses the IP address.
In this sense, the weather station is acting as a mini-Web server. In fact, many
embedded systems are basically Web servers on a chip. The chips contain HTTP and
HTML functions, and custom applications appropriate for the environment in which
the chip will be used.
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CHAPTER-2
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inside it performs one task only; namely getting the data and printing it. Contrast this
with a Pentium based PC. A PC can be used for any number of applications such as
word processor, print-server, bank teller terminal, Video game, network server, or
Internet terminal. Software for a variety of applications can be loaded and run. Of
course the reason a pc can perform myriad tasks is that it has RAM memory and an
operating system that loads the application software into RAM memory and lets the
CPU run it.
In an Embedded system, there is only one application software that is typically
burned into ROM. An x86 PC contains or is connected to various embedded products
such as keyboard, printer, modem, disk controller, sound card, CD-ROM drives,
mouse, and so on. Each one of these peripherals has a Microcontroller inside it that
performs only one task. For example, inside every mouse there is a Microcontroller to
perform the task of finding the mouse position and sending it to the PC. Table 1-1
lists some embedded products.
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system will usually include a A if it supports Asynchronous communications, and a S
if it supports Synchronous communications. Both forms are described below.
Synchronous serial transmission requires that the sender and receiver share a
clock with one another, or that the sender provide a strobe or other timing signal so
that the receiver knows when to “read” the next bit of the data. In most forms of serial
Synchronous communication, if there is no data available at a given instant to
transmit, a fill character must be sent instead so that data is always being transmitted.
Synchronous communication is usually more efficient because only data bits are
transmitted between sender and receiver, and synchronous communication can be
more costly if extra wiring and circuits are required to share a clock signal between
the sender and receiver.
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The Start Bit is used to alert the receiver that a word of data is about to be sent, and to
force the clock in the receiver into synchronization with the clock in the transmitter.
These two clocks must be accurate enough to not have the frequency drift by more
than 10% during the transmission of the remaining bits in the word. (This requirement
was set in the days of mechanical teleprinters and is easily met by modern electronic
equipment.)
After the Start Bit, the individual bits of the word of data are sent, with the
Least Significant Bit (LSB) being sent first. Each bit in the transmission is transmitted
for exactly the same amount of time as all of the other bits, and the receiver “looks” at
the wire at approximately halfway through the period assigned to each bit to
determine if the bit is a 1 or a 0. For example, if it takes two seconds to send each bit,
the receiver will examine the signal to determine if it is a 1 or a 0 after one second has
passed, then it will wait two seconds and then examine the value of the next bit, and
so on.
The sender does not know when the receiver has “looked” at the value of the
bit. The sender only knows when the clock says to begin transmitting the next bit of
the word.When the entire data word has been sent, the transmitter may add a Parity
Bit that the transmitter generates. The Parity Bit may be used by the receiver to
perform simple error checking. Then at least one Stop Bit is sent by the transmitter.
When the receiver has received all of the bits in the data word, it may check
for the Parity Bits (both sender and receiver must agree on whether a Parity Bit is to
be used), and then the receiver looks for a Stop Bit. If the Stop Bit does not appear
when it is supposed to, the UART considers the entire word to be garbled and will
report a Framing Error to the host processor when the data word is read. The usual
cause of a Framing Error is that the sender and receiver clocks were not running at the
same speed, or that the signal was interrupted.Regardless of whether the data was
received correctly or not, the UART automatically discards the Start, Parity and Stop
bits. If the sender and receiver are configured identically, these bits are not passed to
the host.If another word is ready for transmission, the Start Bit for the new word can
be sent as soon as the Stop Bit for the previous word has been sent.
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Because asynchronous data is “self synchronizing”, if there is no data to
transmit, the transmission line can be idle.
CHAPTER-3
MICROCONTROLLER PIN CONFIGURATION
ATmega8
The ATmega8 is a low-power CMOS 8-bit microcontroller, based
on the AVR enhanced RISC architecture. By executing powerful instructions in a
single clock cycle, the ATmega8 achieves throughputs approaching 1 MIPS per MHz
allowing the system designer to optimize power consumption versus processing
speed.
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in one clock cycle. The resulting architecture is more code efficient while achieving
throughputs up to ten times faster than conventional CISC microcontrollers.
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6-channel ADC in PDIP package
Six Channels 10-bit Accuracy
Byte-oriented Two-wire Serial Interface
Programmable Serial USART
Master/Slave SPI Serial Interface
Programmable Watchdog Timer with Separate On-chip Oscillator
On-chip Analog Comparator
• Special Microcontroller Features
Power-on Reset and Programmable Brown-out Detection
Internal Calibrated RC Oscillator
External and Internal Interrupt Sources
Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and
Standby
• I/O and Packages
23 Programmable I/O Lines
28-lead PDIP, 32-lead TQFP, and 32-pad QFN/MLF
• Operating Voltages
2.7 - 5.5V (ATmega8L)
4.5 - 5.5V (ATmega8)
• Speed Grades
0 - 8 MHz (ATmega8L)
0 - 16 MHz (ATmega8)
• Power Consumption at 4 Mhz, 3V, 25°C
Active: 3.6 mA
Idle Mode: 1.0 mA
Power-down Mode: 0.5 μA
The Idle mode stops the CPU while allowing the USART, Two-wire interface,
A/D Converter, SRAM, Timer/Counters, SPI port, and interrupt system to continue
functioning. The Power-down mode saves the register contents but freezes the
Oscillator, disabling all other chip functions until the next External Interrupt or
Hardware Reset.
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In Power-save mode, the Asynchronous Timer continues to run, allowing the
user to maintain a timer base while the rest of the device is sleeping. The ADC Noise
Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and
ADC, to minimize switching noise during ADC conversions.
By combining an 8-bit RISC CPU with In-System Self-Programmable Flash
on a monolithic chip, the Atmel ATmega8 is a powerful microcontroller that provides
a highly flexible and cost-effective solution to many embedded control applications.
3.2 Pin Descriptions:
VCC- Digital supply voltage.
GND- Ground.
Port B (PB7..PB0) XTAL1/XTAL2/TOSC1/TOSC2
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors
(selected for each bit). The Port B output buffers have symmetrical drive
characteristics with both high sink and source capability. As inputs, Port B pins that
are externally pulled low will source current if the pull-up resistors are activated. The
Port B pins are tri-stated when a reset condition becomes active, even if the clock is
not running. Depending on the clock selection fuse settings, PB6 can be used as input
to the inverting Oscillator amplifier and input to the internal clock operating circuit.
Depending on the clock selection fuse settings, PB7 can be used as output from the
inverting Oscillator amplifier. If the Internal Calibrated RC Oscillator is used as chip
clock source, PB7..6 is used as TOSC2..1 input for the Asynchronous Timer/Counter2
if the AS2 bit in ASSR is set.
Port C (PC5..PC0)
Port C is an 7-bit bi-directional I/O port with internal pull-up resistors
(selected for each bit). The Port C output buffers have symmetrical drive
characteristics with both high sink and source capability. As inputs, Port C pins that
are externally pulled low will source current if the pull-up resistors are activated. The
Port C pins are tri-stated when a reset condition becomes active, even if the clock is
not running.
PC6/RESET
If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that
the electrical characteristics of PC6 differ from those of the other pins of Port C. If the
RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this
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pin for longer than the minimum pulse length will generate a Reset, even if the clock
is not running
Port D (PD7..PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors
(selected for each bit). The Port D output buffers have symmetrical drive
characteristics with both high sink and source capability. As inputs, Port D pins that
are externally pulled low will source current if the pull-up resistors are activated. The
Port D pins are tri-stated when a reset condition becomes active, even if the clock is
not running.
3.3RESET
Reset input. A low level on this pin for longer than the minimum pulse length
will generate a reset, even if the clock is not running. Shorter pulses are not
guaranteed to generate a reset.
AVCC
AVCC is the supply voltage pin for the A/D Converter, Port C (3..0), and
ADC (7..6). It should be externally connected to VCC, even if the ADC is not used.
If the ADC is used, it should be connected to VCC through a low-pass filter. Note that
Port C (5..4) use digital supply voltage, VCC.
AREF
AREF is the analog reference pin for the A/D Converter.
ADC7..6 (TQFP and QFN/MLF Package Only)
In the TQFP and QFN/MLF package, ADC7..6 serve as analog inputs to the
A/D converter. These pins are powered from the analog supply and serve as 10-bit
ADC channels.
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Fig 3.3.1 BLOCK DIAGRAM OF AT mega 8
The ATmega8 AVR is supported with a full suite of program and system
development tools including: C compilers, macro assemblers, program
debugger/simulators, in-circuit emulators, and evaluation kits.
A flexible interrupt module has its control registers in the I/O space with an
additional global interrupt enable bit in the Status Register. All interrupts have a
separate interrupt vector in the interrupt vector table. The interrupts have priority in
accordance with their interrupt vector position. The lower the interrupt vector address,
the higher the priority. The I/O Memory can be accessed directly, or as the Data
Space locations following those of the Register File, 20h - 5Fh
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3.4 I/O PORTS
All AVR ports have true Read-Modify-Write functionality when used as general
digital I/O ports. This means that the direction of one port pin can be changed without
unintentionally changing the direction of any other pin with the SBI and CBI
instructions. The same applies when changing drive value (if configured as output) or
enabling/disabling of pull-up resistors (if configured as input). Each output buffer has
symmetrical drive characteristics with both high sink and source capability. The pin
driver is strong enough to drive LED displays directly. All port pins have individually
selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins
have protection diodes to both VCC and Ground.
All registers and bit references in this section are written in general form.
Three I/O memory address locations are allocated for each port, one each for the Data
Register – PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx.
The Port Input Pins I/O location is read only, while the Data Register and the Data
Direction Register are read/write. In addition, the Pull-up Disable – PUD bit in
SFIOR disables the pull-up function for all pins in all ports when set.
Most port pins are multiplexed with alternate functions for the peripheral
features on the device. Enabling the alternate function of some of the port pins does
not affect the use of the other pins in the port as general digital I/O.
3.5 Ports as general purpose I/O:
The ports are bi-directional I/O ports with optional internal pull-ups. Each port pin
consists of three register bits: DDxn, PORTxn, and PINxn. The DDxn bits are
accessed at the DDRx I/O address, the PORTxn bits at the PORTx I/O address, and
the PINxn bits at the PINxI/O address. The DDxn bit in the DDRx Register selects the
direction of this pin. If DDxn is written logic one, Pxn is configured as an output pin.
If DDxn is written logic zero, Pxn is configured as an input pin. If PORTxn is written
logic one when the pin is configured as an input pin, the pull-up resistor is activated.
To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has
to be configured as an output pin. The port pins are tri-stated when a reset condition
becomes active, even if no clocks are running. If PORTxn is written logic one when
the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is
written logic zero when the pin is configured as an output pin, the port pin is driven
low (zero). Normally, the pull-up enabled state is fully acceptable, as a high-
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impedance environment will not notice the difference between a strong high driver
and a pull-up. If this is not the case, the PUD bit in the SFIOR Register can be set to
disable all pull-ups in all ports.
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constitute a synchronizer. This is needed to avoid meta stability if the physical pin
changes value near the edge of the internal clock, but it also introduces a delay. The
maximum and minimum propagation delays are denoted tpd, max and tpd, min
respectively.
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Fig 3.5.3 Timing diagram when Reading an
3.6 8-bit Timer/Counter Register Description
Timer/Counter Control Register – TCCR2
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table 3.6.2 TCCR modes
• Bit 5:4 – COM21:0: Compare Match Output Mode
These bits control the Output Compare Pin (OC2) behavior. If one or both of the
COM21:0 bits
are set, the OC2 output overrides the normal port functionality of the I/O pin it is
connected to.
However, note that the Data Direction Register (DDR) bit corresponding to OC2 pin
must be set
in order to enable the output driver. When OC2 is connected to the pin, the function of
the COM21:0 bits depends on the WGM21:0 bit setting.
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Fig 3.6.4 OCR2
The Output Compare Register contains an 8-bit value that is continuously
compared with the counter value (TCNT2). A match can be used to generate an
Output Compare interrupt, or togenerate a waveform output on the OC2 pin.
3.7 8-bit Timer/Counter
Timer/Counter0 is a general purpose, single channel, 8-bit Timer/Counter module.
The main features are:
• Single Channel Counter
• Frequency Generator
• External Event Counter
• 10-bit Clock Prescaler
Overview
A simplified block diagram of the 8-bit Timer/Counter is shown in Fig 3.8.1 . For
the actual placement of I/O pinsCPU accessible I/O Registers, including I/O bits and
I/O pins, are shown in bold. The device-specific I/O Register and bit locations are
listed in the “8-bit Timer/Counter Register Description”.
Registers
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The Timer/Counter (TCNT0) is an 8-bit register. Interrupt request (abbreviated to Int.
Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR).
All interrupts are individually masked with the Timer Interrupt Mask Register
(TIMSK). TIFR and TIMSK are not shown in the figure since these registers are
shared by other timer units. The Timer/Counter can be clocked internally or via the
prescaler, or by an external clock source on the T0 pin. The Clock Select logic block
controls which clock source and edge the Timer/Counter uses to increment its value.
The Timer/Counter is inactive when no clock source is selected. The output from the
clock select logic is referred to as the timer clock (clkT0).
Definitions
Many register and bit references in this document are written in general form. A
lower case “n”
replaces the Timer/Counter number, in this case 0. However, when using the register
or bit
defines in a program, the precise form must be used i.e. TCNT0 for accessing
Timer/Counter0
counter value and so on.
Timer/Counter Clock Sources
The Timer/Counter can be clocked by an internal or an external clock source. The
clock source
is selected by the clock select logic which is controlled by the clock select (CS02:0)
bits located
in the Timer/Counter Control Register (TCCR0).
Counter Unit
.
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Fig 3.7.2 Counter Unit Block Diagram
Operation
The counting direction is always up (incrementing), and no counter clear is
performed. The counter simply overruns when it passes its maximum 8-bit value
(MAX = 0xFF) and then restarts from the bottom (0x00). In normal operation the
Timer/Counter Overflow Flag (TOV0) will be set in the same timer clock cycle as the
TCNT0 becomes zero. The TOV0 Flag in this case behaves like a ninth bit, except
that it is only set, not cleared. However, combined with the timer overflow interrupt
that automatically clears the TOV0 Flag, the timer resolution can be increased by
software. A new counter value can be written anytime.
Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore
shown as a
clock enable signal in the following figures. The figures include information on when
Interrupt
Flags are set. Figure contains timing data for basic Timer/Counter operation. The
figure
shows the count sequence close to the MAX value.
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Fig 3.7.3 timing diagrams 1
CHAPTER – 4
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4.1 POWER SUPPLY DIAGRAM:
A variable regulated power supply, also called a variable bench power
supply, is one where you can continuously adjust the output voltage to your
requirements. Varying the output of the power supply is the recommended way
to test a project after having double checked parts placement against circuit
drawings and the parts placement guide.
This type of regulation is ideal for having a simple variable bench power
supply. Actually this is quite important because one of the first projects a
hobbyist should undertake is the construction of a variable regulated power
supply. While a dedicated supply is quite handy e.g. 5V or 12V, it's much
handier to have a variable supply on hand, especially for testing.
Most digital logic circuits and processors need a 5 volt power supply. To
use these parts we need to build a regulated 5 volt source. Usually you start
with an unregulated power To make a 5 volt power supply, we use a LM7805
voltage regulator IC (Integrated Circuit). The IC is shown below.
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• Brief description of operation: Gives out well regulated +5V output,
output current capability of 100 mA
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4.4 EXAMPLE CIRCUIT DIAGRAM
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Chapter-5
5.1 Circuit Description and operation
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SPI bus: single master and single slave
5.2 Interface
The SPI bus specifies four logic signals:
The SDI/SDO (DI/DO, SI/SO) convention requires that SDO on the master be
connected to SDI on the slave, and vice-versa. Chip select polarity is rarely active
high, although some notations (such as SS or CS instead of nSS or nCS) suggest
otherwise.
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5.3 Data transmission
During each SPI clock cycle, a full duplex data transmission occurs:
the master sends a bit on the MOSI line; the slave reads it from that same line
the slave sends a bit on the MISO line; the master reads it from that same line
Not all transmissions require all four of these operations to be meaningful but they do
happen.
Transmissions normally involve two shift registers of some given word size, such as
eight bits, one in the master and one in the slave; they are connected in a ring. Data
are usually shifted out with the most significant bit first, while shifting a new least
significant bit into the same register. After that register has been shifted out, the
master and slave have exchanged register values. Then each device takes that value
and does something with it, such as writing it to memory. If there is more data to
exchange, the shift registers are loaded with new data and the process repeats.
Transmissions may involve any number of clock cycles. When there are no more data
to be transmitted, the master stops toggling its clock. Normally, it then deselects the
slave.
Transmissions often consist of 8-bit words, and a master can initiate multiple such
transmissions if it wishes/needs. However, other word sizes are also common, such as
16-bit words for touchscreen controllers or audio codecs, like the TSC2101
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from Texas Instruments; or 12-bit words for many digital-to-analog or analog-to-
digital converters.
Every slave on the bus that hasn't been activated using its slave select line must
disregard the input clock and MOSI signals, and must not drive MISO. The master
must select only one slave at a time.
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Not limited to 8-bit words
Arbitrary choice of message size, content, and purpose
Extremely simple hardware interfacing
Typically lower power requirements than I²C or SMBus due to less circuitry
(including pullups)
No arbitration or associated failure modes
Slaves use the master's clock, and don't need precision oscillators
Slaves don't need a unique address -- unlike I²C or GPIB or SCSI
Transceivers are not needed
Uses only four pins on IC packages, and wires in board layouts or connectors,
much less than parallel interfaces
At most one "unique" bus signal per device (chip select); all others are shared
Requires more pins on IC packages than I²C, even in the "3-Wire" variant
No in-band addressing; out-of-band chip select signals are required on shared
buses
No hardware flow control by the slave (but the master can delay the next clock
edge to slow the transfer rate)
No hardware slave acknowledgment (the master could be "talking" to nothing
and not know it)
Supports only one master device
No error-checking protocol is defined
Generally prone to noise spikes causing faulty communication
Without a formal standard, validating conformance is not possible
Only handles short distances compared to RS-232, RS-485, or CAN-bus
5.9 Applications:
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Control devices: audio codecs , digital potentiometers, DAC
Camera lenses: Canon EF lens mount
Communications: Ethernet, USB, USART, CAN, IEEE
802.15.4, IEEE 802.11, handheld video games
Memory: flash and EEPROM
Real-time clocks
LCD displays, sometimes even for managing image data
Any MMC or SD card (including SDIO varia
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Chapter-6
Test procedure for EMXcore SBC V.1
Objective: to test two SBC01 V1 boards simultaneously for operation
of all ports, and USART.
1. Equipment required
PC with serial port and RS232 cable
Multimeter
2 Nos wall socket adapters for 5V DC
LED strips for testing boards
Serial port cable..male to male 9 pin D connectors
b. Now a window pops up , click on “port” on the menu bar and select the
com port to which the programmers cable is being connected.
d. Now a window opens asking for a hex file to be selected. Select the slave
file present in the test folder named as “slave”.
e. Now connect the programmers 6Pin connecter to the slave board and insert
the connector in such a way that the boss faces the other side of the board..
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Now check eMxSBC01 V.1 boards in the following way.
Slave board
f. Connect 5V DC power supply (adapter) at P1 (Molex connector) and
check voltage at test point 5V with respect to Gd test point. Note voltage
in table 1. It should be between 4.6V and 5.4V
j. Check the temperatures of U1 and U2. If they get hot, switch off power
supply. Otherwise, proceed as follows.
l. Now after the program has been dumped. Switch “OFF” the board.
m. Connect the test jigs to the four ports and also connect one end of the test
USART cable to the slaves com port.
Master board
n. For master programming start the procedure from point 4 and instead of
selecting “slave” file select “master” file from the test folder.
o. Now after the program has been dumped. Switch “OFF” the board.
p. Connect the test jigs to the four ports and also connect the other end of the
test USART cable to the masters com port.
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OBSERVATIONS
a. Now switch “ON” the two boards. Push the reset button of the slave and
then push the reset button of the master.
b. Now in the master the LED’s should glow in a sequential manner. From
port B to port D.
c. If all the LED’s in the master had glowed. Now check the slave to see if
the LED’s are glowing in a similar manner.
d. After all the LED’s in the slave had been glowed then check the master
again to see the LED’s glowing again.
e. If point ‘b’ is not seen then master board has some trouble.
f. If point ‘c’ does not occur then the slave board has some trouble
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Chapter-7
CODING
#include "UART_routines.h"
#include "SPI_routines.h"
void port_init(void)
{
PORTC = 0x00;
DDRC = 0x00;
PORTD = 0x00;
DDRD = 0xFE;
}
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//call this routine to initialize all peripherals
void init_devices(void)
{
cli();
port_init();
uart0_init();
spi_init();
SPI_master_init();
SPI_slave_init( );
sei();
}
//*************************** MAIN *******************************//
int main(void)
{
unsigned char data;
init_devices();
transmitString("Please Enter 1 For MAster 2 For Slave Mode
\n\r");
data=receiveByte();
transmitByte(data);
// SPI_transmit(rx_data);
// transmitByte(SPI_receive());
switch(data)
{
case'1':transmitString("SPI MASTER:\n\r");
while(1)
{
//transmitString("Please Enter Data \n\r");
data=receiveByte();
transmitByte(data);
SPI_transmit(data);
//transmitByte(ack);
}
break;
case'2':transmitString("SPI SLAVE MODE:\n\r");
while(1)
{
data=receiveByte();
transmitByte(data);
SPI_transmit(SPI_receive());
}
break;
}
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}
//**************************************************************
//******** FUNCTIONS FOR SERIAL COMMUNICATION USING UART
*******
//**************************************************************
//Controller: ATmega32 (8 Mhz internal)
//Compiler: AVR-GCC
//**************************************************
// ***** SOURCE FILE : UART_routines.c ******
//**************************************************
#include "UART_routines.h"
#include <avr/io.h>
#include <avr/pgmspace.h>
//UART0 initialize
// desired baud rate: 9600
// actual: baud rate:9600 (0.2%)
// char size: 8 bit
// parity: Disabled
void uart0_init(void)
{
UCSRB = 0x00; //disable while setting baud rate
UCSRA = 0x00;
UCSRC = (1 << URSEL) | 0x06;
UBRRL = 0x33; //set baud rate lo
UBRRH = 0x00; //set baud rate hi
UCSRB = 0x18;
}
//**************************************************
//Function to receive a single byte
//*************************************************
unsigned char receiveByte( void )
{
unsigned char data, status;
status = UCSRA;
data = UDR;
return(data);
}
//***************************************************
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//Function to transmit a single byte
//***************************************************
void transmitByte( unsigned char data )
{
while ( !(UCSRA & (1<<UDRE)) )
; /* Wait for empty transmit
buffer */
UDR = data; /* Start transmition */
}
//***************************************************
//Function to transmit hex format data
//first argument indicates type: CHAR, INT or LONG
//Second argument is the data to be displayed
//***************************************************
/*void transmitHex( unsigned char dataType, unsigned long data )
{
unsigned char count, i, temp;
unsigned char dataString[] = "0x ";
data = data/16;
}
transmitString (dataString);
}
*/
//***************************************************
//Function to transmit a string in Flash
//***************************************************
void transmitString_F(char* string)
{
while (pgm_read_byte(&(*string)))
transmitByte(pgm_read_byte(&(*string++)));
}
//***************************************************
//Function to transmit a string in RAM
//***************************************************
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void transmitString( char* string)
{
while (*string)
transmitByte(*string++);
}
//**************************************************************
//******** FUNCTIONS FOR SERIAL COMMUNICATION USING UART
*******
//**************************************************************
//Controller: ATmega32 (8 Mhz internal)
//Compiler: AVR-G
//**************************************************************
//**************************************************
// ***** HEADER FILE : UART_routines.h ******
//**************************************************
#ifndef _UART_ROUTINES_H_
#define _UART_ROUTINES_H_
#define CHAR 0
#define INT 1
#define LONG 2
void uart0_init(void);
#define TX_NEWLINE {transmitByte(0x0d); transmitByte(0x0a);}
#endif
//**************************************************************
// ****** FUNCTIONS FOR SPI COMMUNICATION *******
//**************************************************************
//**************************************************************
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//**************************************************
#ifndef _SPI_ROUTINES_H_
#define _SPI_ROUTINES_H_
void SPI_slave_init(void );
void spi_init(void);
unsigned char SPI_transmit(unsigned char);
unsigned char SPI_receive(void);
#endif
//**************************************************************
// ****** FUNCTIONS FOR SPI COMMUNICATION *******
//**************************************************************
//**************************************************************
//**************************************************
// ***** SOURCE FILE : SPI_routines.c ******
//**************************************************
#include <avr/io.h>
#include "SPI_routines.h"
//SPI initialize
//clock rate: 125Khz
void spi_init(void)
{
SPCR = 0x52; //setup SPI: Master mode, MSB first, SCK phase low,
SCK idle low
SPSR = 0x00;
}
void SPI_master_init(void )
{
PORTB=0x00;
DDRB=0x2C;
}
void SPI_slave_init(void )
{
PORTB=0x00;
DDRB=0x10;
}
unsigned char SPI_transmit(unsigned char data)
{
// Start transmission
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SPDR = data;
return(data);
}
SPDR = 0xff;
while(!(SPSR & (1<<SPIF)));
data = SPDR;
CHAPTER-8
RESULT:
We finally achieved the aim of the project, which is SPI communication
between two microcontrollers
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