Ic Lab Rec

Division of Computing Sciences
R 407 – Integrated Circuits Lab Rajagiri School of Engineering and

Technology, Kochi - 39
EXPERIMENT NO: 1
DATE: 20/2/06
FAMILIARISATION OF DIGITAL IC
INTRODUCTION
Integrated Circuit is a silicon chip containing an electric circuit made up of components such
as transistors, diodes, resistors and capacitors. Integrated circuits are smaller, faster and more
efficient that the individual circuits used in older computers. Integrated circuits are often
classified according to the number of transistors and other electronic components they
contain, including SSI, MSI, LSI, VLSI, and ULSI. . Integrated circuits are fabricated in a
layer process which includes imaging, deposition, and etching. The earliest integrated circuits
were packaged in ceramic flat packs, which continued to be used by the military for their
reliability and small size for many years.
Classification of IC according to the number of transistors and other electronic components

are as follows:
1. SSI (small-scale integration): Up to 100 electronic components per chip.

2. MSI (medium-scale integration): From 100 to 3,000 electronic components per chip.
3. LSI (large-scale integration): From 3,000 to 100,000 electronic components per chip.
4. VLSI (very large-scale integration): From 100,000 to 1,000,000 electronic
components per chip.
5. ULSI (ultra large-scale integration): More than 1 million electronic components per
chip.
Classifications of IC according to their mode of operation are as follows:
1. Digital or Non Linear: Operation which contains two discrete values or levels. One of
them is called low and the other is called high. It will always be in one of these two
levels. This circuit is called digital circuit.
2. Analog or Linear: This mode of operation has signals which are continuous and can
have any value in a limited range. This circuit is called analog circuit.
There are two main advantages of ICs over discrete circuits
1. Cost.
2. Performance.
The cost is low because the chips, with all their components, are printed as a unit by
photolithography and not constructed a transistor at a time. Chip areas range from a few
square mm to around 250 mm2, with up to 1 million transistors per mm2.
PROBLEM DEFINITION
To familiarize with logic gate IC package and to verify the truth table of the logic gates.
© University Register No: 91508 1
COMPONENTS REQUIRED
COMPONENTS SPECIFICATION QUANTITY

IC 7400 1
7402 1
7424 1
7408 1
7432 1
7486 1
LED 1
Resistor 330Ω 1
THEORETICAL BACKGROUND
LOGIC GATES
In digital electronics, a gate is a logic circuit with one output and one or more input. Logic
gates are available as integrated circuit.
In a digital system there are only few basic operations performed. These basic operations are:
AND GATE
The AND gate performs logical multiplication. The output will be high only when all the
inputs are high. For a two input AND gate, the possible number of input combination is four.
Mathematically, AND gate operation can be expressed as:
Y= A.B.C………N.
U1A
Symbol
Where A, B, C………, N are input variables and Y is an output variable.

7408 is the digital IC in TTL and contains four AND.
OR GATE
The OR gate performs logical addition. Its output goes high if any of its inputs or both its
inputs is high. Mathematically, it can be expressed as:
Y=A+B+C+……..+N.
U1A
Symbol
Where A, B, C, ………, N are input variables and Y is the output variable.

7432 is a quad two input OR gate.
NOT GATE
The NOT gate performs inversion. It has one input and one output. The logical level is
changed to the opposite level. Mathematically, it can be expressed as:
Y=NOT A
Y=A’
IC 7404 is hex invertors.
NAND GATE
The NOT-AND operation is called a NAND gate. It is a NOT gate following an AND gate.
Its output will be low if all the inputs are in high state.
Mathematically, it can be expressed as:
Y= (A.B.C…….N)’
U1A
Symbol
7400 IC is a quad two input NAND gate.
NOR GATE
The NOT-OR operation is called a NOR gate. It is a NOT gate following an OR gate. Its
output will be low if any of its input is in high state.
Mathematically, it can be expressed as :
Y= (A+B+C+…..+N)’
U1A
Symbol
7402 IC is a quad two input NOR gate.
XOR GATE
XOR gate is called a EXCLUSIVE OR gate. It is not a basic gate but is a combination of
basic gates- AND, OR and NOT gate. Its output will be high if and only if one input is in
high state.
Mathematically, it is expressed as:
Y=A ex-OR B.
U1A
Symbol
7486 is a quad two input XOR gate.
PROCEDURE
Test the components and IC packages using a digital IC tester. Also check whether all the
connecting wires are in good condition using a multimeter. Verify the dual in line package
(DIP) pin out of the IC before feeding the input. Set up the circuits and observe the outputs.
Enter the input and output states in truth table corresponding to input combination.
CIRCUIT DIAGRAM

NAND GATE
NOT GATE
AND GATE

OR GATE
XOR GATE
OBSERVATION
AND GATE (7408)
A B Y
0 0 0
0 1 0
1 0 0
1 1 1
OR GATE (7432)
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
NOR GATE (7402)
A B Y

0 0 1
0 1 0
1 0 0
1 1 0
NAND GATE (7400)
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
XOR GATE (7486)
A B Y
0 0 0
0 1 1
1 0 1
1 1 0
NOT GATE (7404)
A Y
0 1
1 0
RESULT
The function of all logic gates were studied using IC’s and result were verified using truth
table.
CONCLUSION
APPLICATION
An IC can function as an amplifier, oscillator, timer, counter, computer memory, or

microprocessor. Modern computing, communications, manufacturing and transport systems,
including the Internet, all depend on the existence of integrated circuits. They are the
fundamental building blocks of digital sysytem.

Experiment no: 2
Date:6/3/06
REALISATION OF ALL GATES USING NAND GATE
INTRODUCTION
LOGIC GATES
A logic gate is an elementary building block of a digital circuit. Most logic gates have two
inputs and one output. At any given moment, every terminal is in one of the two binary
conditions low (0) or high (1), represented by different voltage levels. The logic state of a
terminal can, and generally does, change often, as the circuit processes data. In most logic
gates, the low state is approximately zero volts (0 V), while the high state is approximately
five volts positive (+5 V).
The three types of essential logic gate are the AND, the OR and the NOT gate. With these
three, any conceivable boolean equation can be implemented. However, for convenience, the
derived types NAND, NOR, XOR and XNOR are also used, which often use fewer circuit
elements for a given equation than an implementation based solely on AND, OR and NOT
would do. In fact the NAND has the lowest component count of any gate apart from NOT
when implemented using modern semiconductor techniques, and since a NAND can
implement both a NOT and, by application of De Morgan's Law, an OR function, this single
type can effectively replace AND, OR and NOT, making it the only type of gate that is
needed in a real system. Programmable logic arrays will very often contain nothing but
NAND gates to simplify their internal design.
7400 NAND gate IC.

PROBLEM DEFINITION
To realize all gates using universal gates, NAND gates.
COMPONENTS REQUIRED
COMPONENETS SPECIFICATION QUANTITY

NANDgate IC 7400 quad 2 input 1
Led 1
Resisitor 330Ω 1
DC power supply 0-30v 1
The term universal refers to property of a gate that permits any logic to be implemented by
that gate or a combination of gates of that kind. NAND and NOR gates are universal gates.
All the basic gates, AND, OR, NOT gates and derived gates, XOR, NOR gates can be
obtained from universal gates.
The NOT-AND operation is called a NAND gate. It is a NOT gate following an AND gate.
Its output will be low if all the inputs are in high state.
Mathematically, it can be expressed as:
Y= (A.B.C…….N)’
U1A
Symbol
7400 IC is a quad two input NAND gate.

1. NOT gate from NAND gate:
Y=(A . A)’ = A’
2. AND gate from NAND gate:
Y=((A . B)’)’ = A . B
3. OR gate from NAND gate:
Y=( (A)’ . (B)’ )’ = A+B
4. NOR gate from NAND gate:
Y= (( (A)’ . (B)’ )’)’ = (A+B)’
5. XOR gate from NAND gate:
Y=(( A. (B)’)’ .(( A)’.B)’)’ = A B’+A’B

PROCEDURE
Test all the components using a digital IC tester. Also check whether all the connecting wires
are in good condition using a multimeter. Verify the dual in line package (DIP) pin out of the
IC before feeding the input. Set up the circuits. Use all combinations of NAND gate to
implement AND, OR, NOR, NOT, XOR operation. Enter the input and output states in truth
table corresponding to input combination.
CIRCIUT DIAGRAM

OBSERVATION
AND GATE (7408)
A B Y
0 0 0
0 1 0
1 0 0
1 1 1
OR GATE (7432)
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
NOR GATE (7402)
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
XOR GATE (7486)
A B Y
0 0 0
0 1 1
1 0 1
1 1 0
NOT GATE (7404)
A Y
0 1
1 0
RESULT
.
Realization of all gates using NAND gates was performed and the results were verified.
CONCLUSION
APPLICATION
Logic circuit is used in planes, ships, mobiles and computers. Logic circuits include such
devices as multiplexers, registers, ALUs, and computer memory, all the way up through
complete microprocessors which can contain more than a million gates.

Experiment No:3
Date:27/2/06
HALF AND FULL ADDERS

INTRODUCTION
A combinational circuit consists of logic gates whose output at any time is determined from
the present combination of inputs without regards to previous input. It performs a specific
information processing operation fully specified logically by a set of Boolean function. It
consists of input variable, logic gates and output variables. The logic circuit accepts signals
from the input and generates signals to the outputs. This process transforms binary
information from the given input to the required output data.
For n input variables, there are 2n possible combinations of input values. For each of the
input combination, there is one and only one possible output combination. Each output
function is expressed in terms of the n input variable.
Adders are examples of combinational circuit.
PROBLEM DEFINITION
To design and setup half adders and full adders using EXOR gates and NAND gates.
COMPONENETS REQUIRED

IC 7400 quad 2input NAND 1
7486 quad 2input XOR 1
Led 1
Resistor 330Ω 1
The most basic arithmetic operation is the addition of two binary numbers.
HALF ADDER
The simplest binary adder is called a half adder. Half adder has two input bits and two output
bits. The input variable designates the augend and the addend bits. One output is sum and
other is carry. They are represented by S & C. It is necessary to have two output variable
because the result may consist of two binary digits. The carry output is 0 unless both inputs
are 1. the s output represent the least significant bit of the sum.
S=A’B+AB’.
C= A.B.
A half adder has no provision to add a carry from lower order bits when binary numbers are
added.
FULL ADDER
A full adder is a combinational circuit that forms the arithmetic sum of three input bits. It
consists of three inputs and two outputs. Two of the input variables, represent the two
significant bits to be added. The third input, represents the carry from the previous lower
significant position. Two outputs are necessary because the arithmetic sum of three binary
digits ranges in value from 0 to3 and binary 2 or 3 requires two bits. The two outputs are
designated as S and C. The binary variable S gives the value of the least significant bit of the
sum. The binary variable C gives the output carry.
With three inputs, eight input combination are possible. When all the inputs are 0, then output
is 0. The S is equal to 1 when only one input is equal to 1or all the three inputs are equal to 1.
The C output has a carry of 1 if two or three inputs are equal to 1.
S=A’B’C+A’BC’+AB’C’+ABC.
C=AB+AC+BC.
PROCEDURE
Verify whether all components and wire are in good condition. Setup the half adder control
and feed the input bit combination. Observe the output corresponding to input combination
and enter it in the truth table. Repeat the steps for the full adder.
CIRCUIT DIAGRAM

A
S
B
Cin
Cout
USING NAND ONLY
OBSERVATION
HALF ADDER
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

FULL ADDER
A B Cn-1 S Cn
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
RESULT
Circuit of full and half adder was set .Output of full and half adder is obtained and verified.
CONCLUSION
APPLICATION
One major application of adder are in computers. They are a part of ALU.

Experiment no:4
Date: 27/2/06
HALF AND FULL SUBTRACTOR

INTRODUCTION
Subtractor is examples of combinational circuit.
PROBLEM DEFINITION
To design and setup half subtractor and full subtractor using EXOR gates and NAND gates.

IC 7400 quad 2input NAND 1
7486 quad 2input XOR 1
Led 1
Resistor 330Ω 1
HALF SUBTRACTOR
A half subtractor is combinational circuit that subtracts two bits and produces their
difference. It also has an output to specify if a 1 has been borrowed.
It has two inputs and two outputs. One input is the difference while other is the borrow. It is
represented by D & B. It do not have a borrow input. X is the minuend bit while Y is the
subtrahend. The output borrow B is a 0 as long as X>=Y. It is a 1 for X=0 and Y=1. The D
output is the result of the arithmetic operation.
D=X’Y+XY’
B=X’Y.
FULL SUBTRACTOR
A full subtractor is a combinational circuit that performs a subtraction between two bits,
taking into account that a 1 may have been borrowed by a lower significant stage. This circuit
has three inputs and two outputs. The three inputs, X, Y, Z denote minuend, subtrahend and
previous borrow. The two outputs D and B represent the difference and output borrow.
Three inputs have eight combinations of 1’s and 0’s.
The simplified Boolean function or the two outputs of the full subtractor are:
D=X’Y’Z+X’YZ’+XY’Z’+XYZ
B=X’Y+X’Z+YZ.
PROCEDURE
Verify all the components and the wires are in good condition. Setup the half subtractor
circuit and feed the input bit combination. Observe output corresponding to input
combination and enter it in the truth table. Repeat the steps for full subtractor.
CIRCUIT DIAGRAM

OBSERVATION
HALF SUBTRACTOR
X Y D B
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
FULL SUBTRACTOR
X Y Z D B
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

RESULT
Circuit of full and half subtractor was set .Output of full and half subtractor is obtained and
verified.
CONCLUSION
APPLICATION
One major application of subtractor is it is used in computers. It is a part of ALU.

Experiment no:5
Date: 6/3/06
ASYNCHRONOUS COUNTER
INTRODUCTION
The logic circuits whose output at any instant of time is dependent not only on the present
inputs but also on the past inputs are called sequential circuits. In this type of circuit, outputs
are fed back. Thus, an output signal can be a function, not only on past inputs signals, but
also of the past output signals. It mainly consists of a combinational circuit to which memory
elements are connected to form the feed path. Block diagram is as follows:
The memory elements are devices capable of storing binary information within them. The
binary information stored in the memory element at any given time defines the state of the
sequential circuit. Sequential circuit receives binary information from external inputs. These
inputs, together with the present state of the memory elements determine the binary value at
the output terminal. They also determine the condition for changing the state in the memory
elements. A sequential circuit is specified by a time sequence of inputs, outputs and internal
states. Flip flops are the memory element widely used. It is device that exhibit two different
stable states. Its output remains constants until it is switched in response to its input signal.
They are called so since they allow operations to be performed in sequence.
PROBLEM DEFINITION
To set up a 4 bit binary up asynchronous counter and study their working.

IC 7476 2
Led 4
Resistor 330Ω 4
Bread board 1
A counter is sequential circuit consisting of a set of flip flops that tally or counts the number
of input pulses it receives. An asynchronous or ripple counter is also called as asynchronous
or serial sequential circuit. In this type of counters, flip flops are not in the command of
single clock. Each flip flop is triggered by the previous flip flop and thus the counter has a
cumulative settling time. A 4 bit ripple counter has four flip flops and can count up to fifteen.
A clocked JK flip flop is used. The system clock, a square wave drives first flip flop.
U1A
S
J Q
CP _
K Q
R
The above diagram is JK flip flop. In a counter, output of first flip flop drives the clock of the
second and output of the second drives clock of the third and so on. The trigger moves
through the flip flops k\like a ripple. Hence we call it a ripple counter. The overall
propagation delay time of the counter is the sum of the delay time of the individual flip flop.
All J and K inputs of the flip flop are tied together to Vcc, which means that flip flop toggles
on the negative edge of its clock input. Since this counter has 16 different states, it is called a
16-mod ripple counter.
PROCEDURE
Test all IC’s using a digital tester. Also test all wires for continuity using a multimeter. Set up
the circuit for a 4 bit ripple counter. Connect the preset pins to disable it. Clear all flip flop
outputs initially by connecting common clear terminal to logic o. after the usage of clear pins
connect it to logic 1 or keep it open. Apply mono pulses. Counter starts counting.
CIRCUIT DIAGRAM

OBSERVATION
Clock Q3 Q2 Q1 Q0
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 0 0 0 0
GRAPH
RESULT
Circuit of asynchronous counter was set and counting sequence and waveforms was verified.
CONCLUSION
APPLICATION
Its major application includes pulse counting, frequency division, time measurement, control
and timing operation.

Experiment no:6
Date: 13/3/06
SYNCHRONOUS COUNTER
INTRODUCTION
elements are connected to form the feed path. Block diagram is as follows:
The memory elements are devices capable of storing binary information within them. The
binary information stored in the memory element at any given time defines the state of the
sequential circuit. Sequential circuit receives binary information from external inputs. These
inputs, together with the present state of the memory elements determine the binary value at
the output terminal. They also determine the condition for changing the state in the memory
elements. A sequential circuit is specified by a time sequence of inputs, outputs and internal
states. Flip flops are the memory element widely used. It is device that exhibit two different
stable states. Its output remains constants until it is switched in response to its input signal.
They are called so since they allow operations to be performed in sequence.
PROBLEM DEFINITION
To set up a 4 bit binary up synchronous counter and study their working.

IC 7473 2
Led 4
Resistor 330Ω 4
Bread board 1
A counter is sequential circuit consisting of a set of flip flops that tally or counts the number
of input pulses it receives. The synchronous counters eliminate the cumulative flip flop
delays seen in the ripple counters. All flip flops are under the control of the same clock pulse.
That is all flip flops work in synchronism with the input clock pulse. Output changes at the
same instant. Propagation delay is eliminated. It can be designed in the following procedure
for any given count sequence or modulus.
1. Find number of flip flop using the relation, 2n = M, where M is the modulus of
counter and n is number of flip flops.
2. Write down the count sequence in table.
3. Determine flip flop input which will be present for the desired next state using
excitation table of flip flops.
4. Prepare karnaugh map for each flip flop input in terms of flip flop output as input
variable.
A clocked JK flip flop is used. The system clock, a square wave drives first flip flop. The JK
flip flop used is given below.
U1A
S
J Q
CP _
K Q
R
PROCEDURE
Test all IC’s using a digital tester. Also test all wires for continuity using a multimeter. Set up
the circuit for a 4 bit synchronous counter. Connect the preset pins to disable it. Clear all flip
flop. Verify the counter state.
DESIGN
Excitation table of JK flip flop.
Qn Qn+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

Solving using karnaugh map,

CIRCUIT DIAGRAM
OBSERVATION
Clock Q3 Q2 Q1 Q0
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 0 0 0 0
RESULT
Circuit of synchronous counter was set and counting sequence and waveforms was verified.
CONCLUSION
APPLICATION
Its major application includes pulse counting, frequency division, time measurement, control
and timing operation.

Experiment no:7
Date: 13/3/06
ADDER/SUBTRACTOR USING 7483
INTRODUCTION
Adders and subtractors are examples of combinational circuit.
PROBLEM DEFINITION
To design and set up a 4bit adder/subtractor using IC 7483.

IC 7483 1
Led 4
Resistor 330Ω 4
Bread board 1
A full adder is a combinational circuit that forms the arithmetic sum of three input bits. It
consists of three inputs and two outputs. Two of the input variables, represent the two
significant bits to be added. The third input, represents the carry from the previous lower
significant position. Two outputs are necessary because the arithmetic sum of three binary
digits ranges in value from 0 to3 and binary 2 or 3 requires two bits. The two outputs are
designated as S and C. The binary variable S gives the value of the least significant bit of the
sum. The binary variable C gives the output carry.
With three inputs, eight input combination are possible. When all the inputs are 0, then output
is 0. The S is equal to 1 when only one input is equal to 1or all the three inputs are equal to 1.
The C output has a carry of 1 if two or three inputs are equal to 1.

7483 has four full adders in it. This means that it can add nibble. To add bytes, two 7483 is
required.
To add nibble, SUB is made 0. to subtract B3B2B1B0 from A3A2A1A0 SUB is made 1.
EXOR gates function as controlled inverters. When SUB is 1, B3B2B1B0 is complemented.
Now, A3A2A1A0, complemented version of B3B2B1B0 and 1 at Cin pin are added together.
Cout is ignored. If minuend is less than subtrahend, the obtained output will be 2’s
complement of the difference.
PROCEDURE
Test all components and IC package using multimeter. Set up the nibble adder and try a few
nibble additions. Verify the addition of the circuit. Set up add/subtractor circuit. Make
SUB=0 and verify whether it works as a nibble adder. To function as a subtractor, make
SUB=1 and verify whether it works as the nibble subtractor.
CIRCUIT DIAGRAM

OBSERVATION
ADDER
B3 B2 B1 B0 A3 A2 A1 A0 S3 S2 S1 S0
0 0 0 1 1 0 0 0 1 0 0 1
1 0 0 1 0 1 1 0 1 1 1 1
0 1 0 1 0 0 0 1 0 1 1 0
1 1 0 1 0 0 1 0 1 1 1 1
SUBTRACTOR
B3 B2 B1 B0 A3 A2 A1 A0 S3 S2 S1 S0
0 0 0 1 1 0 0 0 0 1 1 1
1 0 0 1 0 1 1 0 1 1 0 1
0 1 0 1 0 0 0 1 1 1 0 0
1 1 0 1 0 0 1 0 0 1 0 1
RESULT
The add\subtract circuit using 7483 was set up and observation was verified.
CONCLUSION
APPLICATION
One major application of adder\subtractor is in computers. They are a part of ALU.

Experiment no: 8
Date: 27/3/06
JOHNSON’S COUNTER
INTRODUCTION
elements are connected to form the feed path.
Shift registers are a type of sequential logic circuit, mainly for storage of digital data. They
are a group of flip-flops connected in a chain so that the output from one flip-flop becomes
the input of the next flip-flop. Most of the registers possess no characteristic internal
sequence of states. All the flip-flops are driven by a common clock, and all are set or reset
simultaneously. Shift registers are very important in applications involving the storage and
transfer of data in a digital system. The basic difference between register and a counter is that
a register has no specified sequence of state except in certain very specialized application. A
register is used for storing and shifting data entered into it from external source .
A shift register counter is basically a shift register with the serial output connected back to the
serial input in order to produce special sequence.
PROBLEM DEFINITION
To design and set up a four bit Johnson’s counter using

a. JK flip flop.
b. D flip flop.
COMPONENTS REQUIRED


IC 7476 2
7474 2
Led 4
Resistor 330Ω 4
Bread board 1
Johnson counters are a variation of standard ring counters, with the inverted output of the last
stage fed back to the input of the first stage. They are also known as twisted ring counters.
An n-stage Johnson counter yields a count sequence of length 2n, so it may be considered to
be a mod-2n counter.
Initially, all flip flops are reset. After the first clock pulse, FF0 is set and the remaining FF’s
are reset. After the forth clock pulse, all flip flops are set. After the fifth clock pulse, FF0 is
reset and the remaining flip flops are set. After the eight clock pulse, all flip flops are reset.
There are eight different output conditions creating a mode 8 Johnson’s counter.
U1A
U1A
S
D Q S
_ J Q
CP Q CP _
K Q
R
R
D flip flop JK flip flop
Again, the apparent disadvantage of this counter is that the maximum available states are not
fully utilized. Only eight of the sixteen states are being used.
The D's are the parallel inputs and the Q's are the parallel outputs. Once the register is
clocked, all the data at the D inputs appear at the corresponding Q outputs simultaneously.
PROCEDURE
Set up the Johnson’s counter and reset the entire flip flop. Apply monopulses to the clock pin.
Note down the states of the counter outputs on the truth table for successive clocks.
CIRCUIT DIAGRAM

OBSERVATION
Clock Q3 Q2 Q1 Q0
0 0 0 0 0
1 1 0 0 0
2 1 1 0 0
3 1 1 1 0
4 1 1 1 1
5 0 1 1 1
6 0 0 1 1
7 0 0 0 1
GRAPH
RESULT
Johnson’s counter was designed and set up. Output was verified using truth table.
CONCLUSION
APPLICATION
Counter are used as counting circuit in many applications.

Experiment no: 9
Date: 27/3/06
RING COUNTER
INTRODUCTION
elements are connected to form the feed path.
Shift registers are a type of sequential logic circuit, mainly for storage of digital data. They
are a group of flip-flops connected in a chain so that the output from one flip-flop becomes
the input of the next flip-flop. Most of the registers possess no characteristic internal
sequence of states. All the flip-flops are driven by a common clock, and all are set or reset
simultaneously. Shift registers are very important in applications involving the storage and
transfer of data in a digital system. The basic difference between register and a counter is that
a register has no specified sequence of state except in certain very specialized application. A
register is used for storing and shifting data entered into it from external source .
PROBLEM DEFINITION
To design and set up a four bit Johnson’s counter using
a. JK flip flop.
b. D flip flop.

COMPONENTS REQUIRED

IC 7476 2
7474 2
Led 4
Resistor 330Ω 4
Bread board 1
A ring counter is a type of counter composed of a circular shift register. Connecting the
output of the shift register to its input and circulates a single one (or zero) bit around the ring
gives the ring counter. It can be constructed using both D flip flop and JK flip flop.
U1A
U1A
S
D Q S
_ J Q
CP Q CP _
K Q
R
R
D flip flop JK flip flop
To start the counter, first flip flop is set using preset facility and the remaining flip flop are
reset using the clear facility. When clock pulse arrives, set condition in the first flip flop goes
as the input to the next flip flop. During the next clock, set condition from the second flip flop
goes as input to the third flip flop. This continues.
Since the count sequence has 4 distinct states, the counter can be considered as a mod-4
counter. Only 4 of the maximum 16 states are used, making ring counters very inefficient in
terms of state usage. But the major advantage of a ring counter over a binary counter is that it
is self-decoding. No extra decoding circuit is needed to determine what state the counter is in.
PROCEDURE
Set up the Johnson’s counter and reset the entire flip flop. Apply monopulses to the clock pin.
Note down the states of the counter outputs on the truth table for successive clocks.
CIRCUIT DIAGRAM

OBSERVATION
Clock Q3 Q2 Q1 Q0
1 1 0 0 0
2 0 1 0 0
3 0 0 1 0
4 0 0 0 1
5 1 0 0 0
GRAPH
RESULT
Ring counter was designed and set up. Output was verified using truth table.
CONCLUSION
APPLICATION
Counter are used as counting circuit in many applications.

Experiment no: 10
Date:3/4/06
FILP FLOPS USING NAND GATE
INTRODUCTION
LOGIC GATES
A logic gate is an elementary building block of a digital circuit. A logic gate is an

arrangement of controlled switches used to calculate operations using Boolean logic in digital
circuits. They are primarily implemented electronically (using diodes, transistors) but can
also be constructed using electromagnetic relays, fluidics, optical or even mechanical
elements. Most logic gates have two inputs and one output. At any given moment, every
terminal is in one of the two binary conditions low (0) or high (1), represented by different
voltage levels.
The logic state of a terminal can, and generally does, change often, as the circuit processes
data. In most logic gates, the low state is approximately zero volts (0 V), while the high state
is approximately five volts positive (+5 V).
In electronics and computing, the flip-flop or bi stable multivibrator is a pulsed digital circuit
capable of serving as a one-bit memory.
Flip flop is a type of circuit that is interconnected with like circuits to form logic gates in
digital integrated circuits, such as memory chips and microprocessors. The name “flip-flop”
comes from the circuit’s nature of alternating between two states when a current is applied to
the circuit. A flip-flop will maintain its state indefinitely until it receives an input pulse,
called a trigger, which forces it to alternate its state. Once the circuit changes state it remains
in that state until another trigger is received
A flip-flop typically includes zero, one, or two input signals; a clock signal; and an output
signal, though many commercial flip-flops additionally provide the complement of the output
signal.
Some flip-flops also include a clear input signal, which resets the current output. Because
flip-flops are implemented as integrated circuit chips, they also require power and ground
connections. Pulsing, or strobing, the clock causes the flip-flop to either change or retain its
output signal, based upon the values of the input signals and the characteristic equation of the
flip-flop. Strobing here means changing the clock, some flip-flops change output on the rising
edge of the clock, and other change on the falling edge.
Usually a NAND gate is used to implement a flip flop. IC 7400 is the NAND gate IC that is
used.
PROBLEM DEFINITION
To set up the following flip flop.

1. JK flip flop

2. T flip flop
3. D flip flop
4. Master slave flip flop.
COMPONENTS REQUIRED
COMPONENETS SPECIFICATION QUANTITY

NAND gate IC 7400 quad 2 input 2
7410 quad 3 input 2
Led 2
Resistor 330Ω 2
DC power supply 0-30v 1
Four types of flip-flops find common applicability in clocked sequential systems: these are
called the T ("toggle") flip-flop, the MS JK ("master slave JK") flip-flop, the JK flip-flop, and
the D ("delay") flip-flop.
1. JK flip flop: In this type of flip flop, when clock is high if both J and K inputs are low
that is 0, then output is the same as the previous output. When J is low and K is high,
then output is low and when J is high and K is low, then output is high. When both J
and K is high, then output is the complement of the previous output.
2. T flip flop: T flop flop can be obtaind by connecting J and K inputs together. When
clock is given, if T input is high, then outptu goes on toggling and when T input is
low, the outptu is same as the previous output.
3. D flip flop: The D ("delay") flip-flop takes one input, which it conveys to the output
when the clock is given. Regardless of the current value of the output, it will assume a
value 1 if D = 1 when the flip-flop is strobed or a value 0 if D = 0 when the flip-flop
is clocked.
4. MS JK flip flop: A master-slave flip-flop is constructed from two separate flip- flops.
One is the master and other is slave.
The master flip-flop is enabled on the positive edge of the clock pulse CP and the
slave flip-flop is disabled by the inverter. The information at the external J and K
inputs is transmitted to the master flip-flop. When the pulse returns to 0, the master
flip-flop is disabled and the slave flip-flop is enabled. The slave flip-flop then goes to
the same state as the master flip-flop.
PROCEDURE
Test all the components and IC package using the multimeter. Set up the flip flop using gates
and verify their truth table.
CIRCUIT DIAGRAM

OBSERVATION
JK flip flop (clk=1)
J K Qn+1 Q’n+1
0 0 Qn Qn’ No change
0 1 0 1 Reset
1 0 1 0 Set
1 1 Qn’ Qn Toggle
MS JK flip flop (clk=1, master; clk=0, slave)
J K Qn+1 Q’n+1
0 0 Qn Qn’ No change
0 1 0 1 Reset
1 0 1 0 Set
1 1 Qn’ Qn Toggle

T flip flop (clk=1) D flip flop (clk=1)
T Qn+1 Q’n+1 D Qn+1 Q’n+1

0 Qn Qn’ No change 0 0 1
1 Qn’ Qn Toggle 1 1 0
RESULT
JK, D, T, MSJK flip flop was set and its operations were verified using the truth table.
CONCLUSION
APPLICATION
The T flip-flop is useful for counting. T flip-flops as described above will also function to
divide an input in frequency by 2n, where n is the number of flip-flops used between the input
and the output. A D flip-flop can represent one digit of a binary number. The computer's
control unit puts out the clock signal at the right time to capture the data.

Experiment no: 11
Date: 3/4/06
TRANSISTOR TRANSISTOR LOGIC
INTRODUCTION
A group of compatible IC’s with the same logic levels and supply voltages for performing
various logic functions have been fabricated using a specific circuit configuration which is
referred to as logic family.
The main elements of a bipolar IC are resistors, diode and transistor. There are two types of
operation in bipolar IC:
1. Saturated.
2. Non-saturated.
In saturated logic, the transistor in the IC is driven to saturation, whereas in non saturated
logic, the transistor is not driven into saturation.
The saturated bipolar logic families are:
1. Resistor-transistor logic (RTL).
2. Direct-coupled transistor logic (DCTL).
3. Integrated-injection logic (I2L).
4. Diode-transistor logic (DTL).
5. High-threshold logic (HTL).
6. Transistor-transistor logic (TTL).
The non saturated bipolar logic families are:
1. Schottky TTL.
2. Emitter-coupled logic (ECL).
The various characteristic of digital IC’s used to compare their performance are:
1. Propagation delay: The delay time between application of the input and occurrence of
the output. The delay time is measured between 50%of voltage levels of the input and
output waveforms.
2. Power dissipation: the amount of power dissipated by the IC.
3. Figure of merit: the product of speed and power. Its unit is pJ. A low value of speed-
power product is desirable.
4. Fan out: the number of similar gates which can be driven by a gate. High fan out is
advantageous because it reduces the need for additional drivers to drive more gate.
5. Noise immunity: the circuit’s ability to tolerate noise signals is referred to as noise
immunity.
PROBLEM DEFINITION
To plot the transfer characteristic of TTL NAND gate.
COMPONENTS REQUIRED

IC 7400 dual input 1
Ammeter 1
Voltmeter 1
Bread board 1

Transistor-Transistor Logic (TTL) is a class of digital circuits built from bipolar junction
transistors (BJT), and resistors. TTL integrated circuits are examples of small-scale to
medium-scale integration. Each "chip" contains the equivalent of a few dozen to a few
hundred transistors, contrasting with early very-large-scale integration (VLSI) devices that
had the equivalent of up to 10,000 transistors, and modern microprocessors that are
equivalent to tens of millions of transistors.
TTL replaced DTL because there was one main disadvantage of DTL. It was slow. In order to
overcome this, TTL was introduced.
TTL
Working of the above circuit is as follows. When at least one of the inputs is low, the EB
junction of Q1 is forward biased and Q2 and Q3 if off. Since Q3 if off output is high. When
all the inputs are high, the EB junction of Q1 is reverse biased. So Q2 and Q3 are on. So
output is low.
PROCEDURE
Test all the components and IC package using multimeter. Set up the circuit to plot the
transfer characteristic. Vary the input voltage from 0v to 5v. Take the corresponding
voltmeter reading. Plot the graph between Vi and Vo.
CIRCUIT DIAGRAM

OBSERVATION
Input voltage Vi Output voltage Vo

0 5
0.5 5
1 5
1.3 3
1.5 0
GRAPH
RESULT
The experiment to plot the transfer characteristic of TTL NAND gate was performed
successfully and transfer characteristic was drawn.
CONCLUSION
APPLICATION
TTL is notable for being a widespread integrated circuit (IC) family used in many
applications such as computers, industrial controls, music synthesizers, and electronic test
and measurement instruments.

Experiment no: 14
Date: 3/4/06
CMOS CHARACTERISTIC
INTRODUCTION
CMOS is short for complementary metal oxide semiconductor. CMOS is a widely used type
of semiconductor. CMOS semiconductors use both NMOS (negative polarity) and PMOS
(positive polarity) circuits. Since only one of the circuit types is on at any given time, CMOS
chips require less power than chips using just one type of transistor. The word
"complementary" refers to the fact that the design uses pairs of transistors for logic functions,
only one of which is switched on at any time.
The word "complementary" refers to the fact that the design uses pairs of transistors for logic
functions, only one of which is switched on at any time. The phrase "metal-oxide-
semiconductor" is a reference to the nature of the fabrication process originally used to build
CMOS chips. That process created field effect transistors having a metal gate electrode
placed on top of an oxide insulator, which in turn is on top of a semiconductor material.
CMOS logic uses a combination of p-type and n-type metal-oxide-semiconductor field effect
transistors (MOSFETs) to implement logic gates and other digital circuits found in
computers, telecommunications and signal processing equipment.
PROBLEM DEFINITION
To plot the transfer characteristic of CMOS NOT gate.
COMPONENTS REQUIRED

IC 7404 dual input 1
Ammeter 1
Voltmeter 1
Bread board 1
A CMOS inverter uses two enhancement MOSFETS’S, T1 & T2. T1 is a p-channel device
while T2 is an n-channel device.

When an input signal is at logic 0, T1 turns OFF and T2 turns ON. Therefore output is logic 1
. Similarly when the input is logic 1, T1 is ON and T2 is OFF. Hence the output is logic 0.
PROCEDURE
Set up the circuit to find the transfer characteristic after testing the IC and other components.
Vary the input voltage and take the meter reading. Draw the transfer characteristic. To
observe the characteristic on the CRO keep the CRO in the transfer characteristic mode.
CIRCUIT DIAGRAM
OBSERVATION

0 3.6
0.5 3.5
0.8 3.4
1 2
1.1 0
GRAPH

RESULT
The experiment to plot the transfer characteristic of CMOS NOT gate was performed
successfully.
CONCLUSION
APPLICATION
CMOS chips include microprocessor, microcontroller, static RAM, and other digital logic
circuits. The central characteristic of the technology is that it only uses significant power
when its transistors are switching between on and off states. Consequently, CMOS devices
use little power and do not produce as much heat as other forms of logic. CMOS also allows
a high density of logic functions on a chip.

Experiment no: 12
Date: 8/4/06
OP AMP CHARACTERISTIC
INTRODUCTION
An operational amplifier, often referred to as an 'op-amp', is a DC-coupled electronic

differential voltage amplifier, usually of very high gain, with one inverting and one non-
inverting input. The single output voltage is the difference between the inverting and non-
inverting inputs multiplied by the open-loop gain. An op amp is a direct coupled high gain
amplifier consisting of one or two differential amplifier with a level shifter and an output
stage which is usually push pull amplifier.
It has two terminals. One is the inverting (-ve ) terminal, second one is the non inverting
terminal (+ve). When an input is given to the inverting terminal, output is amplified but is
180 degree out of phase. But in the non inverting terminal, it is only amplified and not
inverted. Vs+ and Vs- is the power supply to the amplifier. Vout is the amplified output.
The operational amplifier was originally designed to perform mathematical operations—

hence its name— by using voltage as an analogue of another quantity. This is the basis of the
analogue computer where op-amps were used to model the basic mathematical operations
(addition, subtraction, integration, differentiation, and so on). However, an ideal operational
amplifier is an extremely versatile circuit element, with a great many applications beyond
mathematical operations. It can be used to amplify both dc and ac signal.
For any input voltages the ideal op-amp has infinite open-loop gain , infinite bandwidth,
infinite input impedances (and hence zero input currents), zero output impedance, zero noise,
and zero input offset voltage (exactly 0 V out when both inputs are equal).it also has infinite
bandwidth so that it can amplify signal of any frequency. Real op-amps can only approximate
to this ideal, and the actual parameters are subject to drift over time and with changes in
temperature, input conditions, etc.
PROBLEM DEFINITION
To design and implement an inverting and non inverting amplifier using 741C operational
amplifier and to plot the transfer characteristic.

COMPONENTS REQUIRED

IC 741C 1
Resistor 1k 1
10k 1
Power supply -15v to +15v 1
Bread board 1
Operational amplifier is of two configurations:
1. Inverting amplifier
2. Non inverting amplifier.
In non inverting amplifier, the input signal is effectively used as the reference voltage at the
"+" input to the differential amplifier, while the "-" input is indirectly referenced to ground. In
order to keep the two input voltages to the amplifier the same, the amplifier must set Vout to
whatever voltage is required to make the feedback voltage to the "-" input match the input
voltage to the "+" input. Here the output is amplified by A (gain) times input voltage and it is
in phase with the input signal.
Gain , Af = 1+Rf / R where Rf=feedback resistance.
In inverting amplifier, the input signal is effectively used as the reference voltage at the "-"
input to the differential amplifier, while the "+" input is indirectly referenced to ground. In
order to keep the two input voltages to the amplifier the same, the amplifier must set Vout to
whatever voltage is required to make the feedback voltage to the "-" input match the input
voltage to the "+" input. Here the output is amplified by A (gain) times input voltage and it is
out of phase with the input signal.
Gain, , Af = -Rf / R where Rf=feedback resistance

PROCEDURE
Test all the components and IC package using multimeter. Set up the circuit to plot the
transfer characteristic. Apply the input signal and obtain the output voltage for the
corresponding input. Draw the graph.
DESIGN
Inverting amplifier
Gain, , Af = -Rf / R
To obtain gain of 10, suppose R=1k. Then,
10= -Rf / 1
Rf= 10K.
Non inverting amplifier
Gain , Af = 1+Rf / R .
To obtain gain of 10, suppose R=1k. Then,

10= 1+Rf / 1
Rf= 9K.
CIRCUIT DIAGRAM
OBSERVATION
Inverting Amplifier

0.1 -1
0.2 -2
0.4 -4
0.6 -5.8
0.8 -7.6
1.0 -9.8
1.2 -13
1.4 -14
Non inverting Amplifier

0.1 1
0.2 1.8
0.4 4
0.6 5.8
0.8 7.4
1.0 9.6
1.2 12
1.4 14
GRAPH
Inverting amplifier
0
S
c
al
e
x
:
1
di
v=
0.
2
v
O
u
t
put -
2 y
:
1
di
v=
-2
v
v
o
l
t
age
V
o
-
4
-
6
-
8
-
1
0
-
1
2
-
1
4
1
.
4 1
.
2 1 0
.
8 0
.
6 0
.
4 0
.
2 0
I
n
put
vo
lt
a
geV
i
Non inverting amplifier

1
4
S
c
al
e
x
:
1
di
v
=0.
2
v
1
2 y
:
1
di
v
=2v
O
u
t
p
ut
v
o
l
t
ag
e
V
o
1
0
0
0 0
.
2 0
.
4 0.
6 0
.
8 1 1
.
2 1
.
4
I
n
pu
tv
o
l
t
ag
eV
i
CONCLUSION
APPLICATION
The basic mathematical operations such addition, subtraction, integration, differentiation, and
so on are some of the application of operational amplifier.

Experiment no: 13
Date: 8/4/06
OP AMP PARAMETER
INTRODUCTION
An operational amplifier, often referred to as an 'op-amp', is a DC-coupled electronic

differential voltage amplifier, usually of very high gain, with one inverting and one non-
inverting input. The single output voltage is the difference between the inverting and non-
inverting inputs multiplied by the open-loop gain. An op amp is a direct coupled high gain
amplifier consisting of one or two differential amplifier with a level shifter and an output
stage which is usually push pull amplifier.
It has two terminals. One is the inverting (-ve ) terminal, second one is the non inverting
terminal (+ve). When an input is given to the inverting terminal, output is amplified but is
180 degree out of phase. But in the non inverting terminal, it is only amplified and not
inverted. Vs+ and Vs- is the power supply to the amplifier. Vout is the amplified output.
The operational amplifier was originally designed to perform mathematical operations—

hence its name— by using voltage as an analogue of another quantity. This is the basis of the
analogue computer where op-amps were used to model the basic mathematical operations
(addition, subtraction, integration, differentiation, and so on). However, an ideal operational
amplifier is an extremely versatile circuit element, with a great many applications beyond
mathematical operations. It can be used to amplify both dc and ac signal.
For any input voltages the ideal op-amp has infinite open-loop gain , infinite bandwidth,
infinite input impedances (and hence zero input currents), zero output impedance, zero noise,
and zero input offset voltage (exactly 0 V out when both inputs are equal).it also has infinite
bandwidth so that it can amplify signal of any frequency. Real op-amps can only approximate
to this ideal, and the actual parameters are subject to drift over time and with changes in
temperature, input conditions, etc.
PROBLEM DEFINITION
To measure input bias current, input offset current, input offset voltage, amd commom mode
rejection ratio.

COMPONENTS REQUIRED

IC 741C 1
Resistor 1M 1
100Ω 2
100k 2
Capacitor 0.01µF 1
Power supply -15v to +15v 1
Bread board 1
1. Input offset voltage: It is the voltage that must be applied between the two input
terminal of an op amp to null the output.. it is denoted as Vio. It can either positive or
negative. The maximum value is 6mV dc.
2. Input offset current: The algebraic difference between the current in to the inverting
and non inverting terminal is referred to as input offset current. It is denoted as Iio.
Iio= | IB1- IB2 |.
Where IB1 is current flowing in to the non inverting terminal and IB2 is the current
flowing in to the inverting terminal. Maximum value is 200nA.
3. Input bias current: it is the average of the currents that flow into inverting and non
inverting terminal of the op amp.
IB =( IB1 + IB2 )/2.
Where IB1 is current flowing in to the non inverting terminal and IB2 is the current
flowing in to the inverting terminal. Maximum value is 500nA.
4. Common mode rejection ratio: CMRR is defined as the ratio of differential voltage
gain and common mode voltage gain.
CMRR = Ad /Acm
Where Ad is differential voltage gain and Acm is common mode voltage gain.
PROCEDURE
Test all the components and IC package using multimeter. Set up the circuit and obtain the
different value.
CIRCUIT DIAGRAM

OBSERVATION
1. In input offset voltage,

Output offset voltage, V=0.8v
2. In current through inverting terminal,
Voltage V= 5*2.8 = -14v.
3. In current through non inverting terminal,
Voltage V= 5*2.8 = 14v.
4. CMRR
Voltage Vcm = 0.1.
Voltage Vod = 14v
CALCULATION
1. Input offset voltage:

Vo = Vio* 1+Rf / R
Vio = Vo/ 1+Rf / R
= 0.8/(1+100*10^3/100)
= 0.799mA.
2. Input offset current
IB1 = Vo/Rf = 1.4/1*10^6 = 1.4µA
IB2 = V0/Rf = 1.2/1*10^6 = 1.2 µA
Iio = | IB1- IB2 |.

= 0.2 µA
3. CMMR
CMRR = Ad /Acm
=20 * log(14) / 20 * log(1.1)
= 28db.
RESULT
The circuit for measuring parameters was set up. The various op amp parameters was
calculated.
CONCLUSION
APPLICATION
The basic mathematical operations such addition, subtraction, integration, differentiation, and
so on are some of the application of operational amplifier.


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Division of Computing Sciences

R 407 – Integrated Circuits Lab Rajagiri School of Engineering and

Classification of IC according to the number of transistors and other electronic components

1. SSI (small-scale integration): Up to 100 electronic components per chip.

Classifications of IC according to their mode of operation are as follows:

There are two main advantages of ICs over discrete circuits

COMPONENTS SPECIFICATION QUANTITY

Where A, B, C………, N are input variables and Y is an output variable.

Where A, B, C, ………, N are input variables and Y is the output variable.

7400 IC is a quad two input NAND gate.

7402 IC is a quad two input NOR gate.

7486 is a quad two input XOR gate.

© University Register No: 91508 3

© University Register No: 91508 4

AND GATE (7408)

NOR GATE (7402)

© University Register No: 91508 5

NAND GATE (7400)

XOR GATE (7486)

NOT GATE (7404)

An IC can function as an amplifier, oscillator, timer, counter, computer memory, or

© University Register No: 91508 6

REALISATION OF ALL GATES USING NAND GATE

7400 NAND gate IC.

© University Register No: 91508 7

To realize all gates using universal gates, NAND gates.

COMPONENETS SPECIFICATION QUANTITY

7400 IC is a quad two input NAND gate.

2. AND gate from NAND gate:

3. OR gate from NAND gate:

Y=( (A)’ . (B)’ )’ = A+B

4. NOR gate from NAND gate:

Y= (( (A)’ . (B)’ )’)’ = (A+B)’

5. XOR gate from NAND gate:

Y=(( A. (B)’)’ .(( A)’.B)’)’ = A B’+A’B

© University Register No: 91508 8

© University Register No: 91508 9

AND GATE (7408)

NOR GATE (7402)

XOR GATE (7486)

NOT GATE (7404)

© University Register No: 91508 11

HALF AND FULL ADDERS

Adders are examples of combinational circuit.

COMPONENTS SPECIFICATION QUANTITY

© University Register No: 91508 13

USING NAND ONLY

© University Register No: 91508 14

© University Register No: 91508 15

HALF AND FULL SUBTRACTOR

Subtractor is examples of combinational circuit.

COMPONENTS SPECIFICATION QUANTITY

© University Register No: 91508 17

© University Register No: 91508 18

One major application of subtractor is it is used in computers. It is a part of ALU.

© University Register No: 91508 19

To set up a 4 bit binary up asynchronous counter and study their working.

COMPONENTS SPECIFICATION QUANTITY

© University Register No: 91508 21

© University Register No: 91508 22

To set up a 4 bit binary up synchronous counter and study their working.

COMPONENTS SPECIFICATION QUANTITY