MSAN-127
2B1Q Line Code Tutorial
Introduction
In August 1986 the T1D1.3 (Now T1E1.4) technical
subcommittee of the American National Standards
Institute chose to base their standard for the ISDN
Basic Access on the Network Side of the NT1 on an
echo cancelling technology (over Time Compression
Multiplexing) using the 2B1Q line code. This
decision culminated over 12 months of intensive
study during which the properties of various line
codes such as Biphase, AMI, MDB, 4B3T and 3B2T
as proposed by some of the worldís leading research
organizations were compared. These codes were
compared on the basis of theoretical analysis, as
well as actual performance measurements
conducted with prototype systems operating on 15
test loops. These test loops were chosen from a data
base representative of the entire North American
loop plant. After this exhaustive program of
measurement and analysis, 2B1Q was chosen as
the optimum code based on the best performance/
complexity trade-off of all the evaluated line codes.
2B1Q was found to provide the greatest loop plant
coverage for a given level of transceiver design
complexity of any code studied.
These advantages of the 2B1Q line code were first
recognized by British Telecom Research
Laboratories (BTRL) and proposed by Zarlink after
extensive comparison of various codes in their
search to find the optimum digital subscriber line
technology. The line code is based upon Pulse
Amplitude Modulation (PAM) technology which takes
multiple binary bits and converts them into a multi-
level signal. In the case of 2B1Q, two binary bits are
converted to one of four symbols, the effective
transmission rate on the line is reduced by the ratio
2:1 (i.e., half the transmission rate) or from 160 kbit/s
to 80 kbit/s. This principle is called baud rate
reduction. The advantages of baud rate reduction is
to lower the frequency component on the
transmission line allowing the transmission to benefit
from reduced line attenuation and improved
immunity to near end crosstalk and noise (can filter
the energy at the higher frequencies).
Application Note
ISSUE 2 March 1990
Line Coding
Two broad classifications of line codes exist; block
codes, and linear codes. Of the block codes, 4B3T
and 3B2T are the most prominent. Biphase, and
AMI are the leaders in the linear field. 2B1Q can be
considered to be either a block code, or a linear
code, depending on one’s definition of a block code.
For the time being, we can call it a ”linear block
code”.
In the strictest sense, block codes make use of look-
up tables to perform conversion from binary bits in a
2 level system to X-nary bits in an X-level system.
Using a multi-level line code has the effect of
reducing the transmit spectrum of the transceiver by
a factor dependent on the line code used. Figure 1
shows an example of a 4B3T conversion where 4
binary bits are converted into 3 ternary bauds (3
level). The same principles apply to 3B2T, except
the ratios are different. For 4B3T, the effective
transmission rate is reduced from 160 kbit/s to 120
kbaud/s (160 * 3/4).
2B1Q line code has baud rate reduction from 160
kbit/s to 80 kbaud/s, but it does not make use of
look-up tables in order to perform this reduction. It is
the use of these tables which differentiates block
codes from linear codes. Baud rate reduction is not
enough to label a line code a block code.
Linear codes such as Biphase and AMI, allow the
system to determine the next output baud without
resorting to conversion look-up tables. Based on
the current bit stream, the next output baud can be
determined. 2B1Q falls into this category.
Knowledge of the two current bits (dibit) results in a
prediction of the next output baud. A bit represents
2-level decisions (either 1 or 0), but a baud can
represent several levels. If the transmit rate is equal
to the incoming rate, such as with Biphase or AMI,
then bit and baud can be used interchangeably,
However, when there is baud rate reduction, bit and
baud cannot be interchanged.
A-129
MSAN-127 Application Note

0000
0001
0010
0011
0100
0101 ---> +-0
0110
0111
1000
0 1 0 1 1001
+ - 0
1010
1011
1100
4 Binary Bits 1101 3 Ternary Bauds
160 kbit/s 120 kbaud/s
1110
1111
Look-Up Table
Figure 1 - 4B3T Line Coding Example
2B1Q Coding Rules
DIBIT OUTPUT QUAT
2B1Q is a 4-level code. It takes two 2-level bits and
converts then into one 4-level baud (quat) as 10 +3
indicated in Table 1. This conversion effectively
doubles the period of the symbol. Since the period is
11 +1
inversely proportional to frequency (i.e., f=1/T) the
01 -1
frequency on the line is reduced. With every
advantage there are always drawbacks and the 00 -3
2B1Q is no exception. A 4-level code results in
reduced distance between decision levels, thus Table 1. 2B1Q Coding Rules
increasing the required SNR for a given performance
level (BER). However, the baud rate reduction and
narrower bandwidth results in performance gains Performance
which outweigh this drawback.
The transmit baud rate of the 2B1Q system is one-
The important elements of the transmit quat are its half the rate of linear codes (80 kbaud/s vs 160
sign, and its amplitude. The values assigned to the kbaud/s). This puts the bandwidth of the 2B1Q
levels are set so that there is equal spacing between system in a lower frequency region of the Power
the four levels. Levels can be chosen to be +1, Spectral Density (PSD) graph. It also produces a
+0.33, -0.33 and -1. In order to eliminate the bandwidth which is much narrower than that for
decimals, we’ll choose the four levels to be +3, +1, - Biphase. See Figure 3 for a comparison of the
1, and -3. filtered PSD plots. Telephone transmission lines act
as a low pass filter with attenuation varying directly
The 2B1Q conversion table is shown in Table 1. with frequency. Lower bandwidth codes will
experience less attenuation, thus achieving greater
The first bit of the dibit is called the “sign-bit”. If it is reach.
0, the output quat will have a negative sign. If the
first bit is 1, then the output quat will have a positive A limiting factor to most linear line codes is the
sign. The second bit of the dibit is called the performance in the presence of Near End Crosstalk
amplitude bit, and it determines the magnitude of the (NEXT). NEXT is generated onto a transmission line
output quat If it is 0, then the output level has an from the adjoining twisted pairs that are found in a
amplitude of 3. If the second bit of the dibit is 1, then bundle of cable. The signal on the adjoining pair will
the output amplitude is 1. This provides for a very induce a signal on the line. The magnitude of the
simple means of encoding a binary bit stream into a induced signal will increase proportionally with
4-level code. frequency. Therefore, if you lower a signal
bandwidth (i.e., lower frequency content) you reduce
An example of 2B1Q coding is shown in Figure 2. the effect of NEXT.

A-130
Application Note MSAN-127

INPUT OUTPUT

+3

+1

-1

0 1 0 0 1 1 0 0
-3

12.5
6.25 µs
µs

2-Level Binary Data 4-Level, Quaternary Data

160 kbit/s 80 kbaud/s

Figure 2 - 2B1Q Line Coding Example, 2 Binary, 1 Quaternary

POWER

2B1Q

4B3T

BIPHASE

TCM → 640 kHz

40 kHz 80 kHz 120 kHz 160 kHz 320 kHz

Figure 3 - 2B1Q Power Spectral Density Comparison

A-131
MSAN-127 Application Note

Complexity ST-BUS) into the transmit interface block. The sync

One drawback of low frequency transmission is that
the pulses output on the line tend to develop long
”tails”, or pulse responses caused by excessive
group delay. Several consecutive pulses will tend to
have effect on its neighbours, resulting in
Intersymbol Interference (ISI). This ISI must be
compensated for in order to ensure valid data
recovery. Decision Feedback Equalization (DFE) is
a technique which can be used to remove the effects
of ISI. A DFE is simply a finite impulse response
filter which performs a convolution of the loop
impulse response with the received data. This
convolution will provide an estimate of the effects of
ISI which can be removed from the receive signal.
Implementation
A block diagram of a 2B1Q transceiver is shown in
Figure 4. The 2B1Q transceiver has two ports
consisting of a serial system interface (Zarlink's
standard ST-BUS), and a line port which interfaces
directly to the single twisted pair via a passive
termination hybrid and a line pulse transformer.
The two B-channels and the D-channel to be
transmitted on the line are input to the DSLIC (on the
word and maintenance bits are added to the data
which is then formatted, scrambled and digitally
encoded into 2B1Q symbols. This digital
representation is passed through a finite impulse
response filter which converts the digital
representation into an analog waveform. The
transmitted pulse is then passed through a
smoothing filter whose output is passed to a
differential line driver which is capable of driving the
line directly through a passive hybrid and line pulse
transformer.
On the receive side, the precancelled signal drives a
balanced receiver which feeds the input to an over-
sampled second-order delta sigma A/D converter.
The digital representation of the received signal
yields a Pulse Density Modulated (PDM) stream
which is digitally filtered and decimated to the 80 kHz
baseband. Intersymbol interference (ISI) introduced
by the loop is cancelled by a decision feedback
equalizer. This is achieved by taking a convolution of
the received pulse with the estimated impulse
response of the loop. The cancellation of ISI is
performed in parallel with the echo cancellation.
Estimated received echo is obtained by taking the
convolution of the transmit signal with the estimated
impulse response of the loop. Feedback from the
jitter compensator and the non-linear corrector

DAC AND
ENCODER
TX FILTER

LINE
DRV

2B + D DPLL JITTER LINEAR NON-

I
COMPEN- ECHO LINEAR
N
MTCE SATOR CANCELLER COMPEN-
T SATOR
I/O 2B + D
E FRAMING
8 kHz HYBRID
R AND
CLOCK F MAINTENANCE
MC I/O
A
DECISION
C FEEDBACK
RX
E EQUALIZER
FILTER

FIR DIGITAL 2ND ORDER

DECODER QUANTIZER DECIMATING DELTA SIGMA
FILTER ADC

TIMING
ADAPTION
CIRCUIT

Figure 4 - 2B1Q Transceiver Bloc

k Diagram

A-132
Application Note
interact with the coefficients of the echo canceller to
reduce the error introduced by jitter and non-
linearities in the analog circuitry. The output of all
these blocks is summed together and the result is
the received data which is passed through a decoder
and descrambler before being sent out in TDM
bursts on the ST-BUS.
Echo-Canceller (EC)
The 2B1Q chip uses a transversal filter compensator
to cancel out the signal echo. This principle is shown
in Figure 5. The number of bits needed by the echo-
canceller is greater than for the DNIC. The DNIC
uses five bits of transmitted signal prehistory. It is
expected that the 2B1Q code will need between 30
and 40 bits. The number of bits of prehistory
corresponds to the number of ”taps” in the Echo-
Canceller. These taps carry coefficient values (Ci),
which are multiplied with the corresponding Tx bits
(Bi) and the product of all the bits/coefficients is
summed. This yields an approximation of the signal
echo. Tap coefficients in the Echo-Canceller are
updated based on an analysis of the error following
the quantizer.
Decision Feedback Equalizer (DFE)
The main purpose of the DFE is to compensate for
any ISI which is introduced into the system. Major
sources of ISI are the pulse response of the
transmitted samples, and bridged taps in the
network. The Decision Feedback Equalizer operates
on a similar principle to that described for the EC
above except that it operates on the receive bit
stream. It has taps and coefficients which are
Tx Bit
Stream
b0 b1
C0 C1
Tap
Coefficients X X • • • • • •
ECHO ESTIMATE
Figure 5 - Transversal Filter Compensator
MSAN-127
multiplied with the bit Rx stream in order to generate
an approximation of the amount of ISI in the network.
This is subtracted from the composite received
signal as well. The DFE is expected to require in the
range of 20 to 30 taps.
Quantizer (Slicer)
This block establishes which of the four levels is
present at the sampling instant. The incoming data
is sampled once per baud interval i.e., at a 80 kHz
rate. The 4-level signal is converted to binary,
based on the inverse of the 2B1Q encoding rules
discussed earlier.
Analog to Digital Converter (ADC)
One implementation of the 2B1Q line code makes
use of a “delta-sigma” ADC. This is sometimes
referred to as an “oversampled” or “noise shaping”
ADC. The principle is that the analog waveform is
sampled at a very high frequency (10 MHz), and the
samples are encoded. This information is then
passed through a decimation filter which averages
the data collected at the high frequency over a
specified period of time and filters out the high
frequency quantization noise. This method of doing
the analog to digital conversion results in a highly
accurate digital representation of the received signal.
bn bn+1
Cn Cn+1
X X
∑
A-133
MSAN-127 Application Note

Notes:

A-134
 For more information about all Zarlink products
visit our Web Site at

www.zarlink.com

Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively “Zarlink”)
is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or
use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from
such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or
other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use
of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned
by Zarlink.

This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part
of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other
information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability,
performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee
that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and suitability of any
equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily
include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury
or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request.

Purchase of Zarlink s I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided
that the system conforms to the I2C Standard Specification as defined by Philips.

Zarlink and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

Copyright 2001, Zarlink Semiconductor Inc. All Rights Reserved.

TECHNICAL DOCUMENTATION - NOT FOR RESALE

 For more information about all Zarlink products
visit our Web Site at

www.zarlink.com

Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable.
However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such
information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or
use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual
property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in
certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink.

This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part
of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other
information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the
capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute
any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and
suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does
not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in
significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request.

Purchase of Zarlink’s I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system
conforms to the I2C Standard Specification as defined by Philips.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

Copyright Zarlink Semiconductor Inc. All Rights Reserved.

TECHNICAL DOCUMENTATION - NOT FOR RESALE