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LATCH
Although both the external program memory and the external A16-A23
data memory are accessed by some of the same pins, both the
external data memory and external program memory can be
RD OE
used together. For simplicity, and especially considering that
WR WE
the MicroConverter family now supports parts with 62kBytes
of internal code space, this tech note will assume that the user
is running from internal code space. Fig 2: External Data Memory Interface
(16MByte Address Space)
In this configuration Port 0 outputs the low address (A0àA7)
2.0 ADDRESSING UP TO 64 KBYTES OF while Port 2 outputs the high address (A8àA15) and the page
EXTERNAL DATA MEMORY address (A16àA23). As shown in figure 3 and figure 4 the
falling edge of ALE is used to latch the low address and the
To address up to 64kBytes of external data memory then the page address for the external memory requiring an extra latch
hardware should be configured as shown in figure 1. This for the multiplexing of Port 2. The read (RD) and (WR) write
interface is standard to any 8051 compatible MCU. strobes are used as normal to activate the external memory.
M icroConverter SRAM
As shown in figure 3 if the MicroConverter is writing data to
P0
D0-D7 the external memory, the data (D0àD7) will be automatically
(DATA)
outputted at Port 0 after the falling edge of ALE has been used
to latch the address. The falling edge of the WR strobe is used
LATCH
A0-A7
WR WE
M A C H INE C Y C L E 1 M A C H INE C Y C L E 2
AL E
Fig 1: External Data Memory Interface
(64kByte Address Space)
WR
In this configuration Port 0 outputs the low address (A0àA7) RD
while Port 2 outputs the high address (A8àA15). The falling
edge of ALE is used to latch the low address for the external P0 P0 DP L DATA P0
memory. The read (RD) and (WR) write strobes are used to
P2 P2 DPP DPH P2
activate the external memory. The timing diagrams in figure 3
and figure 4 are also relevant to this configuration except that FALLING EDGE OF ALE USED
FOR EXTE RNAL LATCH
the page address (DPP) on port 2 does not have to be latched
by an external latch. Fig 3: XRAM Write Operation (e.g. MOVX @DPTR, A)