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Abstract: New equations are proposed for frequency and amplitude of a ring oscillator.
The method is general enough to be used for all types of delay stages. Using exact large-
signal circuit analysis, closed form equations for estimating the frequency and amplitude of
a high frequency ring oscillator are derived as an example. The method takes into account
the effect of various parasitic capacitors to have better accuracy. Based on the loop gain of
the ring, the transistors may only be in saturation or experience cutoff and triode regions.
The analysis considers all of the above mentioned scenarios respectively and gives distinct
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equations. The validity of the resulted equations is verified through simulations using
TSMC 0.18 µm CMOS process. Simulation results show the better accuracy of the
proposed method compared with others.
Also the correct amplitude and low phase noise are two
criteria to obtain a suitable performance for VCO in a
circuit. Obtaining the transfer function or any
knowledge about the amplitude and frequency of the (a)
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⎧2π N = 2n
φ (ω ) ω =0 =⎨ (4)
⎩π N = 2n − 1
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microelectronic design text books [12].
Moreover, all of these equations cannot represent ωosc = ω0 tan(π / N ) (5)
the amplitude of the output waveform of the RO
exactly.
This paper presents a novel method to derive
equations for both amplitude and oscillation frequency
of the RO. In this method, the parameterized waveforms
of the outputs are estimated and closed-form equations
SI With simple simulations, one can find that this
analysis is incorrect if the amplitude of outputs does not
meet the small signal conditions. Also, small signal
analysis does not give any idea about the amplitude of
oscillation.
of
for unknown parameters are derived using differential Considering RO as a chain of delay stages is another
equations. The rest of the paper is as follows: SECTION method which is also commonly used by designers.
II introduces mathematical principle used to compute Assuming a delay of td for each stage, total phase shift
the frequency of oscillation and a brief review of the 2π must be provided in the period of 2Ntd. Therefore,
existing methods. Section III describes the proposed the oscillation frequency is as (6):
ive
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1 capacitors that are shown in Fig. 2 is written as (14) for
f = (10)
2 N (0.8) R ⋅ (C DBn + C DBp + CGDn + CGDp + C L ) more accurate estimation. Pure sinusoid waveform as
(15) for the outputs is the key simplifying assumption
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This equation can be adapted for single-ended RO that leads to straightforward analysis along with
considered in this paper. The transistor parasitic accurate results. Assuming this, the analysis is devoted
elements that used in this equation are gate-drain, gate- to find amplitude, A, DC level, B, and frequency, ω.
bulk and drain-bulk capacitors. Parasitic capacitors in a Although the output of an RO will not be purely
delay stage are shown in Fig. 2. sinusoidal, the frequency representation of a practical
Another method to derive an equation for the
of
RO output shows that it is a reasonable assumption [2],
oscillation frequency of only differential ring oscillator [8].
is proposed in [16]. The final equation for obtaining the
frequency is as (11) which is similar to (7), but a large ⎧ V1 − VDD dV
⎪node1 : + C 1 + K (VN − Vth )2 = 0
signal analysis is used for calculating the value of ⎪ R dt
⎪node : 2 −
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capacitors accurately. V V dV
⎪ 2
DD
+ C 2 + K (V1 − Vth )2 = 0
⎨ R dt (12)
f =
I SS ⎪ M
⎡ C jn Ad n ⎤ ⎪
⎢C L + C gdp + + ⎥ ⎪ VN − VDD dV
⎢
V
(1 + DD ) mjn ⎥ ⎪⎩nodeN : + C N + K (VN −1 − Vth ) 2 = 0
⎢ pb n ⎥ R dt
ch
⎢ C Pd ⎥
π
2NV SW ×⎢ jswn n
+ (1 + cos( ))W nC gdon +⎥ (11)
1 W
⎢ V DD mjswn ⎥
⎢ (1 + ) N
⎥ K= µnCox ( ) (13)
pbswn 2 L
⎢ ⎥
⎢C jp Ad p + C jswp Pd n ⎥
⎢ ⎥
C = CL + Cgdp + Cgdn + Cdbp + Cdbn
Ar
⎣ ⎦ (14)
VDD − B
− K ( B − Vth ) 2
A= R (21)
K cos 2 (π / N )
B − VDD
+ K ( B − A sin(π / N ) − Vth ) 2
f = R (22)
Fig. 3. Definition of currents for KCL in a delay stage. 2π CA
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frequency, amplitude and DC level of an N-stage single-
ended ring oscillator just knowing the circuit
parameters. Equation (21) shows that the amplitude is
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just proportional to the circuit parameters except
capacitors. Also the frequency is inversely proportional
to the C and R in (22). Note that the assumptions here
are the output waveform is like a sinusoid and the
transistors are all in saturation region. To verify the
of
analysis above the following two conditions should be
met.
I. The transistors should not meet triode region that
means Vn−1 (t ) < Vn (t ) − Vth .
II. The transistors should not meet cutoff region that
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means B − A ≥ Vth .
Fig. 4. Phase relation between waveforms.
Defining the voltage across the Gate-Drain junction
in first delay stage as (23), if the first condition is
satisfied, the transistors remain in saturation region.
B + A cos ωt − VDD Using the maximum points as an additional condition,
− ωCA sin ωt +
ch
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KCL equations at the output of each delay stage. These
equations can be written as (26).
⎧ V1 − VDD
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dV
⎪ R + C 1 + iD1 (t ) = 0
⎪ dt
⎪ 2V − V dV
⎪
DD
+ C 2 + iD2 (t ) = 0
⎨ R dt (26)
⎪M Fig. 5. Sample output voltages for the case that transistors
⎪
of
meet both triode and saturation regions during oscillation.
⎪ VN − VDD dV
⎪⎩ + C N + iDN (t ) = 0
R dt iD 2 ( t ) =
⎪ N −1
(15) to make the problem traceable. For instance, the ⎪+2K {[B + A cos(ωt + π ) −V th ](B + A cos ωt )
output of the second stage is considered as (15), so the ⎪ N
⎪− ( B + A cos ωt ) } = 0
2
first stage output is written as (16). The unknowns here for V 1 (t ) > V 2 (t ) +V th
⎪⎪ 2 (27)
are the frequency of oscillation, the output voltage ⎨
⎪ B + A cos ωt −V DD
amplitude and DC level of output that are f, A and B − ωCA sin ωt
ch
⎪ R
respectively. Considering the quadratic law between ⎪ N −1
Drain current and the Gate-Source voltage for the ⎪+ K ( B + A cos(ωt + π ) −V th ) 2 = 0
⎪ N
second transistor, M2, the Drain current is written as ⎪ for V 1 (t ) <V 2 (t ) +V th
(27) for second stage. As shown in Fig. 5, the outputs ⎪⎩
Ar
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condition. Fig. 7 shows the circuit model for a delay
stage while each state occurring. At the beginning of the
period, transistor is off because of the low voltage at its
gate connection, so the circuit is modeled as an RC
circuit with a time constant. The transistor meets the
saturation region when the voltage at the Gate
connection overcomes the threshold voltage, Vth. In this
state, the transistor can be modeled as a voltage
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of
controlled current source (VCCS) and increasing the
gate voltage increases the current and causes the charge
of the capacitor decreases. If the Drain-Gate voltage of (a) (b)
the transistor becomes higher than threshold voltage,
Vth, transistor experiences deep triode and triode region
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respectively.
Here, the transistor can be modeled as a small
voltage controlled resistor that is parallel with load
resistor, R, so the output voltage decreases with a small
time constant because of small load resistor. Calculating
ch
(c)
be assumed that transistors are only in triode and cutoff.
Hence, the output voltage is assumed as a triangular-like Fig. 7. Circuit models for each state occur in Fig.. 6. a)
periodic waveform. The output voltage at each stage is transistor off b) transistor is in saturation c) triode and deep
written as (33). triode region
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calculated unknown parameters when devices enter the cutoff
region
VDD (eT / NRC − 1)
tm = RCLn (38)
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Vth Load Simulation results Calculated values
Capacitor
The same expression can be used for V1(t) at the CL (pF) Period (T) tm Period (T) tm
(nsec) (nsec) (nsec) (nsec)
time T as (39)-(40). Substituting (38)-(41) result in an
1 1.11 0.63 0.90 0.58
equation for the period of time, T, as (42).
2 1.22 0.71 1.13 0.70
of
( N − 1)
V1 (T ) = V2 (T − T / N ) = V2 [ T ] = Vm (39) 3 1.43 0.82 1.36 0.84
N
4 1.65 0.93 1.58 0.97
5 1.81 1.02 1.80 1.11
Vm = V2 (tm ) = VDD − Vth (eT / NRC − 1)−1 (40)
6 1.96 1.10 2.03 1.24
ive
(42)
N −1 VDD − Vm Peak
Voltage 1.12 Volts 1.4 Volts
(Vm)
4 Simulation Versus Analytical Results
To evaluate the proposed method and compare with Table 3. Details of Technology, Supply Voltage, Load
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competitive methods, a test benchmark is created in this Capacitor Range, Size and Threshold Voltages of Transistors
section using Advanced Design System software. The Technology TSMC 0.18 µm
TSMC 1.8 V, 0.18 µm CMOS process have been used Supply Voltage 1.8 V
in simulations. Table 3 gives the details of technology, Lmin 0.18 µm
supply voltage, load capacitor, size and threshold µn.Cox 275.6×10-6 F/(V.s)
voltages of the transistors used in simulations. First, a
Capacitor (max/min) 10 pF / 1 pF
single-ended ring oscillator is simulated using different
values of load capacitor for different oscillation Size for Saturation (W/L) 50
frequencies. The sizes of the transistors were chosen Size for Triode (W/L) 80
here such that the circuit would oscillate over a wide Size for Cut-off (W/L) 300
range of capacitor. Different size of transistors is chosen VTN (normal/low) 0.47 V / 0.267 V
to obtain all possible conditions in each experiment VTP (normal/low) -0.46 V / -0.37 V
because of the direct relation between the amplitude of
outputs and the loop gain. Higher loop gain causes
The calculated frequency by the proposed equations,
higher amplitude; consequently more nonlinear
(20), (21) and (22) when transistors are in the saturation
behavior and different waveforms are available. Due to
region are compared with the simulation results
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12 eq.(6) eq.(9) eq.(10) Simulation This work
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eq.(6)
11
7
10 eq.(9)
6.5
9
eq.(10) 6
Frequency (GHz)
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5.5
7
Frequency (GHz)
Simulation
6 5
This work
5 4.5
4 4
3 3.5
2 3
1
2.5
of
0
2
1 2 3 4 5 6 7 8 9 10
21 22 23 24 25 26
Load Capacitor CL (pf)
Load Resistor RD (Ω)
(a) (b)
ive
1 4.5
eq.(6)
0.9 Simulation 4
eq.(9)
0.8 This work
3.5
Frequency (GHz)
eq.(10)
0.7 simulation
3
Amplitude (Volt)
0.5
2
0.4
1.5
0.3
1
0.2 3 5 7
0.1 50 15 12
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(c) (d)
Fig. 9. Comparison of simulation and analysis results when transistors are in saturation region.
(a) Frequency versus CL (b) Frequency versus RD (c) Amplitude versus RD (d) Frequency versus (N, W/L)
This work
Frequency (GHz)
8 2
Frequency (GHz)
6 1.5
4
1
2
0.5
0
1 2 3 4 5 6 7 8 9 10 0
Load Capacitor -CL (pf) 20 21 22 23 24 25
(a) (b)
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5
1 eq.(6)
Simulation 4.5
eq.(9)
This work 4
0.8 eq.(10)
3.5
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Simulation
Frequency (GHz) 3
Amplitude (Volt)
This work
0.6 2.5
0.4 1.5
0.5
0.2
of
0
3 5 7
0
20 21 22 23 24 25 80 40 20
(c) (d)
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Fig. 10. Comparison of simulation and analysis results when transistors meet the triode region
(a) Frequency versus CL (b) Frequency versus (N, W/L) (c) Amplitude versus RD (d) Frequency versus RD
2001.
1.2
[3] Savoj J. and Razavi B., "A 10 Gb/s CMOS clock
output voltage (Volt)
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from Sharif University of Technology in
14. 1994 and M.Sc. from Tarbiat Modares
[13] Weigandt T., "Low-phase-noise, low-timing-jitter University in 1996 and Ph.D. from Iran
design techniques for delay cell based VCOs and University of Science and Technology
frequency synthesizers," Ph.D. dissertation, Univ.
California, Berkeley, 1998.
[14] Leung B., VLSI for Wireless Communication.
Upper Saddle River, NJ: Prentice-Hall, 2002.
[15] Alioto M. and Palumbo G., "Oscillation frequency
SI in 2002 respectively. Since 2003 He has
been member of Electrical and
Electronics Engineering Faculty of
Babol University of Technology. His
research interests are analog CMOS
integrated circuit design, RF microelectronics, Image
of
in CML and ESCL ring oscillators," IEEE Trans. processing and Evolutional Algorithm.
Circuits Syst. I, Vol. 48, pp. 210–214, Feb. 2001.
[16] Docking S. and Sachdev M., "A method to drive an Ataollah Ebrahimzadeh received the
equation for the oscillation frequency of a ring B.Sc. from University of Tehran in
1995 and M.Sc. from Amirkabir
oscillators," IEEE Trans. Circuits Syst. I, Vol. 50,
University of Technology in 1999 and
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