A High-Gain, Low-Power CMOS Op Amp Using
Composite Cascode Stages
David J. Comer, Fellow IEEE, Donald T. Comer, and Rishi Pratap Singh
Department of Electrical and Computer Engineering Brigham Young University
Provo, UT 84602
Email: comer@ee.byu.edu
June 1, 2010
Abstract–This work demonstrates that the com-
posite cascode differential stage, operating in the
subthreshold region, can form the basis of a high-
gain (110 dB), low-power op amp (27.8 µW). The
circuit can be fabricated without adding a compen-
sation capacitance. Advantages of this architecture
include high voltage gain, low harmonic distortion,
low quiescent current and power, and small chip
area. These advantages suggest that this design
might be well-suited for low-power instrumentation
applications requiring multiple amplifiers as often
found in biomedical applications.
I. Introduction
In recent years, an area of increasing interest is that of
biomedical instrumentation amplifiers [1], [2]. These ap-
plications typically require high gain, low power, low fre-
quency, amplifiers that occupy minimal chip real estate.
This work discusses the subthreshold operation of compos-
ite cascode stages to achieve advantages such as high volt-
age gain [3], low nonlinear distortion [1], [4] low noise [1],
low power, low chip area, and low bandwidth. Although
low bandwidth is often considered a shortcoming, in this
case, it can eliminate the need for a compensation capaci-
tor to achieve stable operation in the presence of feedback.
Required chip area is reduced by deleting this capacitance.
II. The Classical Op Amp Architecture
The first generation, bipolar junction transistor (BJT),
general purpose, integrated circuit (IC) op amp of 1964
was designed to have a high voltage gain differential input
stage, a moderately high voltage gain second stage, and a
low voltage gain/high current gain third stage that acts as
a buffer [5]. The first two stages develop the high overall
voltage gain needed for the op amp circuit. This config-
uration, sometimes referred to as the Widlar architecture,
has continued in the design of op amps, for both BJT and
CMOS devices.
These early IC op amps required an external capacitance
or an external RC combination to compensate the op amp
[5]. This compensating network was placed between the
output of the first stage and ground. The capacitance
needed was considerably larger than could be integrated
978-1-4244-7773-9/10/$26.00 ©2010 IEEE 600
on the chip. In the next generation of IC op amps, appear-
ing in 1968, the Miller effect was used in conjunction with
the second stage to reflect a large capacitance to the output
of the first stage for compensation [6].
Although this Miller capacitance eliminates the need for
an external compensating capacitance, a few negative fac-
tors must now be considered. The first is the feedthrough
that takes place in the second stage. The signal applied
to the input of the second stage now has two paths to the
third stage; one is through the amplifier, but a second sig-
nal feeds through the capacitance that bridges the input
and output nodes of the second stage. In most applica-
tions, the feedthrough signal is negligible compared to the
amplified signal and can be ignored. In a small number of
applications, especially digital signals with small rise times,
the feedthrough signal can be troublesome. An additional
resistance in series with the compensation capacitance [8]
can be added to minimize feedthrough.
A second factor to consider is one that involves the analy-
sis or design of the op amp. Bridging the input and output
nodes of the second stage results in a phenomenon known as
“pole splitting”. While the objective of lowering the pole
or 3-dB frequency of the first stage is achieved, the pole
of the second stage is moved to a higher frequency. This
effect is more pronounced in BJT circuits than in CMOS
circuits, but must often be considered in the design with
either device [7]. Pole splitting is advantageous in achiev-
ing a higher frequency design, but requires a capacitance
and a resistance for proper compensation and, thus, adds
complexity to the design.
A third factor that can be significant in single-chip ampli-
fier arrays is the need for additional chip area required by
the compensation capacitance and resistance. Each com-
pensating capacitor may have a value of tens of pF and
occupy a significant chip area. The resistance is often im-
plemented by a MOSFET in the triode region and requires
little extra area.
As CMOS circuits grew in popularity, the BJT architec-
ture was applied to CMOS designs. The low transconduc-
tance of the MOS device compared to that of the BJT has
resulted in several departures from the classical architec-
ture for comparable performance of the CMOS op amp. If
 VDD
M3
Vbias
M4
Vout
M2
M1
Vin
VGG
Figure 1: Single-ended composite cascode gain stage.
only two stages of voltage amplification are used, voltage
gain of the op amp is relatively low [8]. Other implementa-
tions add more gain stages to increase the overall gain, but
become correspondingly more complex [9].
This work increases the CMOS op amp gain to BJT-like
levels by using the composite cascode stage operating in the
subthreshold region. In addition, the parasitic capacitance
at the output of the first stage is used to compensate the
op amp. Not only are the effects of feedthrough and pole
splitting minimized in this way, a great deal of chip area is
conserved by eliminating the compensation capacitor. Be-
cause of the low dc current required by the differential input
stage, dc power consumption can also be minimized. Op-
eration in the weak inversion region can also lead to lower
harmonic distortion than strong inversion operation [4].
III. Operation of MOS Devices in Weak Inversion
An earlier work [4] demonstrated the high gain that can
be obtained with the composite cascode stage operating
in the weak inversion region and suggested the use of this
stage for the first differential stage of a CMOS op amp.
This work also suggested that the resulting lower corner
frequency of the first stage would result in a smaller com-
pensation capacitor. In another work [10], it was suggested
that voltage gains exceeding 10,000 V/V per stage could be
achieved by combining operation in the weak or moderate
inversion region with the composite cascode configuration
of Fig. 1. Aspect ratios are chosen to operate the device
M2 in the subthreshold region while M1 operates in the
moderate or strong inversion region. Both devices are in
the active region. The subthreshold drain current of device
M2 leads to a large output resistance, resulting in a very
high voltage gain. Devices M3 and M4 provide the compos-
ite cascode load for this device which also exhibits a large
output resistance.
This concept was implemented [3] in a high gain (ap-
proximately 120 dB) CMOS op amp that used the Widlar
architecture. In that work, the overall voltage gain was
601
VDD = 1V
21/1
M9
M10 103/1
93/1 M13
M3 5/1 M4
V- V+
Vout
M1 120/1 M2
3.62uA Ibias
50/1
Cc 46/1
M11 28/1
M5 M6 M14
M12
M7 M8 1/1
1/1
VSS = −1V
Figure 2: Composite cascode op amp.
apportioned almost equally between the first and second
stage. Both of these stages have high gain (≈ 1000 V/V)
and moderate bandwidth. The circuit for this op amp is
shown in Fig. 2. Fabrication of the op amp [3] demon-
strated that sufficient gain can be obtained with CMOS
composite cascode stages to implement a high gain op amp
in the classical Widlar architecture. It also demonstrated
that the compensation capacitance can be minimized with
this approach, requiring a 3.5 pF value for the op amp.
IV. An Op Amp with no Compensation Capacitance
Rather than designing the op amp with a high-gain, mod-
erate bandwidth first stage and then degrading bandwidth
with a compensating capacitor, the premise of this work is
to create a very high-gain, very low bandwidth first stage.
This is done by using the composite cascode differential
stage shown in Fig. 3. P-channel input devices, M1 - M4,
are used for the differential pair while the current mirror
load is implemented with devices M5-M8. Source followers
are inserted between the input signal and the differential
stage to act as dc voltage level shifters. The scaling of the
devices and the tail current are selected to place devices M3
and M4 along with M5 and M6 in the subthreshold region.
This significantly increases the drain to source resistances
of these devices. In addition, the load impedances of de-
vices M3 and M4 are further increased due to the source
degeneration provided by devices M1 and M2. Devices M7
and M8 provide source degeneration for devices M5 and M6
as well.
With the high impedance loads of M1 and M3, the gain
increases and the bandwidth decreases due to the parasitic
capacitance at the output of this first gain stage. This
differential stage is similar to that of Fig. 2 [3], however,
the drain current has been decreased and scaling has been
changed from that circuit to achieve the proper quiescent
current to lead to the increased voltage gain and decreased
bandwidth.
This high voltage gain stage is followed by an output stage
consisting of a source follower (M19) that also acts as a
level shifter and the output amplifier consisting of M20 and
 VDD = 1.5V

M9 M18
M10
m=2 m=2
10/10 M13 10/10
10/10
m=8 1/8 M20

M1 M2 10/4
V- 2/20 V+

20/1 20/1 M14

m=8 m=8 Vout
V DD
20/2 1/2 0.5pF
M3 m=10 M4
M11 M19
1/1 100K
M5 M6 25/0.6
40/1 m=2
m=36 RLoad CLoad
M21
M 12
m=4
2/10 6/2
1/16 M15 10/30 M17
M7 M8 m=4
2/10 2/10
m=4 M16

VSS = -1.5V

Figure 3: Op amp without added compensation capac-

itor.

M21. Figure 4: Open loop magnitude response.

The first stage is designed to achieve a voltage gain of tens
of thousands to hundreds of thousands along with a band-
width of a few Hertz. The output stage is designed to have
a gain between 1 and 10 V/V with a relatively high band-
width. With a dominant pole of a few Hertz, the phase
margin of the circuit should be acceptable even in the worst-
case, unity gain feedback configuration. No additional com-
pensation is required for this amplifier.
V. Simulation Results
Operation of this amplifier was simulated with Cadence
using the C5 AMI 0.5-µm technology and BSIM3v3 device
models. The load impedance consisted of a 100-kΩ resis-
tance in parallel with a 0.5 pF capacitance, a heavier load
than that presented by the IC lowpass filter that is intended
to follow the amplifier stage. For the circuit of Fig. 3, the
loaded voltage gain of the differential input stage is 43,550
V/V and the bandwidth is about 1 Hz. The second stage
has a loaded voltage gain of 7.46 V/V and a bandwidth of
about 2.23 MHz. The overall voltage gain is 325,000 V/V
(110 dB) while the open loop bandwidth is about 1 Hz.
The frequency response showing magnitude and phase
is plotted in Figs. 4 and 5. The phase margin is 95◦ .
For power supply voltages of ±1.5 V, the output of the
amplifier can swing from -1.25 V to +1.35 V. In the unity
gain configuration, the total harmonic distortion or THD is
0.24% with a 2.4 V peak-to-peak output voltage and 1.5%
for a 2.6 V peak-to-peak output.
Table 1 summarizes several important parameters for the
op amp when driving the capacitor/resistor load. Figure 5: Open loop phase response.

602

Figure 6: Layout of op amp core.
Table 1 Summary of results
Open loop gain, dB 110
Open loop bandwidth, Hz 1 [7] P. R. Gray, P. J. Hurst, S. H. Lewis, and R. G. Meyer,
Spectral noise density,
√ Analysis and Design of Analog Integrated Circuits, 4th Ed.,
@ 100 Hz RTI, nV / Hz 6.6
DC supply current, µA 9.2
No signal dissipation, µW 27.6
GBW, kHz 320
As expected, the voltage gain for this op amp is high, the
bandwidth is low, and the dc power supply current is low.
A phase margin of 95◦ guarantees stability. Although the
bandwidth is somewhat low, this high gain op amp would
perform sufficiently well for many high-gain, low-frequency,
biomedical applications. The voltage gain varies from 106
dB to 112 dB over the process corners with a temperature
variation from -5◦ C to 80◦ C.
The chip area for this op amp is reduced considerably by
eliminating the need for a compensating capacitance. The
layout of the core op amp, not including the load or the
bond pads, is shown in Fig. 6. The chip area required is
approximately 0.034 mm2 (192 µm × 180µm) compared to
0.05mm2 for the compensated op amp of Fig. 2 that uses
a 3.5 pF capacitor for compensation.
VI. Conclusion
This work demonstrates the feasibility of the composite cas-
code connection, operating in the subthreshold region, for
the input differential stage of an op amp. The resulting am-
plifier has a high gain and low bandwidth while eliminating
the need for the addition of a compensation capacitor. It
also has reduced chip area, low nonlinear distortion, and
low noise. A natural application of such amplifiers is in the
603
realization of amplifier arrays in low-frequency biomedical
measurements.
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