INT. J. ELECTRONICS, VOL. 91, NO.

8, AUGUST 2004, 491–502

The utility of the composite cascode in analog CMOS design

DAVID J. COMER*y, DONALD T. COMERy and CRAIG S. PETRIEy

This work demonstrates the utility of the composite cascode stage by considering
its use (1) as a high-gain amplifying stage; (2) as a high-impedance load for an
amplifying stage; and (3) as a low-impedance, high-frequency summing circuit.
A simulation of the summing circuit using 0.18 mm channel lengths leads to a rise
time of less than 30 ps and good linearity. When used as a high-gain amplifier, both
devices of the active cascode stage must be biased into the active region. In the
summing circuit, one device is biased into the triode region whereas the second
device must operate in the active region. Guidelines for achieving proper bias with
a single bias source are provided in this work.

1. Introduction
The standard cascode circuit (Gray et al. 2001) of figure 1 has been a useful
configuration in CMOS circuit design for many years. Figure 2 shows the composite
cascode circuit that is suggested as a replacement for the standard circuit in some
circuit design applications. The composite cascode requires only a single bias source,
compared to two bias sources for the standard cascode. It can also be used as a low
input impedance summing circuit if the inputs are applied to the junction of the drain
of device M1 and the source of M2 (Comer et al. 2003a). Other possible advantages
include layout compactness and large active region size.
Various aspects and applications of this stage have been reported in previous
articles (Galup-Montero et al. 1994, Jaussi et al. 1999, Rajput and Jamuar 2002).
Furthermore, some variations of this circuit have been reported wherein an addi-
tional device is added to produce a voltage level shift between the gates of devices
M1 and M2 (Sackinger and Guggenbuhl 1990, Coban and Allen 1994). However, the
effects on overall circuit performance with M1 operating in the active (saturation)
region as against operation in the triode region and M2 in the subthreshold region
have not been reported. This mode of operation leads to much higher voltage gains
and higher output impedances. In addition, the possibility of using the junction of
the drain of M1 and the source of M2 (point a in figure 2) as a low-impedance input
to the stage has not been considered.
The composite cascode can approach the high voltage gains of the standard
cascode stage, but offers a configuration that is comparable to a simple common-
source stage. The composite cascode requires only one bias voltage to put both
devices in appropriate regions. For high-gain amplifying stages, the input signal is
applied to the gates of both devices and each device exhibits gain.

Received 21 July 2003. Accepted 30 July 2004.

* Corresponding author. E-mail: comer@ee.byu.edu
y Department of Electrical and Computer Engineering, Brigham Young University,
Provo, UT 84602, USA.

International Journal of Electronics ISSN 0020–7217 print/ISSN 1362–3060 online # 2004 Taylor & Francis Ltd
http://www.tandf.co.uk/journals
DOI: 10.1080/00207210412331314196
492 D. J. Comer et al.

Figure 1. A cascode stage.

Device M2 is always operated in the active region whereas M1 can be biased in

the triode region for medium gains and bandwidths or in the active region for high
gains and low bandwidths. The high-frequency summing circuit reported in this
work also biases M1 in the triode region with M2 strongly inverted in the active
region.
The configuration of figure 2 leads to several useful features in CMOS amplifier
design:
(1) While the composite cascode stage with M1 in the triode region is similar to
the common-source stage, it leads to higher voltage gains. This gain can be
controlled by the relative aspect ratios of the two devices.
(2) If M1 is placed in the active region, the voltage gain can be increased,
approaching that of the cascode stage, but the composite cascode uses only
one bias source. This can reduce the complexity of the bias circuit design. For
high voltage gain, the aspect ratios and the drain current must be chosen so
that both devices are in their active regions with device M2 operating in the
subthreshold region.
(3) Although the bandwidth may be lower than that of the standard cascode
stage, this is an advantage in dominant pole compensation of op amp circuits.
This popular method of compensation adds a shunt capacitance to the output
 Composite cascode in CMOS design 493

Figure 2. The active cascode stage.

terminals of the first stage of the op amp. A smaller capacitor, occupying less
chip area, can be used for the composite cascode input stage.
(4) Since the composite cascode stage presents a higher output impedance than a
simple stage, it can serve as the load impedance of a high-gain amplifier stage.
(5) When the input signal is applied to the drain of M1 and the source of M2
(point a of the circuit in figure 2) rather than the gates, it presents a very low
input impedance to the input signal, if properly biased. This allows the input
to be a summing node for several currents while generating only a small input
voltage (Comer et al. 2003a, 2003b). This summed current can then be con-
verted to a proportional output voltage.

2. The composite cascode amplifier

The composite cascode stage of figure 2 can replace the simple common-source
stage in some amplifying applications. The midband voltage gain of the common
source stage with a current source load is
AMB ¼
gm rds ð1Þ
where gm is the transconductance and rds is the drain-to-source resistance of the
device at the bias point used.
494 D. J. Comer et al.

The voltage gain for the composite cascode stage is

AMB ¼
½gm1 rds1 þ gm2 rds2 þ gm1 rds1 ðgm2 þ gmb2 Þrds2  ð2Þ
where gmb2 accounts for the body effect of M2. This expression can be approximated
within 10% by
AMB ¼
½gm1 rds1 ðgm2 þ gmb2 Þrds2  ð3Þ
Equation (3) generally results in a number that is larger than that of (1), when
M1 is in the triode region, even though both gm1 and rds1 are small. For devices of
comparable size, the voltage gain of the composite cascode stage with M1 in the
triode region may exceed that of the common-source stage by 40%. The voltage
gain–bandwidth product or GBW is similar for both configurations.
To achieve high voltage gains, device M1 is given a much smaller aspect ratio
than that of M2. This allows device M1 to operate in the active region at low drain
currents, increasing rds1. Although gm1 decreases with decreasing drain current, this
falloff is less than the increase in rds1. As device M2 enters the weak inversion or
subthreshold region, the overall product of (gm2 þ gmb2) and rds2 is approximately
constant with drain current (Comer and Comer 2004). As shown by (3), the voltage
gain will increase at lower drain currents as the product gm1rds1 increases and the
product (gm2 þ gmb2) rds2 remains constant. Figure 3 shows the simulated voltage
gain of the composite cascode of figure 2 as a function of drain current for various
aspect ratios. In each case W1/L1 ¼ 5/1, but W2/L2 takes on the values of 20/1, 40/1
and 80/1. The power supply voltage used in these simulations is VDD ¼ 5 V. A Spice
simulator using BSIM3v3 models was used to obtain these curves.
The voltage gain is seen to increase as drain current decreases over the entire
range of current for all aspect ratios; however, the increase is much greater as device

Figure 3. Gain of an active cascode as a function of drain current for

various values of W2/W1.
 Composite cascode in CMOS design 495

M1 moves into the active region and device M2 begins subthreshold operation.
For this situation, the voltage gains far exceed those of the common-source stage.
For example, at drain currents of 8 mA, the common-source stage with an aspect
ratio of 40/1 and an ideal current source load has a voltage gain of
200 V/V
whereas the composite cascode stage gain with W2/L2 ¼ 40/1 is about
4800 V/V.
For a drain current of 1 mA, the composite cascode gain nears
12 000 V/V and can
reach much higher values as drain current decreases.
Figure 3 also indicates that voltage gain increases as W2/L2 increases. For a
drain current of 2 mA, the amplifier with W2/L2 ¼ 20/1 has a gain of 5543 V/V, the
amplifier with an aspect ratio of 40/1 has a gain of 9696 V/V, and the aspect ratio of
80/1 results in a gain of 12 451 V/V.
For a power supply of 5 V, the output active region extends from about 1 V to
5 V. The composite cascode with W2/L2 ¼ 80/1 exhibits a total harmonic distortion
of 2.6% with a peak-to-peak output voltage of 1.2 V and a quiescent drain current of
2 mA. The overall voltage gain at this bias is 12 451 V/V.
Whereas the Miller effect leads to a high input capacitance for the composite
cascode stage, the conventional cascode minimizes the Miller effect. This is often
a minor consideration in the design of high-gain stages since the upper corner fre-
quency is often determined by the output resistance and capacitance. The active
cascode and the conventional cascode have such large output resistances that the
output corner frequency is generally determined by the output circuit in both cases.

3. The composite cascode as a load

A composite cascode using p devices can be used as a load for an amplifying
stage. Figure 4 shows a circuit employing the composite connection for both gain
and load sections of an amplifying stage. The p-cascode has a very high output
impedance since device M4 has the resistance of device M3 as a source resistance.
If M3 is in the active region, the output impedance looking into the drain of M4 is
quite high (Jaussi et al. 1999, Rajput and Jamuar 2002).
The gain of the amplifier of figure 4 was found from simulation to be
1158 V/V
with a drain current of 4 mA. When M3 is removed, leaving M4 as a simple common-
source stage, the voltage gain drops by a factor of 13.5 to 85.9 V/V. Either load
requires only a single bias source. This configuration has been used for the differ-
ential input stages of a rather simple op amp with open loop gains exceeding
50 000 V/V (Jaussi et al. 1999).
As explained earlier, dominant pole compensation of an op amp is generally
accomplished by adding a capacitor to the output terminals of the differential
input stage. Since the output impedance of the stage of figure 4 is high, the additional
capacitance to set the dominant pole location is small.

4. The composite cascode in a summing circuit

In low-frequency applications, summing is often done by an op amp with a
virtual ground summing node. Several wireless communication systems or high-
speed digital communication systems using transmission line channels require higher
frequency summing circuits. For example, a CMOS linear equalizer for a 10 GHz
digital channel dictates that an alternative approach be used, since CMOS op amps
do not operate in this range of frequency.
496 D. J. Comer et al.

Figure 4. Active cascode stage with active cascode load.

This type of application calls for a circuit that responds very quickly to the
current changes of the multiple inputs. It must sum the circuits accurately and
do so without requiring a large input voltage. Power supply voltages for the
small-channel devices necessary to achieve the requisite switching speeds are quite
low. This limits the active region sizes of the circuits that drive the summing circuit
input. Consequently, a low input impedance for the current summer is essential.
The composite cascode amplifier of figure 2 offers the advantages of high voltage
gain, low headroom and ease of bias. The input signal is applied simultaneously
to the gates of M1 and M2 in most amplifying applications. Unfortunately, the
frequency response of this circuit is poor and the high input impedance precludes
the use of the input node as a summer.
The circuit of figure 5 was developed to satisfy the high-speed current summing
specifications of a 10 GHz linear equalizer (Comer et al. 2003a, 2003b). It is a differ-
ential input, double-ended output summing circuit based on the composite cascode
stage. Stages M1/M5 and M2/M6 form composite cascodes; however, the multiple
current inputs to be summed are applied to the sources of M1 and M2 and the drains
 Composite cascode in CMOS design 497

Figure 5. A summing circuit using the active cascode.

of M5 and M6 rather than the gates. Devices M3 and M4 are diode-connected

load stages. All devices have a channel length of 0.18 mm. The power supply is
VDD ¼ 1.6 V.
In this configuration, the single bias voltage along with the proper aspect ratio
force devices M5 and M6 into their triode regions while devices M1 and M2 are in
their active regions. The input signal sees an input impedance determined by the
parallel combination of impedance looking into the source terminal of the active
device and the drain-to-source resistance of the triode device. This impedance at the
Iþ input is given by
Rin ¼ rds5 k 1=gm1 ð4Þ
The resistance rds5 can be written as (Comer and Comer 2002)
1
rds5 ¼ ð5Þ

Cox ðW5 =L5 ÞðVGS5
VT Þ
The reciprocal of this equation equals the transconductance of the device in the
active region. For equal ratios of W/L on devices M1 and M5, the resistance rds5
is approximately equal to 1/gm1. This results in a low value of input impedance,
expressed as
1
Rin  ð6Þ
2gm1
The low input impedance allows relatively large currents to be summed at the input
node while generating only a small input voltage. This minimizes the reduction of
active region size for the product circuits that are connected to the summer inputs.
498 D. J. Comer et al.

The input current splits into two approximately equal components, with one-half
the total input current becoming the drain current of device M1. This current devel-
ops a voltage across the diode-connected load that is proportional to the sum of the
input currents.
Although the transient response of the composite cascode amplifier is poor, the
response of the summing circuit is excellent as a result of (1) the elimination of the
Miller effect on input capacitance resulting from a noninverting input stage and
(2) the small resistance presented to the output by the diode-connected loads. The
W/L ratio for devices M3/M4 is small, to minimize input capacitance, while the
resistive load presented by these stages is again 1/gm.
The voltage gain of this circuit is low, determined by the ratio of channel widths
of devices M1 and M3 (Comer et al. 2003b). This factor is generally unimportant in
current-summing applications. The summed input current splits equally between the
two devices of the composite cascades and the currents through M1 and M2 flow
into the load devices M3 and M4, developing a differential output voltage.
It is also possible to replace the load devices with pMOS current mirrors, as
shown in figure 6. In this circuit, the output differential current is a scaled version
of the sum of the input currents. Again, the load impedance presented to devices M1
and M2 will be small since the current mirror inputs are diode connected. The output
current can be scaled to the desired levels by selection of device sizes in the two
current mirrors.
A summary of the advantages of the circuit of figure 5 in summing applications
follows:
(1) It requires only one bias voltage to put M1/M2 in the active region and
M5/M6 in the triode region.

Figure 6. Summing circuit with current mirror outputs.

 Composite cascode in CMOS design 499

(2) It offers low input impedance, due to triode region operation of M5/M6,
and low impedance looking into the sources of M1/M2. This leads to low
input voltages that only slightly reduce the active regions of the driving
devices.
(3) It will operate at high frequencies since it has low input capacitance and low
output resistance.
(4) It operates linearly with input current over a large range of input current.

5. Biasing the composite cascode stage

For high-gain stages, the composite cascode should operate with both devices
in their active regions. Device M2 should operate in the subthreshold region with
VGS2 slightly less than its threshold voltage. With M1 having a smaller aspect ratio
than that of M2, sufficient drain current flows through M1 to keep this device
strongly inverted. Only strongly inverted devices will be considered in the following
considerations.
The requirement for input impedance in the summer circuit is satisfied by
operating M1 in its triode region while M2 remains in the active region.

5.1. Biasing M1 in the triode region

The summing circuit of figure 5 requires that M1 operate in the triode region. In
general, to bias the composite cascode so that M2 is in the active region and M1 is in
the triode region, the aspect ratio of M1 should be greater than or equal to that of
M2. If the lengths and threshold voltages of the two devices in figure 2 are assumed
equal and body effect and channel length modulation are neglected, the drain-to-
source voltage of M1 can be expressed as
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi!
1
VDS1 ¼ Veff 1
1
ð7Þ
1 þ W1 =W2

where Veff1 ¼ VGG
VT, VT being the threshold voltage, W1 is the channel width
of M1, and W2 is the channel width of M2. The gate-to-source voltage of device M2
is then
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
1
VGS2 ¼ VGG
VDS1 ¼ VT þ Veff1 1
ð8Þ
1 þ W1 =W2
For a ratio of W1/W2 larger than 1, it is easy to apply a bias voltage, VGG,
that puts M2 in the active region and M1 in the triode region. For example, if
W1/W2 ¼ 1, values of VGG ¼ 1.06 V and VT ¼ 0.86 V lead to VDS1 ¼ 0.059 V and
VGS2 ¼ 1.001 V. At 0.059 V, the drain voltage of device M1 is less than the pinchoff
value of 0.2 V.

5.2. Biasing M1 in the active region

For a high-gain amplifier stage, both devices must operate in their active regions.
In order to bias both devices into their active regions, the aspect ratio of M1 is
selected to be considerably smaller than that of M2. Drain current must then be
chosen low enough to result in active region operation of M1.
500 D. J. Comer et al.

It can be shown that a square-law device will put M1 at the edge of the triode and
active regions if
sffiffiffiffiffiffiffi
W2
VGG ¼ VT1 þ ðV
VT2 Þ
W1 T1

Lower values of VGG lead to increased values of VDS1 and ensure that M1 is in its
active region.
For submicron devices, the drain current varies as (VGS
VT)n where n ranges
from about 1 for very short channel devices, for example L ¼ 0.18 mm, toward 2 as
the channel length exceeds 1 mm (Sakurai and Newton 1990).
Since VGD1 ¼ VGS2, the requirement that VGD1<VT1 to place M1 in its active
region also results in VGS2<VT1. Although VT1 and VT2 are not identical, these
values are close enough so that subthreshold operation for M2 occurs as VGG is
lowered to the point required to put M1 in the active region. The values of
VGG that bias M1 into its active region lead to relatively small current densities
through the larger device, M2. Subthreshold operation of device M2 leads to even
higher voltage gains than those for operation in strong inversion (Comer and Comer
2004).

6. Circuit simulations
The current summing circuit of figure 5 was simulated for CMOS with a process
channel length of 0.18 mm (actual length 0.16 mm). While all devices used this same
channel length, the widths were W1 ¼ W2 ¼ W5 ¼ W6 ¼ 16 mm and W3 ¼ W4 ¼
1 mm. This circuit formed the summing circuit for a linear equalizer.
A bias voltage of 0.7 V led to a quiescent current through each leg of the circuit of
about 990 mA. The inputs to the summer were driven by linear sweeps of Imþ ¼ 0 to
Imax and Iin
¼ I max to 0. The three values of Imax used were 400 mA, 800 mA and
1200 mA.
Figure 7 shows the double-ended output voltage for Imax of 400 mA and the input
voltage for this input current. The slope linearity, found by comparing the slope
over the first one-sixth of the curve to the total average slope, is 0.18%. The input
voltage varies from 176 mV to 207 mV over this sweep, an incremental change of
31 mV.
For an input sweep between 0 and 800 mA, the slope linearity was 1.3%. It should
be noted that end-point linearity, an often-used figure for nonlinearity, is about one-
half of this value. When Imax was increased to 1200 mA, the slope linearity degraded
to 7.3%.
Table 1 summarizes the results of the linearity measurements. The error for a
current sweep of 800 mA is linear to within 1.3%. This met the specifications for this
circuit. The nonlinearity for a sweep of 1200 mA is considerably larger.
A transient response was then generated using a quiescent input current of
200 mA. A 100 ps pulse of þ100 mA was then applied to one input while a pulse of

100 mA was applied to the other input. The transient response of the output voltage
is shown in figure 8. This 37 mV output reached 98% of its final value in 30 ps. With
this small transient response time, the overall linear equalizer can form the products
and sum these values within the 100 ps requirement.
 Composite cascode in CMOS design 501

Figure 7. (a) Output voltage of summer for linear input current sweep. (b) Input voltage
to summer.

Max. current, mA Slope lin., %

400 0.18
800 1.3
1200 7.3

Table 1.

7. Conclusions
The composite cascode circuit can be used for very high gain stages such as those
utilized as input stages for op amp circuits. If biased properly, the gains can exceed
10 000 V/V for low drain currents and ideal current source loads. The stage can also
serve as a load to produce practical gains in the range of thousands.
The use of the composite cascode circuit with input applied to the source of the
amplifying device leads to a low input impedance summing circuit with excellent
transient response and good linearity over a wide range of current inputs. The load
devices can also be replaced by current mirrors to produce a differential output
current that is a scaled version of the sum of the input currents.
502 D. J. Comer et al.

Figure 8. Transient response of summer with an input pulse of 100 ps duration.

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