6.

Hands-on: System Design with ARM

6.1. ARM programmers model

6.2. ARM instruction set
6.3. Operating modes & exceptions

Design & Test of Systems-on-a-Chip Winter 2000/2001 1

6.1 The ARM Programmers´ Model

! ARM is a Reduced Instruction Set Computer
(RISC)
! a large, regular register file

! any register can be used for any purpose

! a load-store architecture
! instructions which reference memory just move
data, they do no processing
! processing uses values in registers only
! fixed-length 32-bit instructions

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 ARM register organization
ro
r1 usable in user mode
r2
system modes only
r3
r4
r5
r6
r7
r8_fiq
r8
r9_fiq
r9
r10_fiq
r10
r11_fiq
r11 r13_und
r12_fiq r13_irq
r12 r13_abt
r13_svc r14_und
r13_fiq r14_irq
r13 r14_abt
r14_svc
r14_fiq
r14
SPSR_und
R15 (PC) SPSR_irq
SPSR_abt
SPSR_svc undefined
SPSR_fiq irq
CPSR abort mode
svc mode
fiq mode
mode
mode
user mode

Design & Test of Systems-on-a-Chip Winter 2000/2001 3

ARM CPSR (Current Program Status

Register) format
31 28 27 8 7 6 5 4 0

NZCV unused I F T mode

! In user programs only the top 4 bits of the CPSR

are relevant

! N - the result was negative

! Z - the result was zero
! C - the result produced a carry out
! V - the result generated an arithmetic overflow

! I, F – interrupt enable bits

! T – instruction set (Thumb/ARM)
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 ARM memory organization
! Memory is a linear array
of 232 byte locations.
23 22 21 20
! ARM can address:
19 18 17 16 ! individual bytes
----------------- word 16----------------
! 32-bit words on 4-byte
15 14 13 12

half-word 14 half-word 12 boundaries

11 10 9 8 ! some ARM chips can
----------------word 8-------------------
address 16-bit half-
7 6 5 4
byte 6 half-word 4 words on 2-byte
3 2 1 0 boundaries
byte3 byte2 byte1 byte0

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The ARM instruction set

a) Data processing instructions
b) Data transfer instructions
c) Control flow & conditional execution
d) Special instructions

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 a) Data processing instructions
! ALL operands are 32-bits wide and either:
! come from registers, or
! are literals (´immediate´ values ) specified in the
instruction
! The result, if any, is 32-bits wide and goes
into a register
! except long multiplies generate 64-bit results
! All operand and result registers are specified
independently

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Arithmetic operations

ADD r0, r1, r2 ; r0 := r1 + r2

ADC r0, r1, r2 ; r0 := r1 + r2 + C
SUB r0, r1, r2 ; r0 := r1 - r2
SBC r0, r1, r2 ; r0 := r1 - r2 + C - 1
RSB r0, r1, r2 ; r0 := r2 - r1
RSC r0, r1, r2 ; r0 := r2 - r1 + C - 1

! C is the Carry bit in the CPSR

! the operation may be viewed as unsigned or
2´s complement signed

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 Bit-wise logical operations

AND r0, r1, r2 ; r0 := r1 and r2

ORR r0, r1, r2 ; r0 := r1 or r2
EOR r0, r1, r2 ; r0 := r1 xor r2
BIC r0, r1, r2 ; r0 := r1 and not r2

! the specified Boolean logic operation is

performed on each bit from 0 to 31
! BIC stands for ´bit clear´
! each ´1´ in r2 clears the corresponding bit in r1

Design & Test of Systems-on-a-Chip Winter 2000/2001 9

Register movement operations

MOV r0, r2 ; r0 := r2
MVN r0, r2 ; r0 := not r2

! MVN stands for ´move negated´

! there is no first operand specified as these
are unary operations

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 Comparison operations

CMP r1, r2 ; set cc on r1 - r2

CMN r1, r2 ; set cc on r1 + r2
TST r1, r2 ; set cc on r1 and r2
TEQ r1, r2 ; set cc on r1 or r2

! these instructions just affect the condition

codes (N, Z, C, V) in the CPSR
! there is no result register

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Immediate operands
! the 2nd source operand (r2) may be replaced
by a constant:

ADD r3,r3, #1 ; r3 := r3 + 1
AND r8,r7, #&ff ; r8 := r7 [7:0]

! # indicates an immediate value

! & indicates hexadecimal notation
! allowed immediate values are (in general):
(0 … 255) x 22n

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 Shifted register operands
! the 2nd source operand may be shifted
! by a constant number of bit positions:
ADD r3, r2, r1, LSL #3 ; r3 := r2 + 8*r1

! or by a register-specified number of bits:

ADD r5, r5, r3, LSL r2 ; r5 += 2r2*r3

! LSL, LSR mean ´logical shift left / right´

! ASL, ASR mean ´arithmetic shift left / right´
! ROR means ´rotate right´
! RRX means ´rotate right extended´

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ARM shift operations

31 31

00000 00000
LSL #5 LSR #5

31 0 31 0
0 1

00000 0 11111 1
ASR #5, positive operand ASR #5, negative operand

31 0 31 0
C

C C
ROR #5 RRX

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 Setting condition codes
! All data processing instructions may set the
condition codes
! ’S’ means “set condition codes”
! Example : 64–bit addition

ADDS r4,r2,r0 ; 32-bit carry-out -> C

ADC r5,r3,r1 ; added into top 32 bits

! Comparison operations always (and only)

change the condition codes

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Multiplication
! ARM has special multiply instructions
MUL r4, r3, r2 ; r4 := (r3 *r2)[31:0]
! only the least significant 32 bits are returned
! immediate operands are not supported
! ´multiply-accumulate´:
MLA r4, r3, r2, r1 ; r4 := (r3*r2+r1)[31:0]

! some ARMs support 64-bit result forms

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 Data processing instructions - Summary
Opcode Mnemonic Meaning Effect
[24:21]
0000 AND Logical bit-wise AND Rd:= Rn AND Op2
0001 EOR Logical bit-wise exclusive OR Rd:= Rn EOR Op2
0010 SUB Subtract Rd:= Rn - Op2
0011 RSB Reverse subtract Rd:= Op2 - Rn
0100 ADD Add Rd:= Rn + Op2
0101 ADC Add with carry Rd:= Rn + Op2 + C
0110 SBC Subtract with carry Rd:= Rn - Op2 + C - 1
0111 RSC Reverse subtract with carry Rd:= Op2 - Rn + C - 1
1000 TST Test Scc on Rn AND Op2
1001 TEQ Test equivalence Scc on Rn EOR Op2
1010 CMP Compare Scc on Rn - Op2
1011 CMN Compare negated Scc on Rn + Op2
1100 OPR Logical bit-wise OR Rd:= Rn OR Op2
1101 MOV Move Rd:= Op2
1110 BIC Bit clear Rd:= Rn AND NOT Op2
1111 MVN Move negated Rd:= NOT Op2

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Data processing instructions - Encoding

31 28 27 26 25 24 21 20 19 16 15 12 11 0
cond 00 # opcode S Rn Rd operand 2

destination register
first operand register
set condition codes
arithmetic/logic function

25 11 8 7 0
1 # rot 8-bit immediate

immediate alignment
11 7 6 5 4 3 0
# shift Sh 0 Rm
immediate shift length
25 shift type
0 second operand register
11 8 7 6 5 4 3 0
Rs 0 Sh 1 Rm

register shift length

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 Multiply instructions - Encoding
31 28 27 24 23 21 20 19 16 15 12 11 8 7 4 3 0
cond 0000 mul S Rd / Rd Hi Rn / Rd Lo Rs 1001 Rm

MUL {<cond>} {S} Rd, Rm, Rs

MLA {<cond>} {S} Rd, Rm, Rs, Rn
<mul> {<cond>} {S} RdHi, RdLo, Rm, Rs

Opcode Mnemonic Meaning Effect

[23:21]
000 MUL Multiply (32-bit result) Rd:= (Rm*Rs)[31:0]
001 MLA Multiply-accumulate (32-bit result) Rd:= (Rm*Rs+Rn )[31:0]
100 UMULL Unsigned multiply long RdHi:RdLo := Rm*RS
101 UMLAL Unsigned multiply-accumulate long RdHi:RdLo += Rm*RS
110 SMULL Signed multiply long RdHi:RdLo := Rm*RS
111 SMLAL Signed multiply-accumulate long RdHi:RdLo += Rm*RS

Design & Test of Systems-on-a-Chip Winter 2000/2001 19

b) Data transfer instructions

! 3 types of data transfer instructions:
! single register loads and stores
! byte or word (or possibly half-word) transfers
! multiple register loads and stores
! less flexible, multiple words, higher transfer
rate
! single register-memory swap
! mainly for system use

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 Single register load / store
! 32 bit
LDR r0, [r1] ; r0 := mem [r1]
STR r0, [r1] ; mem [r1] := r0

! 8 bit
LDRB r0, [r1] ; r0 := mem [r1] [7:0]
STRB r0, [r1] ; mem [r1] [7:0] := r0

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Address Specification
! Register – indirect with displacement
LDR r0,[r1, #4] ; r0 := mem[r1+4]
! The offset must be within +/- 4 kBytes

! Special case : register indirect

LDR r0, [r1] ; r0 := mem[r1]
! Required: a register initialized with an address close
to the target
! Immediate values are restricted to (0…255)*22n
! Assembler: pseudo instruction ADR is replaced automatically
by appropriate processor instructions
ADR r1, TABLE1 ; r1 points to TABLE1
...
TABLE1 ... ; LABEL

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 Updating the address register
! Auto - indexing
LDR r0,[r1, #4] ! ; r0 := mem[r1+4]
; r1 := r1 + 4
Write effective address back to base register
! Post - indexing
LDR r0, [r1], #4 ; r0 := mem[r1]
; r1 := r1 + 4

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Multiple register loads and stores

LDMIA r1,{r0, r2, r5} ; r0 := mem [r1]

; r2 := mem [r1+4]
; r5 := mem [r1+8]
! the {..} list may contain any or all of r0 - r15
! including r15 (the PC!) will cause a branch
! the lowest register always uses the lowest
address

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 Block copy adressing
! Addresses can be
! incremented or decremented
! before or after
each transfer
! May be used to implement stacks

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Examples
r 9´ 101816 r 9´ r5 101816
r5 r1
r1 r0
r9 r0 100c16 r9 100c16

100016 100016

STMIA r 9!, {r 0, r 1, r 5 } STMIB r 9!, {r 0, r 1, r 5 }

101816 101816

r9 r5 100c16 r9 100c16
r1 r5
r0 r1
r 9´ 100016 r 9´ r0 100016

STMDA r 9!, {r 0, r 1, r 5 } STMDB r 9!, {r 0, r 1, r 5 }

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 Encoding - single word and unsigned byte data
transfer instructions

31 28 27 26 25 24 23 22 21 20 19 16 15 12 11
0 cond 01 # P U B W L Rn Rd offset

source/destination register
base register
load/store
write-back (auto-index)
unsigned byte/word
up/down
pre-/post-index

25 11 0
0 12-bit immediate

25 11 7 6 5 4 3
1 0 # shift Sh 0 Rm

immediate shift length

shift type
offset register

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Encoding - half-word and signed byte

data transfer instructions

31 28 27 25 24 23 22 21 20 19 16 15 12 11 8 7 6 5 4 3 0
cond 000 P U # W L Rn Rd offset H 1 S H 1
offsetL
source/destination register
base register
load/store
write-back (auto-index)
up/down
pre-/post-index

11 8 3 0
1
22 Imm7:4] Imm[3:0]

22 11 8 3 0
0 0000 Rm

offset register

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 Encoding - multiple register data transfers

31 28 27 25 24 23 22 21 20 19 16 15 0
cond 100 P U S W L Rn register list

base register
load/store
write- back (auto-index)
restore PSR and force user bit
up/down
pre-/post-index

Assembler format:
LDM | STM {<cond>} <add> Rn {!}, <regs>
<add> = IA etc, <regs> = {rn,..rm}
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Swap memory and register instructions

31 28 27 23 22 21 20 19 16 15 12 11 43 0
cond 0 0 0 1 0 B 0 0 Rn Rd 00001001 Rm

destination register

base register source

register
unsigned
byte/word

Assembler format:
SWP {<cond>} {B} Rd, Rm, [Rn]

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 c) Control flow instructions
! Unconditional branches
B LABEL
.. ; these instructions are skipped
LABEL ..

! Conditional branches
MOV r0, #0 ; initialize counter
LOOP ...
ADD r0, r0, #1 ; increment counter
CMP r0, #10 ; compare with limit
BNE LOOP ; repeat if not equal
... ; else continue
! here the branch depends on how CMP sets Z

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Branch conditions
Branch Interpretation Normal Uses

B Unconditional Always take this branch

BAL Always Always take this branch
BEQ Equal Comparison equal or zero result
BNE Not equal Comparison not equal or zero result
BPL Plus Result positive or zero
BMI Minus Result minus or negative
BCC Carry clear Arithmetic operation did not give carry-out
BLO Lower Unsigned comparison gave lower
BCS Carry set Arithmetic operation gave carry-out
BHS Higher or same Unsigned comparison gave higher or same
BVC Overflow clear Signed integer operation ; no overflow occurred
BVS Overflow set Signed integer operation ; overflow occurred
BGT Greater than Signed integer comparison gave greater than
BGE Greater or equal Signed integer comparison gave greater or equal
BLT Less than Signed integer comparison gave less than
BLE Less or equal Signed integer comparison gave less than or equal
BHI Higher Unsigned comparison gave higher
BLS Lower or same Unsigned comparison gave lower or same

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 Conditional execution
! All instructions may be conditional:
CMP r0, #5 ; if (r0 != 5) {
ADDNE r1, r1, r0 ; r1 := r1 + r0 - r2
SUBNE r1, r1, r2 ; }

! May improve performance and code

density

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ARM condition codes

Opcode Mnemonic Interpretation Status flag state for
[31:28] extension execution
0000 EQ Equal / equals zero Zset
0001 NE Not equal Zclear
0010 CS/HS Carry set / unsigned higher or same Cset
0011 CC/LO Carry clear / unsigned lower Cclear
0100 MI Minus / negative Nset
0101 Pl Plus / positive or zero Nclear
0110 VS Overflow Vset
0111 VC No overflow Vclear
1000 HI Unsigned higher Cset and Zclear
1001 LS Unsigned lower or same Cclear or Zset
1010 GE Signed greater than or equal N equals V
1011 LT Signed less than N is not Equal to V
1100 GT Signed greater than Z clear and N equals V
1101 LE Signed less than or equal Z set or Nis not equal to V
1110 AL Always any
1111 NV Never (do not use!) none

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 Branch and link
! ARM´s subroutine call mechanism
! Saves the return address in r14
BL SUBR ; branch to SUBR
... ; return to here
SUBR ... ; subroutine entry point
MOV pc, r14 ; return

! Note: Data processing instruction for

return

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Nested subroutines
! r14 must be saved before the next BL
BL SUB1 ; branch to SUB1
...
SUB1 STMDA r13!, {r0-r2, r14}; save regs
BL SUB2
...
LDMIB r13!, {r0-r2, pc} ; restore regs + return
SUB2 ...
MOV pc, r14 ; return

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 Software Interrupt
! Assembler format:
SWI {<cond>} <24-bit immediate>

! The instruction:
! puts the processor into supervisor mode
! saves the CPSR in SPSR_svc
! sets the PC to 0x8
! Typically used for calls to operating system
functions, e.g.:
SWI SWI_WriteC ; output character in r0
SWI SWI_Exit ; return to monitor

Design & Test of Systems-on-a-Chip Winter 2000/2001 37

Branch and Exchange

Assembler format:
BX {<cond>} Rm

! used to switch execution to the Thumb

instruction set (see later)
! causes a branch to the address in Rm

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 Instruction encoding
31 28 27 25 24 23 0
B, BL cond 1 0 1 L 24-bit signed word offset

! the L bit selects Branch with Link

! the offset is scaled to word
! giving a range of +/-32 Mbytes

31 28 27 4 3 0
BX cond 0 0 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 Rm

31 28 27 24 23 0
SWI cond 1111 24-bit ( interpreted ) immediate

Design & Test of Systems-on-a-Chip Winter 2000/2001 39

d) Special instructions
! Transfer between status register & general
register
MRS{<cond>} Rd, CPSR | SPSR
MSR{<cond>} CPSR | SPSR, #<imm.> | Rm
! Coprocessor instructions
! Data operations
! Depend on coprocessor
! Data transfers, e.g.
LDC p6, c0, [r1]
STC p4, c1, [r2, #4]!
! Register transfers
! More a 32-bit value between the processor and ARM
(including CPSR)

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 6.3. Operating modes and exceptions

! ARM has privileged operating modes:

! SVC mode for software interrupts
! IRQ mode for (normal) interrupts
! FIQ mode for fast interrupts
! Abort mode for handling memory faults
! Undef mode for undefined instruction traps
! System mode for privileged operating system
tasks

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Each privileged mode has:

! some private registers
! its own r14 for a return address
! its own r13, normally for a private stack pointer
! FIQ mode has additional private registers to speed
up its operating
! its own Saved Program Status Register (SPSR)
! to preserve the CPSR so it can be restore upon
return

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 Registers and modes
ro
r1 usable in user mode
r2
system modes only
r3
r4
r5
r6
r7
r8_fiq
r8
r9_fiq
r9
r10_fiq
r10
r11_fiq
r11 r13_und
r12_fiq r13_irq
r12 r13_abt
r13_svc r14_und
r13_fiq r14_irq
r13 r14_abt
r14_svc
r14_fiq
r14
R15 (PC) SPSR_und
SPSR_irq
SPSR_abt
CPSR SPSR_svc undefined
SPSR_fiq irq
abort mode
svc mode
fiq mode
user mode mode
mode

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The CPSR and SPSR format

31 28 27 87 65 4 0
NZCV unused IF T mode

! bits 0 to 4 define the operating mode

! bit 5 controls the instruction set
! ARM (T=0) or Thumb (T=1)
! bit 6 disables FIQ when set
! bit 7 disables IRQ when set

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 Modes - Summary

CPSR [4:0] Mode Use Registers

10000 User Normal user code user
10001 FIQ Processing fast interrupts _fiq
10010 IRQ Processing standard interrupts _irq
10011 SVC Processing software interrupts (SWIs) _svc
10111 Abort Processing memory faults _abt
11011 Undef Handling undefined instruction traps _und
11111 System Running privileged operating system tasks user

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Exception entry sequence

! Change to the appropriate operating mode
! Save the return address in r14_exc
! Save the old CPSR in SPSR_exc
! Disable IRQ, FIQ (on FIQ entry)
! Force the PC to the appropriate exception
vector address

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 Exception vector addresses

Exception Mode Vector address

Reset SVC 0x00000000
Undefined instruction UND 0x00000004
Software interrupt (SWI) SVC 0x00000008
Prefetch abort (instruction fetch memory fault) Abort 0x0000000C
Data abort (data access memory fault) Abort 0x00000010
IRQ (normal interrupt) IRQ 0x00000018
FIQ (fast interrupt) FIQ 0x0000001C

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Return from exception

! from a SWI or undefined instruction:
MOVS pc, r14
! this is a special form with s and pc
! it restores the CPSR from SPSR_exc as well
! from an IRQ, FIQ or prefetch abort:
SUBS pc, r14, #4

! from a data abort to retry the data transfer:

SUBS pc, r14, #8

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 Memory faults

! Access may fail because of:

! virtual memory page faults
! memory protection violations
! soft memory errors
! Prefetch aborts are faults on instruction fetch
! Data aborts are faults on data transfers
! more difficult to handle than prefetch aborts

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25