EE247

Lecture 19
ADC Converters
• Sampling (continued)
– Sampling switch charge injection
• Complementary switch
• Use of dummy device
• Bottom-plate switching
– Track & hold circuits
– T/H circuit incorporating gain & offset cancellation
• ESD protection impact on converter performance
• ADC architectures
- Nyquist rate ADCs
- Oversampled ADCs

EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 1

Switch Charge Injection

Complementary Switch
φ1 VG
VH
Vi

φ1B
VL
t
φ1
φ1B

• In slow clock case if area of n & p devices are equal Æ effect of overlap capacitor
for n & p devices to first order cancel (matching n & p width and ΔL)

EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 2

 Switch Charge Injection
Complementary Switch
Fast Clock
Qc h − n = WnCo x Ln (VH −Vi − Vth − n )
VG
VH
Qc h − p = WpCo x Lp (Vi −VL − Vt h − p ) Vi

1⎛Q Q ⎞
Δ Vo ≈ ⎜ c h − p − c h − n ⎟
2 ⎜⎝ Cs Cs ⎟⎠ VL
t

Vo = Vi (1 + ε ) + Vos
φ1
1 W C L + WpCo x Lp
ε ≈ − × n ox n
2 Cs

• In fast clock case φ1B

ƒ Offset cancelled for equal device width
ƒ Input voltage dependant error worse!

EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 3

Switch Charge Injection

Dummy Switch
VG VGB
Vi VO VG VGB
VH
M1 M2
Vi
WM2=1/2WM1 Cs

VL
t

• Dummy switch same L as main switch but half W

• Main device clock goes low, dummy device goes high Æ dummy switch
acquires same amount of channel charge main switch needs to lose
• Effective only if exactly half of the charge transferred to M2 and requires
good matching between clock fall/rise

EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 4

 Switch Charge Injection
Bottom Plate Sampling
φ1b φ1a
VH
M1
VO VL
Vi φ1b
Cs

φ1a M2
t

• Switches M2 opened slightly earlier compared to M1

Æ Injected charge by the opening of M2 is constant & eliminated when
used differentially

• Since Cs bottom plate open when M1 openedÆ no charge injected on Cs

EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 5

Flip-Around Track & Hold

φ2

S2A φ1
φ1D
φ1D

φ1D φ2 S3 φ2
C
vIN
S1A S2 vOUT

φ1 S1 • Concept based on bottom-

plate sampling
vCM
EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 6
 Flip-Around T/H-Basic Operation
φ1Æhigh
φ2
φ1

S2A φ1D
φ1D
φ2
φ1D φ2 S3
C Charging C
vIN
S1A S2 vOUT

φ1 S1

vCM
EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 7

Flip-Around T/H-Basic Operation

φ2Æhigh
φ2
φ1
S2A
φ1D φ1D

φ2
φ1D φ2 S3
C Holding
vIN
S1A S2 vOUT

φ1 S1

vCM
EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 8
 Flip-Around T/H - Timing
φ2
φ1

S2A φ1D
φ1D
φ2

φ1D φ2 S3
C Sampling
vIN
S1A S2 vOUT

φ1 S1 S1 opens earlier than S1A

"Bottom Plate Sampling"
vCM
EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 9

Charge Injection
• At the instant of sampling, some of the
charge stored in sampling switch S1 is
dumped onto C
• With "Bottom Plate Sampling", charge
injection comes only from S1 and is to
first-order independent of vIN
– Only a dc offset is added This dc offset can
be removed with a differential architecture

EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 10

 Flip-Around T/H
Constant switch VGS φ2
to minimize distortion
S2A φ1
φ1D
φ1D

φ1D φ2 S3 φ2
C
vIN
S1A S2 vOUT

φ1 S1

vCM
EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 11

Flip-Around T/H
• S1 is an n-channel MOSFET
• Since it always switches the same voltage, it’s on-
resistance, RS1, is signal-independent (to first order)
• Choosing RS1 >> RS1A minimizes the non-linear
component of R = RS1A+ RS1
– S1A is a wide (much lower resistance than S1) & constant
VGS switch
– In practice size of S1A is limited by the (nonlinear) S/D
capacitance that also adds distortion
– If S1A’s resistance is negligible Æ delay depends only on S1
resistance
– S1 resistance is independent of VIN Æ delay is independent
of VIN

EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 12

 Differential Flip-Around T/H

S11

S12

Offset voltage associated with charge injection of S11 & S12

cancelled by differential nature of the circuit
Ref: W. Yang, et al. “A 3-V 340-mW 14-b 75-Msample/s CMOS ADC With 85-dB SFDR
at Nyquist Input,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 12, DECEMBER 2001 1931

EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 13

Differential Flip-Around T/H

φ1’
φ1
• Gain=1 φ2
• Feedback factor=1
• ΔVin-cm=Vout_com-Vsig_com
Æ Amplifier needs to have large input common-mode compliance

EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 14

 Differential Flip-Around T/H
Choice of Sampling Switch Size

•THD simulated w/o sampling switch boosted clock Æ -45dB

•THD simulated with sampling switch boosted clock (see figure)

Ref: K. Vleugels et al, “A 2.5-V Sigma–Delta Modulator for Broadband Communications Applications “
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 12, DECEMBER 2001, pp. 1887

EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 15

Input Common-Mode
Cancellation

Ref: R. Yen, et al. “A MOS Switched-Capacitor Instrumentation Amplifier,”

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-17, NO. 6,, DECEMBER 1982 1008

EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 16

 Input Common-Mode Cancellation

Track mode (φ high) Hold mode (φ low)

VC1=VI1 , VC2=VI2 Vo1+Vo2 =0
Vo1=Vo2=0 Vo1-Vo2= -(VI1-VI2)(C1/(C1+C3))

Æ Input common-mode level removed

EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 17

Differential T/H Combined with Gain Stage

Employs the previously discussed technique to eliminate the problem associated

with high common-mode voltage excursion at the input of the opamp
Ref: S. H. Lewis, et al., “A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter” IEEE
JSSC, VOL. SC-22,NO. 6, DECEMBER 1987

EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 18

 Differential T/H Combined with Gain Stage

Ref: S. H. Lewis, et al., “A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter” IEEE

JSSC, VOL. SC-22,NO. 6, DECEMBER 1987

EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 19

Differential T/H Combined with Gain Stage

• Gain=4C/C=4
• Feedback factor =1/(1+G)=0.2
• Input voltage common-mode level removed
• Amplifier offset not removed
Ref: S. H. Lewis, et al., “A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter” IEEE
JSSC, VOL. SC-22,NO. 6, DECEMBER 1987

EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 20

 Differential T/H Including Offset Cancellation

• Operation during offset cancellation phase shown

• Auxilary inputs added with Amain/Aaux.=10
Ref: H. Ohara, et al., "A CMOS programmable self-calibrating 13-bit eight-channel data acquisition
peripheral," IEEE Journal of Solid-State Circuits, vol. 22, pp. 930 - 938, December 1987.

EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 21

Differential T/H Including Offset Cancellation

Operational Amplifier
• Operational amplifier Æ
dual input folded-cascode
opamp
• M3,4 auxiliary input, M1,2
main input
• To achieve 1/10 gain ratio
WM3, 4 =1/10x WM1,2 &
current sources are scaled
by 1/10
• M5,6,7 Æ common-mode
control
• Output stage Æ dual
cascode Æ high DC gain

Vout=gm1roVin1 + gm2roVin2
Ref: H. Ohara, et al., "A CMOS programmable self-calibrating 13-bit eight-channel data acquisition
peripheral," IEEE Journal of Solid-State Circuits, vol. 22, pp. 930 - 938, December 1987.

EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 22

 Differential T/H Including Offset Cancellation Phase

+
(V INAZ+ -VINAZ- )= -gm1/gm2 Voffset
-

Voffset

• During offset cancellation phase AZ and S1 closed Æ main amplifier offset

amplified by gm1/gm2 & stored on CAZ
• Auxiliary amp chosen to have lower gain so that:
‰ Aux. amp offset & charge injection associated with opening of switch AZ Æ reduced
by Aaux/Amain=1/10
‰Minimize power dissipation
• Requires an extra auto-zero clock phase

EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 23

ESD Protection
ADC Architectures

EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 24

 What is ESD?
• Electrostatic discharge
• Example: Charge built up on human body
while walking on carpet...
• Charged objects near or touching IC pins
can discharge through on-chip devices
• Without dedicated protection circuitry, ESD
events could be destructive

EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 25

Model and Protection Circuit

[http://www.idt.com/docs/AN_123.pdf]

[http://www.ce-mag.com/archive/03/ARG/dunnihoo.html]

EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 26

 Equivalent Circuit

• Nonlinear capacitance causes distortion

• Distortion increases with frequency
– Today's converters: High frequency, low distortion!

Ref: I. E. Opris, "Bootstrapped pad protection structure," IEEE J.Solid-State Circuits, pp. 300,
Feb. 1998

EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 27

ESD Circuit Distortion

[I. E. Opris, "Bootstrapped pad

protection structure," IEEE J.Solid-
State Circuits, pp. 300, Feb. 1998.]

C(Vin)= 2......4pF
for Vin=2....0V

EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 28

 ESD Circuit Distortion
• Analysis:
– Volterra Series
– Or SPICE simulations
• Example:
vi vo
R=25Ω
R Cj CL Cjo=1pF
CL=5pF
Vipeak=0.5V

EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 29

ESD Circuit Distortion

3rd Order Harmonic Distortion [dBc]
2nd Order Harmonic Distortion [dBc]

-60 -80

-80 -100

-100 -120

6 7 8 9 10 6 7 8 9 10
10 10 10 10 10 10 10 10 10 10
Input Frequency Input Frequency

HD3(@ 37.5MHz) = -92dB

HD3(@ 100MHz) = -84dB

EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 30

 ESD Circuit Distortion
• Distortion from ESD circuits approaches state
of-the-art ADC performance!
• If you are working on a new, record breaking
ADC, better think about ESD now...
• Ref.: A. Wang, "Recent developments in ESD
protection for RF IC," Proc. DAC Conference,
Jan. 2003
• Solutions still pre-mature
• Lots of company intellectual property! (IP)

EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 31

ADC Architectures
• Slope Converters
• Successive approximation
• Flash
• Folding
• Time-interleaved / parallel converter
• Residue type ADCs
– Two-step
– Pipeline
– Algorithmic
– …
• Oversampled ADCs

EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 32

 Single Slope ADC
Ramp VRamp VIN
Generator stop
Counter
start
"0" Clock

VRamp
• Low complexity
Time
• Hard to generate precise ramp
• Better: Dual Slope, Multi-Slope

EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 33

Dual Slope ADC

http://www.maxim-ic.com/appnotes.cfm/appnote_number/1041

• Integrate Vin for fixed time, de-integrate with

Vref applied Æ TDe-Int ~ Vin/Vref
• Insensitive to most linear error sources

EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 34

 Successive Approximation ADC
Reset
DAC

VIN Set DAC[MSB]=1

VREF DAC
Y N
1ÆMSB VIN>VDAC? 0ÆMSB
Control
Logic
Set DAC[MSB-1]=1

Clock Y N
1Æ[MSB-1] VIN>VDAC? 0Æ[MSB-1]

..
..

Y N
1Æ[LSB] VIN>VDAC? 0Æ[LSB]

• Binary search over DAC output DAC[Input]= ADC[Output]

EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 35

Successive Approximation ADC

Example: 6-bit ADC & VIN=5/8VREF

VDAC/VREF
VIN 1
1/2 3/4 5/8 11/16 21/32 41/64
VREF DAC
3/4
5/8
1/2 VIN
Control
Logic

Clock
Time / Clock Ticks
ADCÆ101000

• High accuracy achievable (16+ Bits)

• Moderate speed proportional to B (MHz range)

EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 36

 Flash Converter

VREF VIN
• B-bit flash ADC: fs
– DAC generates all
possible 2B -1 levels
– 2B-1 comparators
compare VIN to DAC
outputs D 2B-1ÆB
– Comparator output: A Encoder
Digital
Output
• If VDAC< VINÆ 0 C
• If VDAC > VINÆ1
– Comparator outputs form
thermometer code
– Encoder converts
thermometer to binary
code

EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 37

Flash ADC Converter

VIN
Example: 3-bit Conversion Thermo
me t
VIN VREF fs code er
VREF
0

0 B-bits

1 1

0
1
Encoder

1
1

Time

EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 38

 Flash Converter
VREF VIN fs
• Very fast: only 1 clock cycle R/2
per conversion
– Half cycleÆ VIN & VDAC R

comparison
R
– Half cycleÆ 2B-1 to B
.. Digital

Encoder
encoding .. Output
.
• High complexity: R
2B-1 comparators
R
B-bits
R/2
• High capacitance @ input Thermometer
node code

EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 39

Folding Converter
MSB
VIN
ADC
Digital
Output
LSB
ADC

Folding Circuit

• Significantly fewer comparators than flash

• Fast
• Nonidealities in folder limit resolution to ~10-bits

EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 40

 Time Interleaved Converter
4fs fs
VIN S/H ADC

Serial / Parallel Conversion

fs + T/4

• Extremely fast:

Digital Output
ADC

Limited by speed of S/H fs + 2T/4

ADC
• Accuracy limited by mismatch
fs + 3T/4
in individual ADCs (timing,
offset, gain, …) ADC

EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 41

Residue Type ADC

Partial Digital Output

coarse ADC Error S/H & Gain

VIN DAC
(1 ... 6 Bit) (optional)

• Quantization error output (“residuum”) enables

cascading for higher resolution
• Great flexibility for stages: flash, oversampling ADC, …
• Optional S/H enables parallelism (pipelining)
• Fast: one clock per conversion (with S/H), latency
EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 42
 Pipelined ADC
VIN Stage 1 Stage 2 Stage K
B1 Bits B2 Bits Bk Bits

Digital Correction Logic

Digital output
up to (B1 + B2 + ... + Bk) Bits

• Approaches speed of flash, but much lower complexity

• One clock per conversion, but K clocks latency
• Efficient digital calibration possible
• Versatile: from 16Bits / 1MS/s to 14Bits / 100MS/s
EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 43

Algorithmic ADC
Digital Output

Shift Register
& Correction Logic
start of conversion
Residue
VIN coarse
ADC DAC 2B T/H
(1 ... 6 Bit)

• Essentially same as pipeline, but a single

stage is used for all partial conversions
• K clocks per conversion
EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 44
 Oversampled ADC
fs fs/M

Digital
VIN Digital
H(z) Decimation
Output
Filter

DAC

• Hard to comprehend … “easy” to build

• Input is oversampled (M times faster than output rate)
• Reduces Anti-Aliasing filter requirements and
capacitor size
• Accuracy independent of component matching
• Very high resolution achievable (> 20 Bits)
EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 45

Throughput Rate Comparison

18
on~B
Flash, Pipeline~1 to 2

16
1)
ximivaeti

B+
2 (0.4

14
ss
Resolution [Bit]

Su ce
Appcro

ple Bit
d~

12
am 1-
ers der

B
10 2
l~
Ov Or

ri a
Se
2 nd

0 0 1 2 3 4 5
10 10 10 10 10 10
Clock Cycles per Conversion

EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 46

 Speed-Resolution Map

[www.v-corp.com]

EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 47