T.Mary Neebha et al.

/ (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES

Vol No. 5, Issue No. 2, 339 - 342

Design Analysis of FFT Blocks for Pulsed OFDM

UWB Systems using FPGA 1
T.Mary Neebha, 2J.Jeevitha, 3M.S.Sumi
1, 2, 3
Lecturer, Electronics and Communication Engineering,
Karunya University,Coimbatore.
[maryneebha @karunya.edu,jeevithajoseph@karunya.edu,sumi@karunya.edu]

Abstract: performance. The traditional approach employing radix 2

UWB (Ultra Wideband) Technology is an inherently algorithm to compute FFT is consuming large power and
low power radio technology where power levels are restricted. excess resources, which makes FPGA implementation
FFT/IFFT is one of the key components and the most complex unfit.
block in OFDM based designs. This work is mainly destined for
analyzing FFT architectures for P-OFDM UWB receiver
section in both single path as well as multipath modes. The

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FFT architectures obtained from radix 2 and mixed radix
Cooley-Tukey algorithms are discussed in this paper. Thus the
aim here is to compare the FFT architectures used for
implementing the UWB receiver with minimum resource
utilization.

I. INTRODUCTION
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The FFT (Fast Fourier Transform) processor is
widely used in DSP applications and now being used in
communication protocols. Recently, both high data processing
and high power efficiency assumes more and more importance in
wireless systems. UWB has its part in wireless personnel area
network utilizes efficient FFT architectures for its design.
P-OFDM is an improved version of Multiband
Figure 1: Signal flow graph for 8 point FFT
OFDM, which is one of the techniques in implementing
The signal flow graph for 8 point FFT is
UWB transceiver. This is destined to reduce power
consumption as well as hardware resources utilized. shown in figure 1.Similar butterfly structure is obtained for
FFT/IFFT is one of the key components and the most the 128 point FFT and it includes number of Radix 2
complex block in OFDM (orthogonal frequency division butterfly elements. This makes the design easier but it does
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multiplexing) based designs. This paper explores the FFT not provide good performance.
architectures using radix 2 as well as mixed radix
concepts. In the mixed radix concept, both multipath delay III. MIXED RADIX FFT ARCHITECTURES
commutator as well as multipath delay feedback is also Mixed radix algorithm, another modified
dealt with. The synthesis part of the job is accomplished version of Cooley – Tuckey algorithm handle composite
by downloading the verilog hardware description language sizes. It behaves like FFT for any series that can be
factored in factors 2, 3, 4, 5, 8 and 10. When there are
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codings into the XILINX tool, SPARTAN 3E –

XC3S500E.
II. CONVENTIONAL FFT ARCHITECTURE
The DFT of N complex data points x (n) is
defined by the summation of the samples of the product of
twiddle factors and the input samples. The twiddle factor
or the coefficient is given by the exponential term , WN =
e−j2π/N. FFT is the speed up algorithm of DFT. The current
research interest in UWB is in increasing the data rate for
considerable distances. Orthogonal frequency division
multiplexing is considered as the best choice for high data
rate transmission by the 802.15.3a standardization group
for use in establishing a physical-layer standard for UWB
communications [1]. The execution time to calculate 128
point FFT for UWB systems is 312.5ns. Hence efficient
FFT structure should be designed to obtain good
other prime factors in the series, it will calculate the
subseries with a complex Discrete Fourier Transform
(DFT). The mixed-radix FFT is just as fast as normal FFT
for power of 2 series, in all cases where the series can be
composed of the factors above. In other cases it will be
slightly slower [2]. In this paper, various mixed radix
architectures including mixed radix multipath delay
commutator, mixed radix single path delay feedback and
mixed radix combined delayed feedback commutator are
to be dealt with.
i. Mixed radix multipath delay commutator:
The Mixed radix multipath delay commutator
is a very crucial architecture for FFT computation, and it
combines parallel pipelined concept and memory based
architectures so as to obtain power efficiency. The
processor , based on the multipath delay commutator

ISSN: 2230-7818 @ 2011 http://www.ijaest.iserp.org. All rights Reserved. Page 339

 T.Mary Neebha et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES
architecture has high-radix arithmetic units with two main
memories for input storage, intermediate commutators,
delays and output buffer for rescheduling purposes. The
block architecture is shown in Figure .2.
Figure.2: Mixed Radix Multipath Delay Architecture
Here the 128 point FFT suited for UWB
applications are calculated using four parallel 32 point FFT
[2]. The architecture shows the FFT computation for the
32 point FFT, which is decomposed into radix 4 FFT and
radix 2 FFT. The switches are more complex and it is
implemented using multiplexers. All these operations are
controlled by the control unit and the twiddle ROM is
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implemented using shift-add method of twiddle factor
computation. The twiddle ROM computation is made by
observing the unique twiddle factors and then mapping the
values according to the mapping table. The radix 4
architecture shown in figure.3. is implemented using Carry
Save Adder. It is found that Carry Save Adder, which is a
fast adder, is having less delay compared to other adders
and hence this adder is imported into the design to
compute radix 4 algorithms. This design, using mixed
radix multipath delay commutator has four complex
multipliers, so it consumes more multiplier power. To save
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the power consumption, a better implementation of the 128
point FFT is made by using the concept of single path
delay feedback, which is discussed in the next section.
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Figure.3: Radix 4 Architecture
ii. Mixed radix Multiple path delay feedback :
ISSN: 2230-7818 @ 2011 http://www.ijaest.iserp.org. All rights Reserved.
Vol No. 5, Issue No. 2, 339 - 342
In this architecture, the first 64 pieces of
complex data are stored in one register file, so that when
the next 64 sequences arrive both are applied to FFT
calculations. In order to minimize the memory
requirement and to ensure the correction of the FFT
output data, 64 point FFT is calculated using radix 8 and
radix 2 algorithms. The architecture for mixed radix
single path delay feedback is shown in figure.4. The
approach of using four complex multipliers as in the case
of multipath delay commutator is modified by reducing
the number to two. In the beginning, the datas are
reordered and separated into 32 groups. Each group has
four sequences in this design supporting multiple paths.
The data of each path are fed to appropriate constant
multipliers according to the scheduling of the twiddle
factors. The data of the first 32 groups are stored in the
memory. When the data of the next 32 groups enter the
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module the eight input data are loaded into four radix 2,
four from the memory and four from the input,
respectively. Two of these four output data are multiplied
by the appropriate twiddle factors first before they are
stored in the memory; the other two are multiplied by the
twiddle factors before they are fed to the module. Hence
the complexity, power consumption, and resources
required are further reduced. The radix 8 FFT is
computed by decomposing into radix 2 FFTs and by
applying suitable delays.
Figure.4: Mixed radix multipath delay feedback
iii. Mixed radix combined multiple path delay feedback commutator
This architecture combines both the mixed radix
delay commutator and mixed radix delay feedback
concepts. Here also, the 128 point FFT is computed using
four parallel 32 point FFTs. The 32 point FFT is computed
by storing the first 16 points in register file, which stores
the data until the other 16 points arrive from the buffer.
Then these eight outputs are given to radix 4,
commutators, delays, twiddle multipliers and radix 2 to
compute the FFT. The complex multipliers used to
multiply the outputs with the twiddle factors are reduced
by applying the feedback concept. Two outputs from the
radix 4 are multiplied with the complex multiplier before
feeding to the register and the other two are multiplied
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 T.Mary Neebha et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES
Vol No. 5, Issue No. 2, 339 - 342

with the complex multiplier after getting from the

feedback register. Thus the multiplier power is reduced.
The architecture is shown in Figure.5. Close observation of
the twiddle factor reveals that only few twiddle factors are
unique. The other factors can be obtained using the
mapping method and the twiddle factors can be
implemented using shift-add operations.

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Figure.5: Combined delay and feedback architecture

IV. CONCLUSIONS
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The FFT architectures, satisfying
UWB specifications suited for its applications have been
designed, simulated and the simulation results are
compared. It is found that ,even though all the mixed radix
architectures is having better performance, the Mixed radix
combined multiple path feedback commutator has the best
performance in terms of reduced gate count and power
consumption..
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REFERENCES
[1] A. Batra et al., “Multi-Band OFDM Physical Layer
Proposal for IEEE 802.15 Task Group 3a,” IEEE
P802.15- 03/268r3, Mar. 2004.
[2] D.M.W.Leenaerts,” Transceiver design of Multiband
OFDM UWB”, philps Research, EURASIP journal on
Wireless communication and networking, Jan.2006.
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[3] Kai-Chuan Chang, Gerald E.Sobelman, “FPGA Based

Design of a Pulsed-OFDM System”, 1-4244-0387-1,
APCCAS 2006.
[4] Kai-Chuan Chang, Gerald E.Sobelman, “Noise Model
Analysis of Optimized Mixed-Radix Structures for
Pulsed OFDM”, IEEE Global Telecommunication
Conference, 2006.
[5] Yu-Wei Lin , Chen-Yi Lee,” Design of an FFT/IFFT
Processor for MIMO OFDM Systems”, IEEE
Transactions on circuits and systems, VOL. 54, NO. 4,
APRIL 2007
[6] B. M. Bass, “A low-power, high-performance, 1024-
point FFT processor,”IEEE J. Solid-State Circuits, vol.
34, no. 3, pp. 380–387, Mar.1999.

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T.Mary Neebha et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES
Vol No. 5, Issue No. 2, 339 - 342

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