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Hanish chowdary .v et al.

/ (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES


Vol No. 6, Issue No. 1, 141 - 143

Variable Frequency Scheme for Low Power


Digital Circuits
Hanish chowdary .v Mahaboob Alisha Syed Reddy E.V.K Pinnitla Jagannadha Naidu .k
Mtech VLSI DESIGN Mtech VLSI DESIGN Mtech VLSI DESIGN Asst Prof, VLSI Design
SENSE, VIT University, SENSE, VIT University, SENSE, VIT University, SENSE, VIT University,
Vellore, Tamil Nadu, India Vellore, Tamil Nadu, India Vellore, Tamil Nadu, India Vellore, Tamil Nadu, India
vhanish221@gmail.com m_syed6@yahoo.com eshwar455@gmail.com jagannadhanaidu@vit.ac.in

Abstract: Now-a-days, power dissipation is one of the most  Implementation of digital filters using signed
significant focus in VLSI design. The most widely used power of two (SPT).
operation performed today is multiplication. The

T
multiplier is the complex cell which occupies more area Drawbacks: The drawback of this technique is
and dissipates more power compared to all cells in library. low accuracy and overflow
In this paper we explore the possible way to reduce
complexity in FIR filter by reducing the number of
 Implementation of filters using canonical
multiplication operators.
signed digit(CSD).
So, Computation sharing multiplication technique [1] Drawback: It cannot generate programmable

two techniques
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which uses the pre-computation bank is used, to decrease
the number of multiplications so that power can be saved.
We implemented this technique in FIR filter. This paper
combines Computation
multiplication (CSHM) and adaptive frequency scaling
sharing

which has been applied for the FIR filter. Self timed circuit
in synchronous environment is used for applying the above
techniques. To avoid problems at the synchronous

coefficients.
Some techniques use shift and add
multiplication algorithm with common sub-
expression elimination (CSE).
All these schemes although simple does not
guarantee the optimal solution.

interface, care must be taken such that FIFO should never


become full or empty. So, depending upon the state of the II. CSHM APPROACH:
FIFO the clock frequency is adjusted.
A.) CSHM Multiplier: This multiplier reduces
power consumption of FIR filter with real
A
Keywords: Computation sharing multiplication (CSHM) ,
Finite impulse response (FIR) , FIFO value coefficients. It consists of
precomputed, select units, shifters and
adders. To cover every possible coefficient
I. INTRODUCTION: and multiplication operation we used 8
alphabets.( 1x, 3x, 5x, 7x ,9x, 11x,
As there is a need for improving the data rates with
13x, 15x).
reduced power dissipation. One of the most widely used
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B.) CSHM Architecture: This technique is not


operations is finite impulse response (FIR) filtering [5].
power efficient for a single multiplication
This process involves product of filter coefficients with
operation. The computation 1x, 3x, 5x, 7x,
input signal x. In this paper, we tried to reduce the
9x, 11x,13x,15x will be performed once
complexity in FIR filter by removing the computation
and shared by all
redundancy by synthesis phase of filter. The
implementation of filters with CSHM architecture
reduces computation complexity and increases re-
usability which helps in power sharing.

The optimization of constant multiplication problem


(multiplication of input by filter coefficient) has been
accomplished in different ways .Many researchers
reported different techniques to reduce the
computational redundancy.

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Hanish chowdary .v et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES
Vol No. 6, Issue No. 1, 141 - 143

in the down module is again shifted to left by four times


before it is given to the adder where it is added with the
upper module output. Finally, the result we get will be
equivalent to 11100100x i.e. CX. Hence with the use of
precomputed blocks, shifter and adder we are able to
perform the multiplication operation. The advantages in
power saving are observed when more number of
multiplication operations are required

III. PROPOSED ARCHITECTURE

DC TO DC converter

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State
Detector

R
FIFO Buffer FIR with CSHM
E
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Fig1: CSHM architecture [4]
G Clk1

clk1

FIG2: Self timed circuit in synchronous


environment [2].

Let us consider an example for the complete The whole architecture operates in synchronous
understanding of the CSHM. Suppose our coefficient C environment [2]. In this architecture, data is written into
the buffer at the faster rate compared to speed at which
A
is a 8 bit number 11100100[4].The last four bits are
given to the upper module shifter in which the right shift data is read and pumped into FIR. The state detector
operation should take place until a 1 is found in the LSB compares the data rates of writing and reading
bit[4]. This is to match with the computation stored in operations of buffer and generates a signal to increase
the pre-computed bank. As the product of odd numbers the rate of reading data from buffer such that buffer will
with the input signal x are multiplied and stored in the never become full .
pre-computed bank the shifted bits with the last bit one
Similarly buffer never becomes empty, if data is read at
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will match with that in the pre-computed bank data. The


a faster rate from FIFO. So the voltage gets scaled
number of shift operations until we get 1 in last bit is
depending upon the data rate.
stored and given to the lshifter. In the final output of
right shifter the first three bits are given as the select IV RESULTS:
lines to the mux and the corresponding data from the
pre-computed banks are selected. In our example 0100 is Synthesis has been done for basic constant multiplier
given to the upper module and two shits take place so 10 and CSHM based FIR filter (8 – tap) . The filter
is given to the lshift. After two shifts the output of right programmable coefficients are generated using
shift is 0001 so the first three bits 000 are given as select MATLAB. Their reports are summarized as below.
lines to the mux which selects the 1x from the pre-
computed banks and given to the lshift. There again two The synthesis is performed using Cadence RTL
left shift operation take place as two is given from right Compiler with the technology library tsmc-90 nm and
shifter to lshift. So, the resultant from the lshift is operating voltage is 1V.
equivalent to the 0100[4].

The same procedure is repeated with the down module


to which the first four bits are given as inputs. The result

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Hanish chowdary .v et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES
Vol No. 6, Issue No. 1, 141 - 143

S.No FIR FILTER POWER AREA Acoustics, Speech, and Signal Processing,
REPORT REPORT 2001. Proceedings. (ICASSP '01). 2001 IEEE
(nW) (u m2) International Conference on Page(s): 1245 -
1248 volume.2.
1. With constant 444095 7589
multiplier 2. Lars S. Nielsen, Cees Niessen, Jens Sparso, and
Kees van Berkel, Dept. of Comput. Sci., Tech.
2. With CSHM 277147 3948 Univ. ― Low-power operation using self-timed
multiplier circuits and adaptive scaling of the supply
voltage" Denmark, Lyngby Very Large Scale
Integration (VLSI) Systems, IEEE Transactions
on , Page(s): 391 – 397, Publication Year: 1994
Table.1 .
The power consumed by the FIR filter with constant 3. Georgios Karakonstantis and Kaushik Roy
multiplier is more compared to the FIR filter with School of Electrical and Computer

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CSHM multiplier if the numbers of computations are Engineering, Purdue University ―A n optimal
more. Simulation is done using 90nm technology. Area algorithm for low power multiplierless fir filter
occupied is also less in the CSHM filter compared to design using chebychev criterion” Acoustics,
FIR constant multiplier. Speech and Signal Processing, 2007. ICASSP
2007. IEEE International Conference on
V Future work: Volume: 2, Publication Year: 2007, , Page(s):
ES
To the proposed architecture, we can save the power
further by using adaptive supply voltage scaling. Scaling
of voltage is done with work load estimation of FIFO
which. is operating in synchronous environment . If the
FIFO is running empty the supply voltage applied to FIR
will get scaled to lower voltage level such that data from
4.
II-49 - II-52

Ji-Woong Choi, Senior Member, IEEE,


Jungwon Lee, Member, IEEE, Byung Gueon
Min, and Jongsun Park, Member, "Energy
Efficient Hardware Architecture of LU
Triangularization for MIMO Receiver" IEEE
FIFO can be read at lower rate. Similarly if FIFO is transactions on circuits and systems—ii:
running full, the supply voltage gets increased. express briefs, vol. 57, no. 8, august 2010, on
page(s): 632-636.
VI Conclusion:
5. Sandeep dhar and Dragan maksimovic
A
In this paper, we proposed a CSHM FIR filter
department of electrical and computer
architecture which is power and area efficient. It helped
engineering university of Colorado, boulder, co
us to achieve low power and high performance. The
80309-0425 ― Low-Power Digital Filtering
design which was presented in this paper is simple but
Using Multiple Voltage Distribution and
effective for synchronous low power digital circuits.
Adaptive Voltage Scaling”, vol 2, on pages
There are number of power efficient techniques to
207-209.
reduce the computational redundancy in FIR filters but
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each technique has its own drawbacks.

In this technique we reduced the complexity and


improved the reusability. In addition to that we
controlled the data rate for efficient operation of FIR
using FIFO in synchronous environment.

VII References:

1. Hunsoo Choo, Khurram Muhammad and


Kaushik Roy School of Electrical and
Computer Engineering, Purdue University
West Lafayette, IN 47907, USA, ― Decision
feedback equalizer with two's complement
computation sharing multiplication”

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