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Abstract: Now-a-days, power dissipation is one of the most Implementation of digital filters using signed
significant focus in VLSI design. The most widely used power of two (SPT).
operation performed today is multiplication. The
T
multiplier is the complex cell which occupies more area Drawbacks: The drawback of this technique is
and dissipates more power compared to all cells in library. low accuracy and overflow
In this paper we explore the possible way to reduce
complexity in FIR filter by reducing the number of
Implementation of filters using canonical
multiplication operators.
signed digit(CSD).
So, Computation sharing multiplication technique [1] Drawback: It cannot generate programmable
two techniques
ES
which uses the pre-computation bank is used, to decrease
the number of multiplications so that power can be saved.
We implemented this technique in FIR filter. This paper
combines Computation
multiplication (CSHM) and adaptive frequency scaling
sharing
which has been applied for the FIR filter. Self timed circuit
in synchronous environment is used for applying the above
techniques. To avoid problems at the synchronous
coefficients.
Some techniques use shift and add
multiplication algorithm with common sub-
expression elimination (CSE).
All these schemes although simple does not
guarantee the optimal solution.
DC TO DC converter
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State
Detector
R
FIFO Buffer FIR with CSHM
E
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Fig1: CSHM architecture [4]
G Clk1
clk1
Let us consider an example for the complete The whole architecture operates in synchronous
understanding of the CSHM. Suppose our coefficient C environment [2]. In this architecture, data is written into
the buffer at the faster rate compared to speed at which
A
is a 8 bit number 11100100[4].The last four bits are
given to the upper module shifter in which the right shift data is read and pumped into FIR. The state detector
operation should take place until a 1 is found in the LSB compares the data rates of writing and reading
bit[4]. This is to match with the computation stored in operations of buffer and generates a signal to increase
the pre-computed bank. As the product of odd numbers the rate of reading data from buffer such that buffer will
with the input signal x are multiplied and stored in the never become full .
pre-computed bank the shifted bits with the last bit one
Similarly buffer never becomes empty, if data is read at
IJ
S.No FIR FILTER POWER AREA Acoustics, Speech, and Signal Processing,
REPORT REPORT 2001. Proceedings. (ICASSP '01). 2001 IEEE
(nW) (u m2) International Conference on Page(s): 1245 -
1248 volume.2.
1. With constant 444095 7589
multiplier 2. Lars S. Nielsen, Cees Niessen, Jens Sparso, and
Kees van Berkel, Dept. of Comput. Sci., Tech.
2. With CSHM 277147 3948 Univ. ― Low-power operation using self-timed
multiplier circuits and adaptive scaling of the supply
voltage" Denmark, Lyngby Very Large Scale
Integration (VLSI) Systems, IEEE Transactions
on , Page(s): 391 – 397, Publication Year: 1994
Table.1 .
The power consumed by the FIR filter with constant 3. Georgios Karakonstantis and Kaushik Roy
multiplier is more compared to the FIR filter with School of Electrical and Computer
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CSHM multiplier if the numbers of computations are Engineering, Purdue University ―A n optimal
more. Simulation is done using 90nm technology. Area algorithm for low power multiplierless fir filter
occupied is also less in the CSHM filter compared to design using chebychev criterion” Acoustics,
FIR constant multiplier. Speech and Signal Processing, 2007. ICASSP
2007. IEEE International Conference on
V Future work: Volume: 2, Publication Year: 2007, , Page(s):
ES
To the proposed architecture, we can save the power
further by using adaptive supply voltage scaling. Scaling
of voltage is done with work load estimation of FIFO
which. is operating in synchronous environment . If the
FIFO is running empty the supply voltage applied to FIR
will get scaled to lower voltage level such that data from
4.
II-49 - II-52
VII References: