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1628 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 55, NO.

6, JULY 2008

Comprehensive Behavioral Modeling of Conventional


and Dual-Tuning PLLs
Luca Bizjak, Nicola Da Dalt, Member, IEEE, Peter Thurner, Roberto Nonis, Pierpaolo Palestri, Member, IEEE,
and Luca Selmi, Member, IEEE

Abstract—This paper presents a modular and comprehensive [2] and [3], are the flexibility (e.g., once a set of models for the
nonlinear time-domain behavioral model for phase-locked loops building blocks is available, it is straightforward to compose
(PLLs) that are suitable for analyzing the impact on the output them to create a PLL with a given architecture and evaluate its
signal of the noise contribution and nonidealities of the constituent
building blocks. The model building blocks are described by
performance) and the ability to incorporate nonidealities such
Simulink submodels and can be configured to implement different as device mismatch, that are expected to become increasingly
PLL topologies. Postprocessing of the PLL output provides the important in future technologies [9]. A further advantage of
PLL phase noise and spur-to-carrier-ratio performances. The cal- using the commercial MATLAB and Simulink environment
culated phase-noise spectra are compared with those obtained with is that many of the modeled functions are readily available
the well-known linear model and with measurements. To show the and easily maintained. Moreover, the environment permits
flexibility of this approach, many case studies are reported; among
them, the analysis of the spurs due to charge pump mismatch
time-domain simulations which are the most appropriate for
and the transient phase noise, and spurs performances of a PLL the problem at hand due to the nonlinear, time-variant, both
featuring a dual control of the voltage-controlled oscillator. continuous and discrete nature of the PLL. The parameters of
each block can be derived from SPICE-level simulations of
Index Terms—Circuit modeling, circuit simulation, frequency
synthesizers, nonlinear circuits, phase-locked loops (PLLs), phase the individual blocks that are much simpler and faster than the
noise, voltage-controlled oscillators (VCOs). simulation of the whole PLL.
The model has been used to analyze many aspects of PLLs
such as transient responses, phase noise, and spurs generated
I. INTRODUCTION by charge pump mismatch. The results have been compared with
alternative models and simulation approaches, e.g., circuit-level
HE design of phase-locked loops (PLLs) [1] is often
T driven by tight specifications in terms of phase noise,
spectrum of the frequency spurs, and transient response to fre-
simulators, analytical approaches, and linearized models. They
point out that our simulation approach, while being able to take
into account nonidealities that are impossible to treat with sim-
quency variation, which must be satisfied in spite of changing pler models, was a great speed advantage over detailed circuit-
operating conditions and device mismatch. Accurate behavioral level simulation. Furthermore, to demonstrate the flexibility of
system-level simulations are needed for reliable estimates of the model, we have applied it to the analysis of a dual-tuning
the PLL performance including nonideal effects in order to PLL.
reduce the number of design iterations at the transistor level. This paper proceeds as follows. The Simulink model and the
Various behavioral-level simulation approaches have been Clock_Analyzer are described in Section II. Examples of appli-
reported in the literature. Simulation environments using cation are reported in Section III. In Section IV, the model is
Simulink and MATLAB have been described in [2] and [3]. A applied to a PLL featuring a dual-tuning control [10]. A conclu-
custom C++ simulator has been developed in [4]. A mixed sion is given in Section V.
MATLAB and CMEX platform has been developed in [5]. A
Harmonic Balance model has been presented in [6].
In this paper, we develop a Simulink [7] model for the II. MODEL DESCRIPTION
building blocks of various kinds of PLLs and a MATLAB [8] This section illustrates the implementation of each functional
code (referred to in the following as Clock_Analyzer) to ex- block of the PLL underlining the differences between our ap-
tract the PLL performance in terms of phase noise, jitter, and proach and the ones in the literature. After that, a brief descrip-
spur-to-carrier ratio without having to rerun the simulations. tion of the postprocessing of the output signal (performed by the
The main advantages of this approach, similar to the ones in Clock_Analyzer) for evaluating noise performance and spurious
tones is given.
Manuscript received April 21, 2007; revised September 4, 2007 and October
19, 2007. First published February 2, 2008; last published July 10, 2008 (pro-
jected). This paper was recommended by Associate Editor Bernard C. Levy. A. PLL Building Blocks
L. Bizjak and R. Nonis were with the DIEGM, University of Udine, 33100
Udine, Italy. They are now with Infineon Technologies Austria, A-9500 Villach, Voltage-Controlled Oscillator (VCO): The model for this
Austria (e-mail: luca.bizjak@infineon.com). block is the one that presents more differences from the model
N. Da Dalt and P. Thurner are with Infineon Technologies Austria, A-9500 proposed in [3] and thus is described more extensively. The
Villach, Austria.
P. Palestri, and L. Selmi are with the DIEGM, University of Udine, 33100
VCO implementation is shown in Fig. 1. In the upper part of
Udine, Italy. the model, the control voltage determines the VCO
Digital Object Identifier 10.1109/TCSI.2008.916700 frequency feeding a look-up table (LUT) that implements the
1549-8328/$25.00 © 2008 IEEE
BIZJAK et al.: COMPREHENSIVE BEHAVIORAL MODELING OF CONVENTIONAL AND DUAL-TUNING PLLs 1629

Fig. 1. Schematic representation of the VCO. The VCO model has two inputs: the control voltage (V CO In) and the supply noise input (V Noise). The two
outputs represent the VCO output clock (Clock 0) and the instantaneous frequency (f monitor ). In the upper part of the model, the control voltage determines
the VCO frequency. Furthermore the noise generator feeds the block noise through three different paths for the three different regions of the phase-noise spectrum.
The sum of the noise and the frequency signals is transformed into a phase signal. At the output the P2C block transforms the phase signal into a clock signal. As
recommended in the MATLAB manual, we have placed a Memory block on the Trigger signal feedback path in order to avoid any ambiguous execution order.

nonlinear VCO tuning curves [3]. Here, a nonideality that is not the phase signal into the squared waveform clock signal. This
present in [3] is the supply noise, i.e., variations of the supply block allows the user to specify the number of output clocks,
voltage that cause a deviation of the output frequency from its their duty cycle, and a possible phase mismatch between them.
nominal value, creating spurs. This has been taken into account In Fig. 1, we consider a P2C with a single output clock and
by the input, as described in Section III-C. Fur- with a duty cycle equal to 50%. When the falling edge of the
thermore, the phase-noise generator block (lower left part of output clock occurs, the updates
the model) feeds the noise through three different (correlated) the thresholds of the high-level intervals of the output clock
paths for the three different regions of the phase noise ( , simply adding to each of them the constant , since the phase
, and flat noise region). The phase noise is obtained is expressed in radians. When the duty cycle is 50%, these two
with the block implementing a bank of digital numbers differ by . These two limits are then used by the
filters [11] between 100 Hz and 10 MHz. The lower bound two blocks that compare them with the
of 100 Hz is sufficiently small for the application considered, phase signal coming from the integrator block to identify the
since the integrated jitter corresponding to a frequency range high-level interval of the clock. Using more than one P2C block,
between 100 Hz and 10 kHz is negligible. This approach it is possible to provide output clocks with different phase.
differs from [3] since this latter only considers the flicker This implementation justifies our choice to realize the VCO
noise present on the control voltage. The sum of the noise without resetting its output phase signal, since it simplifies the
and frequency signals is translated into a phase signal by the implementation of the P2C block and decreases the run-time,
integrator block. The VCO output is thus the phase signal, especially when simulating more than one output clock.
whereas in [3] the phase is used to compute a cosine function Reference Generator (REFGEN): The Reference Generator
representing the output clock. Furthermore, differently from is modeled as the VCO. The only difference is that the upper left
[3], the phase signal is not a sawtooth waveform, i.e., it is part of the model is simply modeled
not reset every . The sawtooth waveform is needed in [3] with the Simulink constant block.
because a constant simulation time-step is used. Thus, when Charge Pump (CHP): Both single-ended and differential
the simulated time reaches the point at which the last digit used charge pump configurations have been considered. The im-
to represent it is larger than the simulation time-step, serious plementations extend those in [2] and [3] including more
numerical problems arise. We do not encounter these kinds nonidealities. First, the nonlinear I–V characteristic of the tran-
of problems for simulations consisting of as many as 250 000 sistors that form the Up and Down current sources is described
cycles of the reference clock, and so we do not reset the VCO by an LUT. The mismatch between the Up and Down currents
output phase signal. An additional block (phase-to-clock block, (see Section III-D) is specified as a percentage of the CHP
P2C, right-lower part of the model in Fig. 1) then transforms current. Other nonidealities such as the noise of the current
1630 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 55, NO. 6, JULY 2008

sources and the CHP leakage current are implemented in a way


similar to [2], [3].
Loop Filter (LF): The filter is modeled in the -domain, fol-
lowing [2] and [3], however differently from these references,
in the case of an active LF, we also consider the contribution
of the operational amplifier (op-amp) to the transfer function
accounting for its finite bandwidth. The thermal noise of the re-
sistors is included by computing the transfer functions from the
noise source to the output of the LF as in [2] and [3], whereas the
noise contribution of the op-amp has been obtained from circuit
simulations.
Phase Frequency Detector (PFD): We have implemented the
classic PFD, composed by two D-flip-flops driven by the ref-
erence and the feedback signal and a simple reset circuit [12],
using the D-flip-flops and NAND gate blocks already included in
the Simulink library, following [2], [3]. The delay of the
NAND gate [3] has been also modeled, whereas other nonideali-
ties, such as the dead zone, have not been taken into account in
the present implementation.
Divider (DIV): It is implemented with an ideal counter gen- Fig. 2. Starting from the stored instants of the rising edges of the PLL output
erating a transition in the output every transitions in the input, clock, represented by crosses, linear regression is used to determine the ideal
clock (solid line) that best fits these instants. The parameters of the ideal clock
neglecting its noise contribution. In some cases, when simu- are t , the instant at which the first rising edge occurs, and the period T .
lating transient of PLLs with a fixed divider ratio, in order to
speed up the simulation the frequency of the VCO (
in Fig. 1) is divided by the divider factor, proceeding in a way
and ) of the phase error signal (whole se-
similar to [4], i.e., the frequency of the VCO is directly divided
quence of length ). It is then averaged over all segments
by before entering the P2C block.
and divided by the normalizing constant that depends on the
type of window used
B. Clock_Analyzer
To reduce the amount of data necessary to analyze the (3)
PLL output signal, an event-driven approach has been used.
The Simulink solver used to simulate the model is the Ode45
Dormand-Prince [7] with a variable step. Only the instants where are the window coefficients. In this work, a Hanning
at which the rising edges of the PLL output occur are stored. window has been adopted.
This operation has been implemented in Simulink using a To obtain the spectrum of the spurs, we act as if they were
continuous integrator to obtain a ramp function that indicates small index-frequency modulations on top of the PLL main
the time. This variable enters a subsystem triggered by the output signal. Accordingly, we calculate the modulus of the
VCO output that stores the time instants corresponding to each Fourier transform of the phase error as follows:
rising edge. The period and offset time of the ideal
clock are obtained applying the linear regression method to the (4)
array of values (Fig. 2)
where is the windowed Fourier transform of the whole
(1) phase error signal (sequence of samples), and is a
normalizing constant depending on the type of window used

Comparing the actual instants of the rising edges with those (5)
of the ideal clock, we obtain the phase error for each clock pe-
riod . Using the array of phase errors and applying the
Periodogram method [13], the phase-noise power-spectral den- Also, for this case, a Hanning window has been adopted. Then,
sity (PSD) is computed as follows: we compute the spurious-to-carrier ratio (SCR) as

dBc (6)
dBc/Hz
where and are the Bessel functions of order zero and one,
(2) respectively. Here, we assume a small modulation index so that
where is the windowed Fourier transform of the th length- the SCR gives accurate results only for the first spurious com-
limited segment constituted of samples ( with between ponent when the modulation of the VCO is strong.
BIZJAK et al.: COMPREHENSIVE BEHAVIORAL MODELING OF CONVENTIONAL AND DUAL-TUNING PLLs 1631

TABLE I
PARAMETERS OF THE PLL SIMULATED IN FIG. 4. SEE FOOTNOTES 1–4 AND
FIG. 3 FOR DETAILS

Fig. 3. Schematic of (a) the second-order and (b) third-order passive loop filter
used in the PLL model. (c) Phase-noise shape of the reference generator, ex-
plaining the parameters specified in Tables I and II. The phase noise produced
by the VCO is specified with a similar shape, just considering f = f . (d)
For the parameters of the noise generators implemented in the REFGEN, I–V characteristic of the n-MOS transistor that models the down pump switch
refer to Fig. 3(c). of the charge pump. A complementary characteristic is defined for the p-MOS
The V ,V and R are the parameters that define the V –I transistor.
characteristic of the CHP switches, see Fig. 3(d).
The meaning of the parameters of the LF is explained in Fig. 3(a) and (b).
the arrays Output freq. and Control voltage are derived accurately by
simulating the actual VCO schematic with the circuit simulator TITAN [15],
here we report only the boundary values.

The instants of the rising edges of the simulated clock can


also be used to compute period jitter, cycle-to-cycle jitter, and
absolute jitter [14].

III. APPLICATION TO CONVENTIONAL PLL


Here, we exemplify the ability of the nonlinear time-domain
model and of the clock analysis tool to simulate the nonideal
effects and the transient behavior of a conventional PLL de-
veloped in the design center of Infineon Technologies in Vil-
lach, Austria. Some of the original PLL parameters have been
changed to simulate the effect of the nonidealities that can be
accounted for by our model.
In Section IV, we will then consider an especially challenging
application, namely a dual-tuning PLL whose operation de-
pends on largely different time constants.
Fig. 4. Comparison between the start-up transient obtained with the nonlinear
A. PLL Start-Up Transient time-domain model of this paper and with the circuit simulator TITAN [15].
We first compare the start-up transient computed with the The PLL data are from Table I.
model and the one obtained via the circuit simulator TITAN
[15]. Table I reports the parameters of the PLL under study. The runtime of the Simulink model is only 10 s, instead of the
The LUT that models the VCO tuning curve has been de- approximately 10 h that would be typically required for tran-
rived accurately by simulating the actual VCO schematic with sistor-level simulations of the whole PLL circuit (performed,
TITAN. As depicted in Fig. 4, an excellent match between the e.g., with TITAN [15]).
nonlinear time-domain model and the circuit simulation has
been obtained: the lock state is reached almost at the same B. Phase Noise
instant, and the overshoot presents the same amplitude. This To test the correctness of phase-noise calculations within the
result is obtained thanks to the nonlinear tuning characteristic nonlinear time-domain PLL model we compared the results
of the VCO and the nonlinear time-domain modeling of the with those obtained using the linear model of [12] and [16].
PFD-CHP. In fact, taking into account the period when both Up To this purpose we simulate a different PLL. The parameters
and Down pump switches are active due to the delay introduced of the new PLL that differ from those of the first PLL are
by the NAND gate in the PFD and the current mismatch due summarized in Table II. The same noise parameters have been
to the different – characteristic of the n-MOS and p-MOS used in the linear model as well as in the nonlinear time-domain
transistors is necessary to reach the lock state at the same time. simulations.
1632 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 55, NO. 6, JULY 2008

TABLE II
PARAMETERS OF THE BUILDING BLOCKS OF THE PLL UNDER STUDY IN
FIGS. 5, 6, 7, AND 9 THAT DIFFER FROM THOSE REPORTED IN TABLE I. THE
MEANING OF THE PARAMETERS IS THE SAME AS IN TABLE I

Fig. 6. Superposition of the SCR plots obtained simulating the PLL described
in Table II with a VCO affected by a sinusoidal supply noise at 100 kHz, 500
kHz, 1 MHz, and 10 MHz. The dashed line indicates the predictions of (7). In
this case, the x-axis represents the frequency of the disturbance. The last spur at
frequency 500 MHz (present in all cases) is caused by the signal at the output of
the PFD. The PLL output signal has been sampled at the VCO output frequency
equal to 1 GHz.

In this example, we consider a sinusoidal disturbance with an


amplitude equal to 5% of the VCO supply level and the factor
is taken equal to 0.1. Although
we consider a simplified disturbance waveform the values of
Fig. 5. CHP, LF, and VCO contribution to the total PLL output phase noise these parameters have been estimated with TITAN simulations
computed applying the periodogram method to the nonlinear time-domain of a realistic differential state ring oscillator.
output (solid line) and from calculations based on the PLL linear model [12], Fig. 6 shows the superposition of the SCR plots obtained with
[16] (dashed line). The PLL parameters are reported in Table II.
different frequencies of the sinusoidal supply noise signal. Note
that the amplitude of the spurious components at the PLL output
Fig. 5 reports the phase-noise PSD at the PLL output pro- increases with the frequency of the sinusoidal noise. We can
duced by the different blocks. In this figure, the solid line is the understand this behavior by noting that (assuming narrow-band
PSD given by the nonlinear time-domain model, whereas the frequency modulation)
dashed line is that of the linear model [12], [16]. The curves
match quite well; small differences at high frequency are justi-
fied by the frequency folding introduced by the sampling of the
VCO output. The effects of frequency folding inside the PLL (7)
will be analyzed in more detail in Section III-E.

C. VCO Supply Noise This is the product between the transfer function from the VCO
output to the PLL output ( is the frequency divider factor,
A disturbance on the VCO supply voltage generates un-
is the transfer function of the PFD-CHP
wanted spurious components at its output. The normalized
system, is the VCO gain, and is the transfer
supply noise is the input of our model (signal
function of the loop filter), multiplied by the term
in Fig. 1). By multiplying it by a factor
(converting the frequency deviation in a phase deviation)
(obtained from circuit-level simulations), the normalized fre-
and then multiplied by the frequency deviation itself (i.e.,
quency deviation is obtained, where is the VCO
). Equation (7) is indicated with a
nominal frequency. In real cases, the factor varies as the
dashed line in Fig. 6 and nicely reproduces the results of the
output nominal frequency changes. Nevertheless, to simplify
nonlinear time-domain model.
the implementation of the model, we considered a constant
factor . In order to obtain the waveform of the distur-
D. Spurious Components Caused by the CHP Mismatch
bance signal, a circuit simulation of the whole system should
be performed. However, we assume that the supply noise is a Mismatch in the CHP circuitry is becoming an increasingly
sine wave, so that the frequency deviation is a sinusoid with important nonideality of PLL systems that causes a modulation
amplitude and with frequency equal to the frequency of of the VCO output when the PLL is in the locked state. This will
the supply noise. The disturbed output frequency is thus a then produce spurious components at the PLL output, as shown
frequency modulation superimposed to the nominal frequency. by the nonlinear time-domain results in Fig. 7.
BIZJAK et al.: COMPREHENSIVE BEHAVIORAL MODELING OF CONVENTIONAL AND DUAL-TUNING PLLs 1633

TABLE III
COMPARISON BETWEEN THE AMPLITUDE OF THE FIRST SPURIOUS
(f 6 f ) OBTAINED WITH THE NONLINEAR TIME-DOMAIN PLL MODEL
OF THIS PAPER AND WITH THE ANALYTICAL FORMULA (8)

where the VCO control voltage gain is expressed in


Hz/V, the mismatch current is expressed in ampere, and the
modulus of the LF transfer function is expressed
in ohms. Notice that, when considering a second-order passive
LF [Fig. 3(a)] and assuming that the reference frequency is
higher than the LF pole frequency , the LF transfer func-
tion can be simplified, and the resulting equation for the SCR
Fig. 7. SCR of the PLL output due to a CHP current mismatch equal to 1%.
The simulated PLL is the same described in Table II except for the reference calculation is in accordance with the one reported in [17]:
frequency (equal to 100 MHz) and the divider factor (equal to 10). The first
spurious component is at 100 MHz (reference frequency) and presents an SCR
0
of 77.3 dBc.

(9)

where is the resistance of the LF [see Fig. 3(a)].


To verify the consistency of the analytical result with the
ones of the nonlinear time-domain PLL model, we simulated
a noiseless PLL with different CHP current mismatch values.
The results are summarized in Table III. Quite good agreement
is found between (8) and the nonlinear time-domain model; a
limited discrepancy is observed for higher values of mismatch
due to the simplifications introduced in the analytical derivation
of (8).

E. Comparison Between the -Domain, -Domain, and


Nonlinear Time-Domain Models
Fig. 8. Sketch of the output current of the Charge Pump in steady state condi-
tions in the presence of a current mismatch. The Up pump current (I ) is larger As shown in Section III-B, the phase-noise PSD plots ob-
than the Down pump current (I ), and the output current presents a pulse of
0
height I and length t to compensate the excess of current caused by the
tained with the linear model and with the nonlinear time-domain
mismatch of the I current. Note that 1t  T and t  1t . model are not exactly the same, particularly at high frequencies.
This problem can be explained considering that the PLL is a dis-
crete time system. The PFD compares the phase of the reference
Fig. 8 sketches the CHP output current waveform in the pres- generator with the one of the divider output with a sampling time
ence of a mismatch between the Up and Down currents. The equal to the period of the reference signal. On the contrary, in
CHP output current is not null as it should be. In fact, it fea- the linear model, the PLL is considered to be a continuous-time
tures two pulses for each period of the reference signal. As- system described in the -domain.
suming that the Up current is larger than the Down current To illustrate this point, we compare the transfer function of
, the height of the two pulses is equal to and , re- the PLL calculated in the -domain, in the -domain [18], [19],
spectively. The duration of the second pulse is equal to the delay and with the nonlinear time-domain model. In this latter case,
introduced by the NAND gate in the PFD. The first pulse the transfer function has been obtained by adding a white noise
(of height ) compensates for the excess of charge that is in- of 100 dBc/Hz in the reference generator, while keeping the
jected in the filter by the mismatch current . An other blocks ideal (i.e., without any noise), and then dividing
analytical model for the effects on the output can be derived by the output noise by the reference noise value. The PLL is the
computing the first coefficient of the Fourier series of the CHP same as in Table II but with a CHP current of 500 instead of
output current. After some algebra, assuming a small modula- 90 A, instead of and a reference frequency
tion index, the equation that defines the SCR of the first spurious of 250 instead of 500 MHz. Fig. 9(a) reports these three
component (the one at ) is obtained as transfer functions. The -domain model presents the expected
frequency folding at multiples of the input clock frequency
(250 MHz) since it samples the PLL at the PFD operating
frequency (equal to the reference generator) [18], [19]. On the
(8) other hand, the transfer function obtained with the nonlinear
1634 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 55, NO. 6, JULY 2008

Fig. 9. (a) PLL transfer functions given by the s-domain (dashed line), the
z -domain (dot–dashed line), and the nonlinear time-domain models (solid line).
(b) Sampling frequency of the nonlinear time-domain transfer function is equal
to the reference generator frequency (250 MHz), thus presenting frequency Fig. 10. (a) Block diagram of the dual-tuning PLL. The output of the loop
folding starting from 125 MHz as in the z -domain case. Note the spurious filter drives the CC block. The VCO is driven by two control voltages: V
tones in (a), featuring a frequency which is a multiple of the reference. These and V . (b) Simulink model of the CC. The loop filter output (V ) is
are artifacts caused by the activity of the PFD, since we obtain the PLL transfer compared with the reference voltage (V ). This signal is provided to a g –C
function by stimulating the PLL with a white noise in the input, and the PFD structure that transfers current to a capacitor through a switch. The noise con-
responds with pulses at the reference clock frequency (250 MHz). tribution is then added, obtaining the output signal V .

time-domain model features frequency folding at 1 GHz be- automatically shifts the VCO low-gain characteristic, allowing
cause the Clock_Analyzer samples the nonlinear time-domain for a wide tuning range [10].
simulations at the VCO output frequency. Furthermore, we see The inputs of the CC block are the LF output voltage and
a second peak of the transfer function placed between 250–500 the reference voltage . For a given lock frequency, the CC
MHz (and its folded version placed between 750 MHz and 1 senses the difference between these two signals and, via integra-
GHz); this is created by the frequency folding produced by tion, it slowly varies the coarse control voltage in order to shift
the PFD, that is however partly filtered out by the LF (see [12, the VCO characteristic and keep the fine control voltage close to
Ch. 7.4]). Considering the -domain transfer function, at high the reference voltage. In order to be advantageous in this new ar-
frequencies, it differs from the other ones because it does not chitecture, the CC should present a narrow bandwidth and a low
take into account the sampling process introduced by the PFD. noise contribution to the output. Furthermore, due to stability is-
As another indication of the accuracy of the nonlinear time- sues, the implementation of the proposed DT-PLL requires an
domain model, we can sample the PLL output clock signal at the integrator with a time constant as large as 1 ms, which is an
frequency of the reference clock (i.e., take only one sample over issue for a fully integrated design because of the large capacitor
4) and compare the outcome of the Clock_Analyzer to the -do- required. To overcome this difficulty, the CC is implemented as
main model. As shown in Fig. 9(b), they are fully consistent. a – integrator. The output current of the differential opera-
tional transconductance amplifier (OTA) charges a 1-pF capac-
itor. To obtain the required narrow band (1-kHz unity gain fre-
IV. APPLICATION TO A DUAL-TUNING PLL quency), the OTA output is connected to the capacitor through
We apply our modeling approach to a PLL featuring a dual- a switch driven by a clock with duty cycle . This
tuning loop where the gain of the VCO, , is much smaller approach lowers the average current charging the capacitance of
than in a normal VCO in order to reduce the sensitivity of the the integrator by the factor [10].
PLL output to the noise generated by the PLL’s building blocks In order to analyze the DT-PLL with the nonlinear time-do-
[10]. To maintain a wide tuning range, the VCO characteristic main model, we modified the VCO model implementing the
is adjusted continuously with an analog coarse control signal. tuning surface with a 2-D LUT.
Thus, this DT-PLL presents a two-input VCO: a fine control We have then modeled the CC block as shown in Fig. 10(b).
signal and a coarse control signal [see Fig. 10(a)]. The fine con- The input of the block is the output of the LF, and it is compared
trol signal comes from the output of the LF, while the coarse with the reference voltage . The difference between these
control signal is provided by a coarse control (CC) block that two signals is multiplied by a signal, obtained with a counter
BIZJAK et al.: COMPREHENSIVE BEHAVIORAL MODELING OF CONVENTIONAL AND DUAL-TUNING PLLs 1635

block, that takes the value “1” for one period over 2048 pe-
riods of the reference clock and “0” elsewhere, thus modeling
the switch [10] that is implemented in the CC. Afterwards, the
signal is provided to a LUT that models the – structure used
to charge a capacitor [gain block and integrator in Fig. 10(b)].
The noise characteristic of the block is modeled by two dif-
ferent noise generators to take into account the cases when the
switch is either open or closed and it is added at the output of
the block (their spectrum is taken from TITAN simulations). Fi-
nally, two Constant blocks model the capacitor leakage current
and the initial output coarse voltage to start the simulation from
the steady-state condition.
Another important block to be modeled is the active loop
filter. In fact, during transient simulations, the op-amp that con-
stitutes the active LF can saturate and it is thus important to
properly model its behavior. As reported in Fig. 11, the input of
the model is the differential current . Starting from the input
current, the op-amp input differential voltage is computed
as the difference between the output voltage and the voltage
drop on the feedback impedance. This input voltage is fed back
to the CHP to determine the operation point of CHP switches.
The LF output voltage is then computed considering the satu-
ration characteristic of the op-amp (using an LUT) and its lim-
ited bandwidth, implemented with a transfer function block. The
model for the saturation of the op-amp does not take into ac-
count memory effects such as slow recovery from overload. This
simplification does not limit the model accuracy because of the
large time constant of the – block. Fig. 11. (a) Simulink implementation of the active LF of plot (b). The dif-
ferential input current coming from the CHP (I ) is modeled with the single
Given the three new building blocks, it is straightforward to ended input In1. The impedance of the feedback path Z is implemented with
build the model of the DT-PLL and to evaluate its performance. a transfer function block. Subtracting the voltage that drops on the impedance
We present hereafter three applications of the model: a transient Z from the output voltage V [Out1 in (a)], we obtain the input voltage V
[Out2 in (a)] that is fed back to the CHP. The limited bandwidth of the op-amp
simulation to understand the dynamic behavior of the DT-PLL, is considered with a transfer function block, while the saturation is implemented
the phase-noise comparison with a measured DT-PLL, and the with the LUT. The op-amp gain is set with the gain block. The gain, 2, after the
analysis of the output spurs. impedance Z transfer function considers the differential implementation of the
LF, hence the two impedances present on the two feedback of the op-amp. The
We will consider the DT-PLL described in [10] and the ex-
perimental data from the same reference. This DT-PLL is char-
0
gain, 1, just before the Out1 sets the characteristic of the active LF as nonin-
verting.
acterized by a reference frequency of 25 MHz and a feedback
division factor equal to 96. The VCO output frequency is then
2.4 GHz. The DT-PLL presents on its output a divider-by–6, that converges to . These results are consistent with the ex-
i.e., the output frequency is 400 MHz. perimental behavior in [10], where a frequency down step of
300 kHz is locked (i.e., 99% of the transient has been completed)
A. Transient Behavior by the DT-PLL in 0.8 ms (see [10, Fig. 10]).
Transient simulations are useful to understand how the Fig. 13 refers to a much larger frequency down step of 2 MHz.
DT-PLL reacts to an abrupt change of the reference frequency. In this case, cannot follow the frequency variation and thus
Hereafter we report two cases, one for small frequency down it does not lock the DT-PLL output frequency. In fact, we can
steps (Fig. 12) and the other for a large frequency down step see how goes down to the voltage equal to 1.5 V. The
(Fig. 13). These simulations are performed considering an ideal lock state is then reached thanks to that goes down until it
DT-PLL without noise. locks the DT-PLL output frequency and then makes going
For the small frequency step (200 kHz), the fine control signal back to .
of the VCO can follow very rapidly the frequency step, and it The results in Fig. 13 agree with the experiments in [10]
locks the DT-PLL at the desired output frequency. In order to where the transient for the frequency relock after a large fre-
do that, it has to move away from the reference voltage level quency step lasts about 6 ms (see [10, Fig. 11]). They demon-
(a differential voltage 0.75 V in these simulations), and this strate the usefulness and accuracy of the nonlinear time-domain
forces also the coarse control signal to move. The CC block in model in describing the full DT-PLL transient in spite of the
fact senses the difference between and and lowers the much different time constants involved.
coarse control signal of the VCO in order to let return to
. The “sample and hold” characteristic of the coarse voltage B. Phase Noise and Spurious Components
is apparent in Fig. 12; in fact, changes once every 2048 Fig. 14 compares the phase-noise PSD predicted by the non-
reference clock periods. Changes in induce steps in , linear time-domain model at the output of the DT-PLL with
1636 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 55, NO. 6, JULY 2008

Fig. 13. Simulated output frequency (top), coarse control signal (middle), and
Fig. 12. Simulated output frequency (top), coarse control signal (middle), and fine control signal (bottom) transient behavior caused by a frequency down step
fine control signal (bottom) transient behavior caused by frequency down step in the reference generator equal to 2 MHz. For this frequency step, the fine
in the reference generator equal to 200 kHz. For this frequency step, the fine control signal is not able to lock the new frequency (see top subplot) hence, it
control signal is able to lock the new frequency (see top subplot), then it goes 0
saturates to the differential voltage 1.5 V, i.e., its single-ended components
0
back to the reference voltage ( 0.75 V) due to the adjustment of the coarse saturate to the supplies, and only when the coarse control voltage has locked
control voltage. the output frequency, then the fine control voltage goes back to the reference
0
voltage ( 0.75 V, differential).

that given by the linear model and the experimental one [10].
For the sake of a fair comparison, we have modified the CC of the switch. This means that, only for one period every 2048
in the nonlinear time-domain model by removing the switch, periods of the reference clock, the – output current [the
while still taking into account the effect of the CC block on the output signal of the LUT in Fig. 10(b)] flows into the output
transfer function, by dividing the integrator output by a factor capacitance [the and the in Fig. 10(b)]. In this
, i.e., that used into the counter that drives the switch way, we also distinguish the noise produced by the CC when the
[see Fig. 10(b)]. We have also assumed that the noise produced switch is closed or open.
by the CC block at the output is equal to the one produced when Fig. 15(a) depicts the phase-noise PSD at the output of the
the switch is open. In fact, the block works for most of the time DT-PLL that has been obtained using the CC model presented
in this condition. This modification mimics the assumptions im- in Fig. 10(b). The new results are in good agreement with the
plicitly made in the linear model, and, indeed, we observe good experimental data and demonstrate the accuracy of the nonlinear
agreement between the two models and between them and the time-domain modeling approach. The number of points at low
experiments, apart from the spurs present in the latter, which are frequency is limited by the dimension of the vector containing
not accounted for by the models. Note that the main differences the instant of the crossing points of the VCO that, due to the
between the linear and the nonlinear time-domain model are due relevant simulation time, has been limited to 1.2 million points
to the fact that, in the linear model, we can load directly the mea- (corresponding to 3 ms of simulated time).
sured phase-noise PSD of the crystal oscillator, whereas in the Furthermore, we show [see Fig. 15(b)] how the nonlinear
nonlinear time-domain model the measured PSD of the crystal time-domain approach, unlike the linear model, lets us detect
is approximated with a linear piecewise function, which is sim- the spurious components caused by the switching behavior of
ilar to the one used for the VCO phase noise. the coarse control signal. Note that the spur at 30 kHz that is
The implemented nonlinear time-domain approach allows us visible in Fig. 15(b) is not related to the operation of the circuit.
to perform a more accurate simulation of the DT-PLL taking Although maximum attention has been paid during the measure-
into account the real behavior of the CC, namely the operation ment in order to isolate the chip from the environment, it seems
BIZJAK et al.: COMPREHENSIVE BEHAVIORAL MODELING OF CONVENTIONAL AND DUAL-TUNING PLLs 1637

The decision to graphically compare the spurs in dBc/Hz in-


stead of dBc has been taken because the only available measured
data are the PSD of the DT-PLL output phase noise and the SCR
for the first spur at 12.2 kHz, equal to 85.94 dBc [10]. We have
compared this latter value with the SCR computed with (6) that
yields a value of 86.77 dBc, demonstrating the capability of
the nonlinear time-domain analysis.

V. CONCLUSION
A flexible approach for the modeling of PLLs at the behav-
ioral level has been presented. Each building block is modeled
using a Simulink description of its input/output characteristic
and of the noise generation inside the block. The specifications
of each block can be extracted from circuit simulations or can
be guessed from the back of the envelope calculations. The
blocks can be combined together to implement different PLL
topologies.
This approach has been applied to the analysis of the tran-
Fig. 14. Phase noise at the output of the DT-PLL obtained by dividing the sient behavior of different PLL architectures. The lock tran-
1
sequence of  (defined in Section II-B) into four subsequences. In this case,
sient after a frequency step at the input has been compared with
the switch in the CC block of the nonlinear time-domain model is not simulated.
Parameters for the linear and nonlinear time-domain models are the same used time-consuming circuit simulation of the whole PLL. Simula-
in [10]. The measured phase noise of the reference oscillator is approximated tion of the output spurs due to CHP mismatch and of the spurs
by a flat region above 1 MHz. due to supply noise have been used to validate compact formulas
for these effects.
Also, we have compared the PLL transfer function provided
by the Fourier analysis of this nonlinear time-domain model
with the ones in the - and -domains, showing that none of the
latter are able to capture accurately the sampling phenomena in-
side the PLL.
Finally, to demonstrate the flexibility of the approach, we
have modeled a PLL featuring a dual control of the VCO. The
transient behavior, the phase-noise spectrum, and the frequency
spurs obtained with this approach are in good agreement with
the experimental data and demonstrate the limits of alternative
approaches.

ACKNOWLEDGMENT
The authors would like to thank E. Thaller and
E. Tatschl-Unterberger of Infineon Technologies for many
helpful discussions. They would also like to thank the reviewers
for many valuable suggestions to improve the quality of the
paper.

REFERENCES
[1] B. Razavi, RF Microelectronics. Upper Saddle River, NJ: Prentice-
Hall, 2000.
[2] S. Brigati, F. Francesconi, A. Malvasi, A. Pesucci, and M. Poletti,
“Modeling of fractional-N division frequency synthesizers with
Simulink and Matlab,” in Proc. 8th IEEE Int. Conf. Electron., Circuits
Syst., Sep. 2–5, 2001, vol. 2, pp. 1081–1084.
Fig. 15. Same data as in Fig. 14 but obtained with the Simulink model, taking [3] G. Manganaro, S. U. Kwak, S. Cho, and A. Pulincherry, “A behavioral
into account the operation of the CC switch. (a) This plot was obtained by di- modeling approach to the design of a low jitter clock source,” IEEE
1
viding the sequence of  (defined in Section II-B) into two subsequences. Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 50, no. 11,
(b) Zoom of (a) at low frequency. Filtering of the spurs occurs in the measured pp. 804–814, Nov. 2003.
curve. [4] M. H. Perrott, “Fast and accurate behavioral simulation of fractional-N
frequency synthesizers and other PLL/DLL circuits,” in Proc. 39th De-
sign Autom. Conf., Jun. 10–14, 2002, pp. 498–503.
[5] M. Kozak and E. G. Friedman, “Design and simulation of fractional-N
fairly possible to us that the spike is the result of the coupling of PLL frequency synthesizers,” in Proc. Int. Symp. Circuits Syst., May
an external noise source with the chip or the instrumentation. 23–26, 2004, vol. 4, pp. 780–783.
1638 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 55, NO. 6, JULY 2008

[6] S. Sancho, A. Súarez, and J. Chuan, “General envelope-transient for- Peter Thurner was born in Klagenfurt, Austria, in
mulation of phase-locked loops using three time scales,” IEEE Trans. 1971. He received the M.Sc. degree in electronic en-
Microw. Theory Tech., vol. 52, no. 4, pp. 1310–1320, Apr. 2004. gineering from the Graz University of Technology,
[7] Simulink 4.1 (Release 12) The MathWorks, Natick, MA, 2001 [On- Graz, Austria, in 1998.
line]. Available: http://www.mathworks.com/products/simulink/ He is currently with Infineon Technologies’ Devel-
[8] Matlab 6.1.0.450 (Release 12.1) The MathWorks, Natick, MA, 2001 opment Center, Villach, Austria, as a Mixed-Signal
[Online]. Available: http://www.mathworks.com/products/matlab/ Design Engineer with a focus on high-performance
[9] T.-C. Chen, “Where CMOS is going: Trendy Hype versus Real Tech- and high-speed clock systems in advanced CMOS
nology,” in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 2006, vol. technologies.
1, pp. 22–28.
[10] R. Nonis, N. Da Dalt, P. Palestri, and L. Selmi, “Modeling, design
and characterization of a new low-jitter analog dual tuning LC-VCO
PLL architecture,” IEEE J. Solid-State Circuits, vol. 40, no. 6, pp.
1303–1309, Jun. 2005.
[11] R. B. Staszewski, C. Fernando, and P. T. Balsara, “Event-driven sim- Roberto Nonis was born in Udine, Italy, in 1977.
ulation and modeling of phase noise of an RF oscillator,” IEEE Trans. He received the Laurea degree in management en-
Circuits Syst. I, Reg. Papers, vol. 52, no. 4, pp. 723–733, Apr. 2005. gineering and the Ph.D. degree in electronics from
[12] W. F. Egan, Frequency Synthesis by Phase Lock, 2nd ed. New York: the University of Udine, Udine, Italy, in 2002 and
Wiley-Interscience, 2000. 2006, respectively. His thesis involved phase-noise
[13] A. V. Oppenheim and R. W. Schafer, Discrete-Time Signal Pro- modeling in PLL-based frequency synthesizers. His
cessing. Englewood Cliffs, NJ: Prentice-Hall International, 1989. dissertation focused on the design of RF frequency
[14] N. Da Dalt, M. Harteneck, C. Sandner, and A. Wiesbauer, “Numerical dividers.
modelling of PLL jitter and the impact of its non-white spectrum on From September 2006 to September 2007, he was
the SNR of sampled signals,” in Proc. Southeast Symp. Mixed-Signal with LSI (formerly Agere Systems), Allentown, PA,
Design, Feb. 2001, pp. 38–44. where he was involved with the design of dynamic
[15] TITAN 7.0. Infineon Technologies, Munchen, Germany, 2005. comparators for ADCs. He is currently with Infineon Technologies, Villach,
[16] R. Nonis, P. Palestri, N. Da Dalt, and L. Selmi, “Phase noise modeling Austria, as a Mixed-Signal Design Engineer.
in phase locked loop frequency synthesizers,” in Proc. Austrochip, Oct.
2002, pp. 29–35.
[17] W. Rhee, “Design of high performance CMOS charge pumps in
phase locked loops,” in Proc. IEEE Circuits Syst. Symp., 1999, pp. Pierpaolo Palestri (M’05) received the Laurea
II-545–II-548. degree (summa cum laude) from the University
[18] J. Lu, B. Grung, S. Anderson, and S. Rokhsaz, “Discrete Z-domain of Bologna, Bologna, Italy, in 1998 and the Ph.D.
analysis of high order phase locked loops,” in Proc. IEEE Int. Symp. degree from the University of Udine, Udine, Italy, in
Circuits Syst., May 2001, vol. 1, pp. 260–263. 2003, both in electronic engineering.
[19] F. M. Gardner, “Charge-pump phase-lock loops,” IEEE Trans. In 1998, he joined the Department of Electrical,
Commun., vol. COM-28, no. 11, pp. 1849–1858, Nov. 1980. Mechanical and Management Engineering, Univer-
sity of Udine, as a Research Assistant in the field
of device simulation. From July 2000 to September
2001, he held a postdoctoral position with Bell Labo-
ratories, Lucent Technologies (now Agere Systems),
Murray Hill, NJ, where he was involved with high-speed silicon-germanium
bipolar technologies. In October 2001, he became an Assistant Professor and,
in November 2005, an Associate Professor with the University of Udine. His
research interests include the modeling of carrier transport in nanoscale devices
and the simulation of hot-carrier and tunneling phenomena in scaled MOSFETs
Luca Bizjak was born in Udine, Italy, in 1981. and nonvolatile-memory cells.
He received the B.S. and M.Sc. degrees from the
University of Udine, Udine, in 2003 and 2006,
respectively, both in electronic engineering. His
thesis concerned phase-locked-loop modeling for Luca Selmi (M’01) was born in 1961. He received
accurate time-domain simulations and clock analysis the Ph.D. degree in electronics from the University
software. of Bologna, Bologna, Italy, in 1992.
He is currently with Infineon Technologies’ In 2000, he became a Full Professor of Electronics
Development Center, Villach, Austria, as a Concept with the University of Udine, Udine, Italy. During
Engineer. His research interests are now focused on 1989–1990, he was a Visiting Scientist with Hewlett
power management units with applications to mobile Packard Microwave Technology Division, Santa
phones and portable electronics. Rosa, CA, where he was involved with the design
and characterization of gallium–arsenide devices
and circuits for high-frequency applications. During
1995–1996, he was a member of the IEDM technical
Nicola Da Dalt (M’03) was born in Vittorio Veneto, subcommittee on “Modeling and Simulation.” From 2001 to 2002, he held the
Italy, in 1969. He graduated in electronic engineering same position in the “Circuit and Interconnect Reliability” subcommittee. He is
(summa cum laude) from the University of Padova, presently a TPC member of the ESSDERC, INFOS, and ULIS conferences. His
Padova, Italy, in 1994. research interests include characterization and simulation of silicon devices,
From 1996 to 1998 he was with CSELT, Turin, with emphasis on Monte Carlo transport techniques and hot carrier effects
Italy, as a Concept Engineer for architectures and in MOSFETs and nonvolatile-memory cells, leakage currents, and reliability
synchronization of data transmission networks. of ultrathin oxides. More recently, he has been involved in research activities
Since 1998, he has been with Infineon Technologies’ on the design of integrated circuits for telecommunication. These activities
(formerly Siemens Semiconductors) Development have been conducted in cooperation with international research centers such
Center, Villach, Austria, as a Mixed-Signal Senior as Infineon Technologies (Villach, Austria, and Munich, Germany), Philips
Staff Engineer. His current position is as leader of Research Leuven, IMEC, LETI (Grenoble), Bell Labs/Agere Systems, and
a mixed-signal design group with a current focus on high-performance and the IBM T.J. Watson Research Center. He has coauthored approximately 140
high-speed clock systems in advanced CMOS technologies. papers, including approximately 30 IEDM papers.

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