Vector Control of Three-Phase Front End

Converter (FEC)

T1 T3 T5

vs1 is1 Ls Rs

vs2 is2 Ls Rs Ro Vdc

N C
vs3 is3 Ls Rs

T4 T6 T2

1
 I. INTRODUCTION

A three-phase AC to DC converter is often used to obtain a DC supply from three-

phase AC mains. Typical applications are UPS, battery charger, static frequency changer,
motor drives etc. As this type of converter is normally connected at the front end / utility
end of most of the power electronic systems, these are also called the front-end converter
(FEC). The use of three-phase diode/thyristor bridge rectifiers, as the frond-end converter
lead to the degradation in the power quality due to the input current distortion caused by
them. In the attempt to reduce their effects, various standards (IEEE-519 and IEC-555)
and recommendations have been introduced in order to limit the harmonics that an
individual load can inject into the utility.
The input current distortion caused by the bridge rectifiers (diode/thyristor bridge) can
be reduced by using a bulk input filter or harmonic traps. Sometimes it is also required to
have a converter with bi-directional power flow capability as in drives applications. In
such applications the attractive solution is to use a three-phase PWM AC to DC
converter. Hence the ideal requirements of an FEC are,
1. Sinusoidal input current at any given power factor (preferably unity)
2. DC bus voltage control
3. Bi-directional power flow
4. Fast dynamic response
- Should be able to track DC bus voltage reference and power reference
quickly.
The FEC can be controlled in a number of ways to satisfy the above objectives. In this
report the vector control approach is explained in detail along with the design of the
controller.

II. VECTOR CONTROL

In vector control method, the control is done on a rotating reference frame where the
sinusoidal quantities (voltage, current) appear stationary. It is easier to handle the active

2
and reactive powers separately. The controllers handle the DC quantities. Hence the
following points can be concluded,
- Decoupled control of active and reactive power
- Easy reference generation
- Controllers handle DC quantity

A. Three-phase PWM FEC

Fig.1 shows a three-phase PWM ac-dc converter. It has a three-phase PWM inverter.
The three-phase input is connected to the output of the three-phase inverter through three
inductors. The power circuit is similar to that of any three-phase electrical machine when
fed from a three-phase inverter. Three balanced input phase voltages vs1, vs2 and vs3 can be
thought of as the motor per-phase back emf with Ls and Rs as the per-phase inductance
and resistance respectively. The input to the system is the output of the three-phase PWM
inverter.

T1 T3 T5

vs1 is1 Ls Rs
vi1
vs2 Ls
N
is2 Rs
vi2 C
Ro Vdc
vs3 is3 Ls Rs
vi3

T4 T6 T2

Fig.1

Let us define the input voltages as follows,

v s1 = 2V s co s(ω t ).......................................................................................(1)
vs 2 = 2V s co s(ω t − 1 2 0 0 )...........................................................................(2 )
vs3 = 2V s co s(ω t − 2 40 0 )...........................................................................(3)

3
Where Vs is the rms value of the phase voltage. Transforming these voltages from three-
phase to two-phase stationary a-b reference frame we have,

3
v sa = 2V s cos(ω t )...................................................................................(4)
2
3
v sb = 2V s sin(ω t ).................................................................................. ..(5)
2

The voltage space vector vs can be defined as

3
v s = v sa + jv sb = 2V s e jω t ........................................................................(6)
2

Similarly considering any arbitrary phase angle, we can write the current space vector as

2 I s e(
3 jω t − Φ )
is = isa + jisb = ....................................................................(7)
2

Here a synchronous d-q reference frame, similar to vector control of electrical machines,
is selected such a way that the voltage space vector vs is directed along q axis as shown

in Fig.2 The reason for aligning vs along q axis is that in case of rotating electrical

machine the d axis represents the machine flux and q axis the input voltage.

q b
vs

d ω
θ
a
Fig.2

4
Similar analogy is followed here. However it is possible to direct vs along d axis. In the

present report we will consider the previous convention, i.e. q-axis corresponds to the
active power and d-axis corresponds to the reactive power.
Writing KVL (Fig.1) around the input side of the FEC,

d i s1
v s 1 = v i1 + L s + R s i s1 ................................................................................(8)
dt
di
vs 2 = v i 2 + L s s 2 + R s i s 2 ......................................................................... .....(9 )
dt
di
vs3 = v i 3 + L s s 3 + R s i s 3 ..............................................................................(1 0)
dt

Where vi1, vi2 and vi3 are the voltages across the output terminals of the inverter. The
equations (8-10) correspond to the three-phase, three-winding systems of any three-phase
rotating electrical machines. These can be transformed to equivalent two-phase two
winding system with same Ls and Rs. Multiplying both sides of (8) by ‘3/2’ and then

multiplying both sides of (9) and (10) by 3 we have

2
⎛3 ⎞
d ⎜ i s1 ⎟
3
v s 1 = v i1 + L s ⎝
3 2 ⎠ + R ⎛ 3 i ⎞ .........................................................(1 1)
s⎜ s1 ⎟
2 2 dt ⎝2 ⎠
⎛ 3 ⎞
d⎜ is 2 ⎟
3
vs 2 =
3
vi 2 + L s ⎝
2 ⎠ + R ⎛ 3 i ⎞ ...........................................(1 2 )
s⎜ s2 ⎟
2 2 dt ⎝ 2 ⎠
⎛ 3 ⎞
d⎜ is 3 ⎟
3
vs3 =
3
vi 3 + L s ⎝
2 ⎠ + R ⎛ 3 i ⎞ ............................................(1 3)
s⎜ s3 ⎟
2 2 dt ⎝ 2 ⎠

Subtracting (13) from (12) and using three-phase to two-phase transformation, we

have the corresponding equations in a-b reference frame as
d i sa
v sa = v ia + L s + R s i sa ...........................................................................(1 4 )
dt
di
v sb = v ib + L s sb + R s i sb ...........................................................................(1 5)
dt

5
 These equations can be written in terms of space phasor as

d is
v s = v sa + jv sb = v i + L s + R s i s .............................................................(16 )
dt

Where vi is the voltage space phasor corresponding to inverter output voltages vi1, vi2

and vi3. Equation (16) represents the space phasor equation in a-b (stationary) reference.

q
b
Vsq φ
vs
is
Isq d ω
Isd θ
a
Fig.3
This needs to be transferred to synchronously rotating d-q reference frame. Referring to
Fig.3 let us assume that the d-q frame is rotating counterclockwise direction at the
synchronous speed ‘ω’ (ω = 2πf) with ‘f’ as the supply frequency in Hz. The d axis is
making an angle θ with respect to stationary ‘a’ axis. The voltage and current space
phasors vs and is are shown in the same figure. It is assumed that the current space

phasor is is lagging the voltage space phasor by an angle ‘φ’, which is the power factor

angle. Equation (6) and (7) define the space phasors with respect to stationary a-b
reference frame. The same quantities can be defined with respect to synchronously
rotating d-q reference frame as,

v s = v sd + jv sq = 0 + jv sq ...........................................................................(17)

is = isd + jisq .............................................................................................(18)

6
 The same space phasors can also be expressed with respect to stationary a-b reference
frame as

( ) ( )
v s = ( v sa + jv sb ) = v sd + jv sq e jθ = 0 + jv sq e jθ ...................................(19)

( )
is = ( isa + jisb ) = isd + jisq e jθ ................................................................(20)

( )
vi = ( via + jvib ) = vid + jviq e jθ ...............................................................(21)

Substituting (19 – 21) in (16) the space phasor equation with respect to stationary a-b
reference frame becomes

( 0 + jvsq ) e jθ = ( vid + jviq ) e jθ + Ls dtd ⎡⎣( isd + jisq ) e jθ ⎤⎦ + Rs ( isd + jisq ) e jθ

⎛ dθ ⎞
( )
jvsq e jθ = vid + jviq e jθ + Ls e jθ
d
dt
( ) (
isd + jisq + jLs isd + jisq e jθ ⎜)
⎝ dt
( )
⎟ + Rs isd + jisq e
⎠
jθ

The above equation is still in stationary a-b reference frame. This can be transformed
− jθ
to synchronously rotating d-q reference frame by multiplying both sides of it by e as,

⎛ dθ ⎞
(
jv sq = vid + jviq + Ls ) d
dt
( ) (
isd + jisq + jLs isd + jisq ⎜ ) ( )
⎟ + Rs isd + jisq ..........(22)
⎝ dt ⎠

Equation (22) represents the space phasor equation of the system with respect to
synchronously rotating d-q reference frame. Separating the real and imaginary parts of
(22), we have two sets of equations corresponding to d-axis and q-axis respectively as
follows,
d
vid + Ls isd − ω s Ls isq + Rs isd = 0...........................................................................(23)
dt
d
viq + Ls isq + ω s Ls isd + Rs isq = v sq .........................................................................(24)
dt

Rearranging the above equations, we have,

7
 d
Ls isd + Rs isd = − vid + ω s Ls isq = vid ' ( say )..........................................................(25)
dt
d
Ls isq + Rs isq = − viq − ω s Ls isd + v sq = viq ' (say)...................................................(26)
dt

The left hand sides of the above two equations (23) and (24) corresponds to simple R-
L circuit of first order type. This is called the plant. The right hand sides of the same two
equations correspond to the DC excitations to the respective plants (also shown in fig.4).

Ls
d-axis Rs

i sd

v id = ( − v id + ω s Ls i sq )
'

q-axis
Ls Rs

i sq

v iq = ( − v iq − ω s L s i s d + v sq )
'

Fig.4

III. CONTROL OF FEC

There are two quantities to be controlled

(i) DC bus voltage
(ii) Input current
Hence there are two control loops
(1) DC bus voltage control loop
(2) Current control loop
In the control circuit DC bus voltage control loop is the outer loop as it is much slower
compared to inner current control loop. The control block diagram of the FEC is shown
in figure 5.

8
 d-q to a-b
transformation
*
Vdc * isq v iq'' v iq * v ia * v i1 *
+- +- ++ +- -1

DC bus Voltage q-axis current

controller controller

Vdc-fb isq-fb ω s Ls i sd v sq Two-ph vi2 *

G G e jθ to
Three-ph

isd * v id'' v id * v ib * vi3 *

+- +- -1

d-axis current
controller a-b to three-phase
isd-fb ω s Ls i sq transform ation

cos θ sin θ
G
Feed forward term

v i1 * G 1
V i1 Ls Rs v s1
G 2
is1 V s1
is 1
v i2 * G 3 Ls
S in e -T ria n g le T h re e -p h a s e V i2 Rs is 2
PW M G 4 in v e rte r
v * is2 Vs2
v s2
i3
G 5
Ls Rs
V i3
G 6
is 3 Vs3

Vdc-fb
Vd c D C b u s v o lta g e
sensor
Two-ph to Two-ph to
d-q transformation d-q transformation
v s1 v s1 v sa v sd is1 isa isd-fb
is1
Three-ph Three-ph
v s2 − jθ
e− jθ
to is2
Vs1+Vs2+Vs3=0
two-ph
e is1+is2+is3=0 to
two-ph
v s2 v s3 v sb v sq is2 is3 isb isq-fb

Three-phase to Three-phase to
a-b transformation a-b transformation
cosθ sinθ cosθ sinθ
Fig. 5

9
 IV. FEED FORWARD / DECOUPLING TERMS

Equation (23) shows that ‘d’ axis current ‘ isd ’ is not only depend on the ‘d’ axis voltage

but also on ‘q’ axis current ‘ isq ’. Similarly ‘q’ axis current ‘ isq ’ (equation (24)) depends

on the ‘d’ axis current ‘ isd ’. Referring to Fig.5, the control objectives are as follows.
''
1. The ‘d’ axis controller output ‘ vid ’ should only drive ‘d’ axis current

‘ isd ’through ‘d’ axis plant as per equation (27).

d
Ls isd + Rs isd = Gvid '' .............................................................................(27)
dt

''
2. The ‘q’ axis controller output ‘ viq ’ should only drive ‘q’ axis current

‘ isq ’through ‘q’ axis plant as per equation (28).

d
Ls isq + Rs isq = Gviq '' ..............................................................................(28)
dt

Where ‘G’ is the converter gain. Equating right hand sides of equations (25) and (27)
we have,

− vid + ω s Ls isq = Gvid ''

vid = [ − 1] × ⎡ Gvid '' − ω s Ls isq ⎤

⎣ ⎦
⎡ ω s Ls isq ⎤
vid = [ − 1] × ⎢ vid '' − ⎥G
⎣ G ⎦
vid = vid * × G ........................................................................................(29)
⎡ ω s Ls isq ⎤
vid * = [ − 1] × ⎢ vid '' − ⎥ ................................................................(30)
⎣ G ⎦

Similarly equating right hand sides of equations (26) and (28) we have,

10
 − viq − ω s Ls isd + v sq = Gviq ''

viq = [ − 1] × ⎡ Gviq '' + ω s Ls isd − v sq ⎤

⎣ ⎦
⎡ ω Li v sq ⎤
viq = [ − 1] × ⎢ viq '' + s s sd − ⎥×G
⎣ G G ⎦
viq = viq * × G .....................................................................................(31( a ))
⎡ ω Li v sq ⎤
viq * = [ − 1] × ⎢ viq '' + s s sd − ⎥ ...................................................(31(b ))
⎣ G G ⎦

Equation (30) and (31) may be used to find out the required feed forward terms for d-
axis and q-axis control. This is also shown in fig.5.

V. DESIGN OF CONTROLLERS

Isq * Isq
Vdc * KV (1 + STV ) KC (1 + STC ) G 1/ RS 1
Vdc
+_ STV
+_ STC 1 + STd 1 + STS K +_ SC

K2
Isq.fb 1 + ST2 IL
Vdc .fb
K1
1 + S T1

Fig. 6

Fig. 6 shows the block diagram of the entire system (controller and plant) of q-axis
only. The d-axis system will be similar to this and not reproduced here. In this diagram it
is assumed that all feed forward terms are accurately acting on the system.

KV :Voltage controller gain

KC :Current controller gain
K1 :Gain in the voltage sensing path
K2 :Gain in the current sensing path
TV :Voltage controller time constant
TC :Current controller time constant
T1 :Voltage sensing path time constant

11
T2 :Current sensing path time constant
Td :Converter delay (normally Ts/2)
Ts :Switching time period = 1/fsw.
IL :Load current.
K : A constant. May be found out from input-output power balance as follows

Considering unity power factor case,

⎛ 2Vsq ⎞ ⎛ 2 I sq ⎞ 2
Total power = Vdc.Idc = 3Vrms ( phase) .I rms ( phase) = 3. ⎜ ⎟ .⎜ ⎟ = Vsq I sq
⎝3 2 ⎠ ⎝3 2⎠ 3

2 Vsq
I dc = I sq = K .I sq
3 Vdc
………………………………………………………….(32)
2 Vsq 2 ⎛ VLL ( Rms ) ⎞
K= = ⎜ ⎟
3 Vdc 3 ⎝ Vdc ⎠

A. Design of current loop

The current loop is shown in Fig. 7. Using TS = TC it is possible to cancel out the
effect of plant time constant. With this, the close loop transfer function may be obtained
as given below. Here a damping factor of ξ=0.707 has been considered to obtain the
expression for KC.

I sq * I sq
K C (1 + STC ) G 1/ RS
+_ STC 1 + STd 1 + STS

K2
I sq .fb 1 + ST2

Fig. 7

It should be noted that here the second order pole (1+STd)(1+ST2) has been approximated
as a first order (1+S (Td+T2)) with σ = Td+T2. This is because the operating region is

12
close to zero frequency and both frequencies ((1/T2) and (1/Td)) are far away from that.
Hence for the purpose of controller design such approximation is valid.

Isq (s)
=
( KCG / Rs ) (1+ ST2)
Isq*(s) STs (1+ ST2 )(1+ STd ) + ( KCG / Rs ) K2 1
= 2ξω n ; ξ =
1
;
σ 2
Isq (s)
≈
( KCG / Rs ) (1+ ST2) KC GK 2
Isq*(s) STs (1+ S(T2 + Td )) + ( KCG / Rs ) K2 ωn2 =
RsTsσ
Isq (s)
=
( KCG / Rs ) (1+ ST2)
Isq*(s) STs (1+ Sσ ) + ( KCG / Rs ) K2 RsTs
KC =
⎛ KCG ⎞ 2GK 2σ
⎜ ⎟ (1+ ST2 ) TC = TS
Isq (s) σ
= ⎝ ⎠
RsT s
*
Isq (s) S ⎛ K GK ⎞
S2 + + ⎜ C 2 ⎟
σ ⎝ RsTsσ ⎠

With this the current controller transfer function is given in (33).

I sq ( s )
=
1 (1 + ST2 )
( )
............................................................................(33)
I sq* ( s ) K 2 1 + 2σ S + 2σ 2 S 2

It should be noted that the presence of any pole in the feed back loop (1+ST2), appears
as zero in the close loop transfer function. In order to cancel out its effect, the reference
to the current controller may be modified as shown in Fig. 8. With this the overall
transfer function of the current loop is given by (34).

I sq ( s ) 1/ K 2
=
( )
………………………….…………..……….(34)
I sq* ( s ) 1 + 2σ S + 2σ 2 S 2

13
 I sq * G 1/ R S
I sq
1 K C (1 + STC )
1 + ST2
+_ STC 1 + STd 1 + STS

K2
I sq .fb 1 + ST 2

Fig. 8

B. Design of voltage loop

The outer voltage control loop is shown in Fig. 9. Here the inner current loop transfer
function has been approximated as

I sq ( s ) 1/ K 2
=
*
I sq ( s ) (1 + 2σ S )

The reasons behind this are as follows,

1. To realize the current loop as a first order system for the purpose of design.
2. The outer voltage loop is much slower compared to it.
3. Multi-order systems are difficult to design.

Vdc * Vdc
Kv (1 + STv ) 1/ K2 1
+_ STv 1 + 2σ S K CS

Vdc.fb K1
1 + ST1

Fig. 9

14
 The order of the system, even after approximation, is more than two. The zero of the
voltage controller may not be used to compensate the pole (1+2σS) because in that case
there will not be any ‘S’ term present, in the characteristic equation as shown in (35).

Vdc ( s ) KV K (1 + ST1 )
= …………………………..…….…(35)
Vdc* ( s ) (1 + ST1 )CK 2TV S 2 + KV KK1

This will lead to instability. Hence to design the outer voltage loop a different method
needs to be followed. Here will follow the method of ‘symmetric optimization’.
Loop gain is given in (36)

KV KK1 (1 + STV ) / K 2
G(S ) H (S ) = …………………………………..(36)
STV (1 + 2σ S )(1 + ST1 )CS

The speed loop is much slower compared to current loop. Hence the following
approximation holds good.

(1 + 2σ S )(1 + ST1 ) ≈ (1 + (2σ + T1 ) S ) = 1 + δ S

Where δ = T1+2σ. With this the loop gain is given in (37)

⎛ K KK ⎞ (1 + STV ) K e (1 + STV )
G(S ) H (S ) = ⎜ V 1 ⎟ =
⎝ K 2 ⎠ STV (1 + δ S )CS STV (1 + δ S )CS …………(37)
K KK
Ke = V 1
K2

Here the poles of the system are (STV), (SC) and (1+δS). Of these we can control only
(STV) as the others like (CS) is decided by the plant and (1+δS) is decided by the current
loop. Now the task is to place the pole (STV) in appropriate position to ensure sufficient

15
gain margin and phase margin. As the pole (CS) is associated with dc bus capacitor (large
valued) we can set the following inequalities.

1 1 1 1
<< ; and <<
C TV C δ

Now we don’t have idea about the relative positions of (1/TV) and (1/δ) as TV is not
yet decided. Let us consider both possibilities.

1 1
Case (a) >
TV δ

The corresponding gain and phase plots are given in Fig. 10. Hence in this case we
have phase margin equal to (-φ+1800), which is a negative quantity. Hence the above
assumption leads to instability.

dB 1
TV
1 1 ωc
C
δ
Phase

φ
180
270

Fig. 10

1 1
Case (b) <
TV δ

16
 The corresponding gain and phase plots are given in Fig. 11. Hence in this case we
have phase margin equal to (-φ+1800), which is a positive quantity. Hence the above
assumption leads to a stable design.

dB 1
δ
1 1 ωc
C TV
Phase

φ
180
270

Fig. 11

Next question is where to place the crossover frequency ωC in between (1/TV) and
(1/δ). The standard procedure is to place ωC in the geometrical mean of them. Let us
consider (TV = a2δ). Where a is any number 2,3,4……… With this the expression for ωC
becomes

1
ωC =
aδ

The objective is to select the proper value of Ke of equation (37) such a way that

K e 1 + (ωcTV ) 2
G ( jω ) H ( jω ) ω =ω = 1 =
C
ωc 2CTV 1 + (ωcδ )2
C
Ke = ; substituting the expression for K e
aδ
CK 2
KV = ; and TV = a 2δ
K1Kaδ

17
 The expression for phase margin is given below

⎛1⎞.
φ m = tan − 1 ( a ) − tan − 1 ⎜ ⎟
⎝a⎠

As an example, for a = 2, φm = 360. Hence selecting a suitable ‘a’, desired phase

margin may be achieved.

Vdc* Vdc
1 KV(1+STV) 1/ K2 1
(1+ ST1)(1+ STV ) +_ STV 1+ 2σS K CS

Vdc.fb K1
1+ ST1

Fig. 12

As mentioned earlier, the presence of pole (1+ST1) will also appear as zero in the
overall transfer function. Referring to (37) one additional zero (1+STV) will also appear
in the close loop transfer function. Hence to cancel out their effect the voltage reference
may be modified as shown in Fig. 12.

C. Load current feed-forward

Load current feed-forward may be added in the controller to improve the dynamic
response of the system. In order to do this the load current is required to sense using a
current sensor. Equation (32) is reproduced in (38). This relates the steady state load
current Idc with Isq.

2 Vsq
I dc = I sq = K .I sq (38)
3 Vdc

18
 At steady state the output of the voltage controller should be zero and the load current Idc
should set the reference current for the q-axis current controller as shown in Fig. 13. IL(fb)
is the sensed load current.

IL(fb) 1 d-q to a-b

transformation
K
Vdc * isq* v iq'' v iq * v ia * v i1 *
+- ++- ++ +- -1

DC bus Voltage q-axis current

controller controller

Vdc-fb isq-fb ωs Ls isd v sq Two-ph vi 2 *

G G e jθ to
Three-ph

isd* v id'' v id * v ib * vi 3 *
+- +- -1

d-axis current
controller a-b to three-phase
isd-fb ωs Ls isq transformation

cosθ sinθ
G
Feed forward term

Fig. 13

19
 Three-phase shunt active filter

I. INTRODUCTION

As mentioned in the previous section, three-phase diode bridge rectifiers or six-pulse

thyristor converters are extensively used in many high-power low-cost applications
leading the degradation in the power quality due to the current distortion. In the attempt
to reduce their effects, various standards (IEEE-519 and IEC-555) and recommendations
have been introduced in order to limit the harmonics that an individual load can inject
into the utility. The input current distortion caused by bridge converter (Diode/Thyristor
bridge) may be reduced by connecting a PWM rectifier. Again, there are applications,
where a dc bus voltage less than the peak line-line ac voltage is required. This may not be
achievable in case of a PWM boost rectifier without using an additional conversion stage.
Thus in many applications it is proffered to use six-pulse thyristor/diode rectifier
compared to PWM rectifier. To meet the rigid harmonic standard an active power filter
may be used at the input to the rectifier. The filter will supply only the harmonic currents
to the rectifier while the fundamental component of current will be supplied from the
input source
Active filter is actually a voltage source inverter connected in parallel to the point of
common coupling (PCC) between utility and grid. Active filters are employed for
reactive current and harmonic current compensation. The voltage source inverter is
controlled in such a way, as to inject the reactive and harmonic current demanded by the
utility.
Fig. 1 shows the single line block diagram of a system containing a six-pulse rectifier
and an active power filter. It is assumed that a large inductor is connected at the dc bus of
the phase controlled rectifier to make the dc bus current constant. The nature of input
current drawn by the rectifier is also shown in Fig. 1. It has fundamental and harmonic
components. The active filter is required to supply locally the harmonic component of the

20
 load current to the rectifier. The input source supplies the fundamental component of the
load current.

Ilo a d
is (t) iL (t)

AC ic (t) P h a s e c o n tro lle d

R e c tifie r
v s 1 2 ,v s 2 3 il1 ,il2

ic 1 ,ic 2

V dc
C o n tro lle r

A c tiv e F ilte r
G a te p u ls e s
(G 1 -G 6 )

Fig. 1

II. CONTROL OF ACTIVE FILTER

Assumptions:

1.The load is balanced in nature.

2.There is no control over the voltage at the point of common coupling.

Load currents are required to get the information of amount of harmonic current and
reactive current demanded by the non-linear load. In this present study, a phase-
controlled rectifier is taken as a non-linear load (Fig 1).

3-2 phase Transformation

21
 (t) = ( t ) ..................................................................................................................................(1a )
2
i i
la l1
3

(t) = ⎡i ( t ) − i ( t ) ⎤ ................................................................................................................(1b )
3
i
lb
2 ⎣ l2 l3 ⎦

b-Axis

q-Axis

ω
d-Axis
ωt
θ
a-Axis

Fig. 2

In the above figure, θ is the angle between stationary a-axis and d-axis. The d-q axes
is rotating at a speed of ω (2 π f ) with respect to stationary coordinate (a-b), where f is
the line frequency. If at t=0, q-axis is aligned with a-Axis, then at any time instant, ‘t’ the
angle between q-Axis and a-Axis is ω t . d-Axis is lagging q-Axis by 90 degree. Hence,

22
 π
θ = ωt − .........................................................................................................................( 2 )
2

2-Phase-DQ Transformation

ild ( t ) = ila ( t ) .cos θ+ ilb ( t ) sin θ.................................................................................................................................( 3a )

ilq ( t ) = ilb ( t ) .cos θ− ila ( t ) sin θ.................................................................................................................................( 3b)

ld ( t )..........................................................................................................( 4a )
ild ( t ) = Ild + i±

lq ( t )..........................................................................................................( 4b )
ilq ( t ) = Ilq + i±

Ild and Ilq are the dc components of the load current corresponding to the fundamental

component. i± ±
ld ( t ) and i lq ( t ) correspond to the harmonic components of iL .

Applying KCL at the point of common coupling (PCC),

is1 ( t ) = ic1 ( t ) + il1 ( t ) ......................................................................................................( 5a )

is2 ( t ) = ic2 ( t ) + il2 ( t ) .....................................................................................................( 5b )
is3 ( t ) = ic3 ( t ) + il3 ( t ) .....................................................................................................( 5c )

is1 ,is 2 ,is3 are the source currents for R,Y and B phases respectively.

23
i c1 ,i c 2 ,ic3 are the compensator currents for R,Y and B phases respectively.
il1 ,il2 ,il3 are the load currents for R,Y and B phases respectively.

In space phasor notation, KCL can be written as,

isa ( t ) + jisb ( t ) = ⎡⎣ica ( t ) + jicb ( t ) ⎤⎦ + ⎡⎣ila ( t ) + jilb ( t ) ⎤⎦ ..................................................( 6 )

− jθ
Multiplying both side of the above equation with e , we get

⎡⎣isa ( t ) + jisb ( t ) ⎤⎦ e− jθ = ⎡⎣ica ( t ) + jicb ( t ) ⎤⎦ e− jθ + ⎡⎣ila ( t ) + jilb ( t ) ⎤⎦ e− jθ

[ isd ( t ) + jisq ( t )] = [ icd ( t ) + jicq ( t )] + [ ild ( t ) + jilq ( t )].............................................(7)

Equating real and imaginary part of the above equation we get,

isd ( t ) = icd ( t ) + ild ( t ).....................................................................................................(8.a)

isq ( t ) = icq ( t ) + ilq ( t ).....................................................................................................(8.b)

Equation. (8.b) can be written as,

I sq + i±
sq ( t ) = ( I cq + icq ( t )) + ( I lq + ilq ( t )).......................................................................(9)
± °

If we equate the DC components from the both sides of the equation

I sq = I cq + I lq .................................................................................................................(10)

As the shunt active filter is not drawing active power from the grid, active power
demanded by the load is totally supplied by the source.

24
 Hence, I sq = I lq and I cq _ ref is decided by the DC bus voltage controller, to maintain

the DC bus at its nominal value. If we equate the ac components of the equation. (9)

sq ( t ) = icq ( t ) + ilq ( t )......................................................................................................(11)

i± ± °

The active filter should work such that, the harmonic current demanded by the non-linear
load is not drawn from the source but supplied by the active filter locally.

Hence, i±
sq ( t ) = 0

cq ( t ) = −ilq ( t )
i± °

Therefore, q-axis current reference can be generated in the following way,

icq _ ref = I cq _ ref − i°

lq ( t ).................................................................................................(11.a)
icq _ ref = PI(VDC _ ref −VDC )−( ilq ( t )− Ilq ) .......................................................................................(11.b)

The dc component of the q-axis load current is generated by employing a low-pass

filter of cut-off frequency of 30 Hz. Equation (8.a) can be written as,

I sd + i±
sd ( t ) = ( I cd + icd ( t )) + ( I ld + ild ( t ))...................................................................(12)
± ±

If we equate the DC components from the both sides of the equation

I sd = I cd + I ld ...................................................................................................................(13)

As the active filter has to compensate for the demanded reactive power by the load
and maintain the desired power factor at source side,

25
I cd _ ref = I sd _ ref − I ld ......................................................................................................(14)

I sd _ ref , is decided by the operating power factor at the grid side.

Equating the ac components of the equation. (12), we get

sd ( t ) = icd ( t ) + ild ( t )......................................................................................................(15)

i± ± ±

The active filter should work such that, the harmonic current demanded by the non-
linear load is not drawn from the source but supplied by the active filter locally. Hence,

i±
sd ( t ) = 0

cd ( t ) = −ild ( t )................................................................................................................(16)
i± ±

Therefore, the d-axis current reference is generated by,

icd _ ref = I sd _ ref − I ld − i±

ld ( t ).......................................................................................(17.a)

icd _ ref = I sd _ ref − ild ( t )...............................................................................................(17.b)

From the knowledge of unit vector and d-q axis current references, current references
in stationary coordinate can be calculated.

ica _ ref = icd _ ref cos θ − icq _ ref sin θ .............................................................................(18.a)

icb _ ref = icq _ ref cos θ + icd _ ref sin θ .............................................................................(18.b)

26
 Figure 3 explains the block diagram of current reference generation.

isd_ref

+ ica_ref
ila 2-Phase- ild - icd_ref DQ-
il1 3-2-Phase
il2 DQ 2-Phase
il3 Trans. ilq Trans
ilb Trans. - - icb_ref
+ +icq_ref
cut-off = 30Hz

cosθ sinθ cosθ sinθ

Vdc*
+
-

Vdc Fig. 3: Block Diagram of Current Reference Generation

Unit Vector Generation

In the previous section, it is well understood that, unit vector ( e jθ ) is required for the
ab-dq transformation of load currents and the reverse transformation (dq-ab) of d-q axes
current references (refer fig. 3).

27
 In order to generate unit vectors ( cos θ ,sinθ ) synchronized with the grid voltage,
algorithms like Phase Locked Loop (PLL) are generally used. The presence of the
harmonics in the grid voltages results in the distortion of the unit vectors derived from
them. To avoid this kind of problem the following scheme has been adopted to generate
the unit vectors.

Low pass filter

Vs1 Vsa
3-phase x
to cut off = 50Hz cut off = 50Hz cosθ
2 Phase Normalisation
Vs2 Transformation
sinθ
Vsb y

cut off = 50Hz cut off = 50Hz

Low pass filter

Fig. 4: Block Diagram of Unit vector Generation

Let us define the input voltages as follows,

v s1 = 2V s co s( ω t )......................................................................( 1 9 .a )
vs 2 = 2V s co s( ω t − 1 2 0 0 )..........................................................( 1 9 .b )
vs3 = 2V s co s( ω t − 2 4 0 0 )........ ..................................................( 1 9 .c )

Where Vs is the rms value of the phase voltage. Transforming these voltages from three-
phase to two-phase stationary a-b (or α-β) reference frame we have,

28
 3
v sa = 2V s cos( ω t )..................................................................( 20 .a )
2
3
v sb = 2V s sin( ω t )...................................................................( 20 .b )
2

Two low pass filters (in cascade), with cut-off at 50 Hz, are used to generate a delay of
900 and also to suppress any noise present in Vsa and Vsb (Fig. 3).
π
As, θ = ω t − ,
2
The outputs of the filters are proportional to cosθ and sinθ respectively. These are then
normalized to get the required unit vectors cosθ and sinθ.

From figure 4, we can write

Vs π
x= cos( ω t − ) − − − − − − − − − − − − − ( 21.a )
2 2
V π
y = s sin( ω t − ) − − − − − − − − − − − − − ( 21.b )
2 2

Therefore, after normalization we get,

x
cos θ = − − − − − − − −( 22.a )
x2 + y 2
y
sinθ = − − − − − − − −( 22.b )
x2 + y 2

Current controller
Quantities required to be sensed for controller
a) 2, load currents (il1, il2)
b) 2, compensator currents (ic1, ic2)
c) 2, line voltages (vs12, vs23)
d) DC bus voltage (Vdc)
The total system is described in the following figure.

29
 U s12
U n it
V e c to r
U s23 G e n e ra
to r
s in θ co sθ
is d * ic a * U c1*
+ P u ls e -
_
il1 C u rre n t re f. C u rre n t U c2* w id th
g e n e ra to r c o n tro lle r m o d u la to r
il2 ic b * U c3*
+
-

G 1 -G 6

D C bus
V dc* ic a 3 -2 ic 1
v o lta g e A c tiv e
+ phase
- c o n tro lle r ic b ic 2 F ilte r
V dc tra n s .

Fig. 5: Block Diagram of total Control system

The current reference generator and unit vector generator is described in the previous
section.

Design of Current Controller

Let v f 1,v f 2 ,v f 3 be the active filter output phase voltages, then the filter equations can be

written as

dic1( t )
vs1( t ) = Rs ic1( t ) + Ls + v f 1( t ) − − − − − − − − − −( 23.a )
dt
di ( t )
vs 2 ( t ) = Rs ic 2 ( t ) + Ls c 2 + v f 2 ( t ) − − − − − − − − − ( 23.b )
dt
di ( t )
vs 3 ( t ) = Rs ic3 ( t ) + Ls c3 + v f 3 ( t ) − − − − − − − − − ( 23.c )
dt

30
Using three phase to two phase transformation, the active filter circuit can be modeled as

dica ( t )
vsa ( t ) = Rs ica ( t ) + Ls + v fa ( t ) − − − − − − − ( 24.a )
dt
di ( t )
vsb ( t ) = Rs icb ( t ) + Ls cb + v fb ( t ) − − − − − − − ( 24.b )
dt

The effect of grid voltages, vsa ( t ),vsb ( t ) can be compensated using feed forward
technique as shown in the Fig. 6

The plant is represented by a first order lag along with the input voltage terms for both a-
axis and b-axis. The plant equations are as follows,

dica ( t )
Rs ica ( t ) + Ls = vsa ( t ) − v fa ( t ) − − − − − − − ( 24.a )
dt
di ( t )
Rs icb ( t ) + Ls cb = vsb ( t ) − v fb ( t ) − − − − − − − ( 24.b )
dt

The a-axis plant and controller are given in Fig. 6

vsa
G

+
i*ca - ica
+ K c ( 1 + s.Tc ) G + 1
. 1 + sTd Rs ( 1 + sTs )
G s.Tc
ica - -

vsa
31
i*ca 1
1 + s.Tc G Rs
Kc
+ s.Tc 1 + s.Td 1 + s.Ts
-
ica

K1

ω n2
i*ca ( t ) ica ( t )
s 2 + 2ξω n s + ω n2

Fig. 6
Proportional-Integral Controller parameters are given by,

1
ωn =
2ξ Td
32
 Ls
Tc = Ts = ;
Rs

RsTs
Kc =
4ξ K1GTd
2

If we consider the converter as only gain,

Then the parameters of the PI- controller is given by

Ls RsTs
Tc = Ts = ; Kc =
Rs Tcl K1G

Tcl = Closed loop time constant

K1 = Current sensor gain

G= Converter gain
Td = Time delay of the converter

ξ= Damping factor for the closed loop system

ω n = cut-off frequency of the closed loop transfer function

The resulting current controller is described in block diagram in Fig.7

Usa/G

-
ica_ref + -1
+
-
Uc1*
2-3 Phase
Transform Uc2*
ica ation
Uc3*

+ +
icb_ref -1
- -

Usb/G
icb
33
 Fig. 7

Three-Level Inverters

V d c /2
T11 T 21 T31

0
T 12 P1 T22 P2 T32 P3

34
T13 T23 T33
V d c /2
The above figure shows the functional equivalent circuit of a three phase three level
inverter realized using ideal switches. Each pole of the three level inverter will have three
voltage levels with respect to mid-point of DC bus referred as ‘o’ in the figure. Actually,
each phase of the inverter is a single pole triple throw switch.

For example, when pole ‘P1’ of phase-R is connected to throw ‘T11’

VRO= Vdc/2;
When pole ‘P1’ of phase-R is connected to throw ‘T12’
VRO= 0;
When pole ‘P1’ of phase-R is connected to throw ‘T13’
VRO= - Vdc/2;
Similar way, VYO and VBO will have three voltage levels (Vdc/2, 0, -Vdc/2). The line
voltages will have five voltage levels; - Vdc, - Vdc/2, 0, Vdc/2, Vdc. (Fig 2)

35
This concept can be extended to M-level inverters. Each pole of M-level inverter will
have M voltage steps and line voltage will have (2M-1) voltage steps. The inverters with
voltage level three or more are referred as multilevel inverters in the literature.

Vdc
2

π +α 2π −α
VRO α
π 2π
π −α π
4π 5π 2π
3 3 3 3

Vdc
−
2
Vdc
2
2π
−α 5π
3 +α
VYO 2π 5π
−α
3

+α 3
3
Vdc
−
2
V dc
2

VBO

Vdc
−
2
Vdc
V dc
2

VRY
Vdc
−
2

−Vdc

36
 Fig 2: Pole voltages (VRO,VYO, VBO) & Line Voltage (VRY) of a Three-level
Inverter

For medium voltage application, multilevel inverters are more suitable compared to the
conventional two-level inverters as
• It is possible to synthesize the higher voltages using power devices of lower
rating.
o Multilevel inverters offer increased number of voltage levels which leads
to better voltage waveform and reduced total harmonic distortion (THD) at
the output.
o Multilevel inverters offer better performance at low switching frequency.
This results in reduced switching loss.

In figure 1, the switch P1-T11 has to block a voltage of -Vdc (maximum) when OFF and
has to carry bi-directional current when ON. The switch P1-T13 has to block a voltage of
+ Vdc (maximum) when OFF and has to carry bi-directional current when ON .The switch
P1-T12 has to block a bipolar voltage of Vdc/2 and has to carry a bi-directional current.

Diode Clamp Inverter

The three level diode clamp inverter is also called neutral point clamped (NPC) inverter.
This is one of the realizations of the functional equivalent circuit of a three level inverter
(Fig. 1). Fig. 3 shows the power circuit of a three phase three level NPC inverter. Node
‘o’ indicates the mid point of dc bus. Switches ( S R1 , S R′ 2 ) of phase R, ( SY 1 , SY′ 2 ) of
phase Y and ( S B1 , S B′ 2 ) of phase B are the main devices operating as modulating
switches for the PWM. S R 2 , S R′ 1 , SY 2 , SY′ 1 , S B 2 , S B′ 1 are the auxiliary switches to
clamp the output voltage to the mid-point(node o) together with the diodes
DR1 ,DR 2 ,DY 1 ,DY 2 ,DB1 and DB 2 .

37
The switch P1-T11 is realized by ( S R1 ,S R 2 ), P1-T12 is realized by ( S R 2 ,S R′ 1 ,DR1 ,DR 2 )
and P1-T13 is realized by ( S R′ 1 ,S R′ 2 ). For phase Y and B the switch realization follows as
given below:

P2-T21---------------------------- ( SY 1 ,SY 2 )
P2-T22---------------------------- ( SY 2 ,SY′ 1 ,DY 1 ,DY 2 )
P2-T23---------------------------- ( SY′ 1 ,SY′ 2 )

P3-T31---------------------------- ( S B1 ,S B 2 )

P3-T32---------------------------- ( S B 2 ,S B′ 1 ,DB1 ,DB 2 )

P3-T33---------------------------- ( S B′ 1 ,S B′ 2 )

The switch status, definition of state and pole voltage of phase R of three level diode
clamp inverter are given in Table 1

S R1 SR2 S R′ 1 S R′ 2 DR1 DR 2 VRO

ON ON OFF OFF OFF OFF +Vdc/2

OFF ON ON OFF ON OFF 0
OFF ON ON OFF OFF ON 0
OFF OFF ON ON OFF OFF - Vdc/2

Table 1: Diode clamp inverter: Switch status and definition of state for phase R

S R1 SY 1 S B1

C D R1 DY1 D B1

S R2 SY 2 SB2

38
 Fig.3: Three level diode clamp inverter

Sine Triangle PWM(SPWM)

SPWM is the most widely used PWM technique for inverters of two and more levels. The
basic principle of the bipolar PWM used in two level inverters is as follows. The
reference signal ( vr ) which is generally sinusoidal, is compared with the high frequency
triangular wave ( vc ) of constant amplitude, Vc . At any instant of time the PWM output

39
will be high (State ‘+’) for vr > vc and output will be low (State ‘-’) for vr < vc as
illustrated in fig. 4.

40
 Fig. 4: Pole voltages (VRO) and Line voltage (VRY) of a Two-level Inverter
operating at fundamental frequency of 50Hz .PWM carrier frequency is 1 KHz.

The modulation index is defined as

Vr
Mi = ,
Vc

where Vr is the peak of the reference and Vc is the peak of the triangle. By varying Vr

and keeping Vc constant, that is by varying M i , the amplitude of the fundamental

component of the output will be varied. Similarly by varying the frequency of vr , the
frequency of the fundamental component of the output waveform can be varied.
The pulse number, P is defined as
f sw
P= ,
Fs

where f sw is the switching frequency and Fs is the frequency of vr . For two level

inverters, f sw = f c , where f c is the frequency of vc . For three phase inverters, the same

carrier signal vc is used for all the three phases and three reference signals are phase

2π
displaced by radians are used for each phase. The above principle is easily extended
3
to three level and other multilevel inverters. Some of the approaches for the
implementation of SPWM for three level inverters are discussed below.

Multiple Carrier Method or Unipolar Modulation

In this method, two carrier signals ( vt1 ,vt 2 ) can be in phase opposition (PO-SPWM) or in

phase (IP-SPWM). In both approaches the switching logic is decided as follows.

41
 Condition Switch status for R phase State VRO
v*R > vt1 and v*R > vt 2 S R1 = ON ,S R 2 = ON Vdc
S R′ 1 = OFF ,S R′ 2 = OFF ‘+’ 2

v*R < vt1 and v*R > vt 2 S R1 = OFF ,S R 2 = ON

S R′ 1 = ON ,S R′ 2 = OFF ‘0’ 0

v*R < vt1 and v*R < vt 2 S R1 = OFF ,S R 2 = OFF Vdc

−
S R′ 1 = ON ,S R′ 2 = ON ‘-’ 2

For M i = 1, the fundamental component of the inverter output voltage will be maximum.

Vdc
The maximum amplitude of the fundamental component is given by V1 peak = and
2
the RMS value is given by V1rms = 0.35Vdc .

So the maximum value of V1rms in linear modulation range is 78% of that of square wave
output. In this type of SPWM switching will take place between state ‘+’ and state ‘0’
during the positive half cycle of the fundamental and between state ‘-’and state ‘0’ in the
negative half cycle of the fundamental. The switching frequency f sw = f c 2 , where f c is

the frequency of vt1 and vt 2 . Compared to two level inverter, for a given carrier

frequency ( f c ), the switching frequency ( f sw ), will be half.

In Fig. 5, the IP-SPWM is explained for one carrier time period ( Tc = 1 f c ). From the
figure the sequence of the inverter states applied for one half of the carrier period (sub-
cycle), are found to be,
( +00 ) → ( 000 ) → ( 00− ) → ( 0 − − ) . In the next sub-cycle the sequence retraces the path
it came through and reaches the starting vector. The vectors applied for a total carrier
time period are as below:
ur ur ur ur ur ur ur
(V 1 → V z → V 2 → V 1 → V 2 → V z → V 1 ) . The sequence obeys the rule of Space-
Vector PWM for three-level inverter (as shown in Fig. 6).

42
+1 D D′′ D′

v t1

v*R A A′ A′′ A′′′

0 O O′′ O′

vY* B B′ B′′ B′′′

v*B C C′ C ′′ C ′′′

vt 2

−1 E E′
0 0 0 0
+00 000 0 - - 0 000 +00
- - - -
Ts Ts

43
 Fig. 5. In-Phase Sine Triangle PWM generation for 3-level Inverter

ur
V 9( + + − )
E

T4
ur ur
V 2 ( + + 0 ,00− ) D C V 8 ( +0 − )

T1 T2 T3
Vref
α
ur O ur ur B
V z ( + + + ,− − − ,000 ) A
V 1( +00 ,0 − − ) V 7( + − − )

Fig 6: In-Phase Sine-Triangle

44 PWM
In Fig. 7, the PO-SPWM is explained for one carrier time period ( Tc = 1 f c ). From the
figure the sequences of the inverter states applied for one half of the carrier period (sub-
cycle), are found to be,
( + − − ) → ( +0− ) → ( +00 ) → ( 000 ) . In the next sub-cycle it retraces the path it came
through and reaches the starting vector. The vectors applied for a total carrier time period
is as below:
ur ur ur ur ur ur ur
(V 7 → V 8 → V 1 → V z → V 1 → V 8 → V 7 ) . It does not obey the rule of Space-Vector
PWM for three-level inverter (as shown in Fig. 8). In this case, the applied vectors are not
the vertices of the triangle in which the tip of the reference vector falls.

+1 D′′
D D′

+1

vt1
45
v t1
v*R A A′ A′′ A′′′
Fig. 7: Phase Opposition Sine Triangle PWM generation for 3-level Inverter

46
 ur
V 9( + + − )
E

T4
ur ur
V 2 ( + + 0 ,00− ) D C V 8 ( +0 − )

T1 T2 T3
Vref
α
ur O ur ur B
V z ( + + + ,− − − ,000 ) A
V 1( +00 ,0 − − ) V 7( + − − )

Fig. 8: Phase-Opposition Sine-Triangle

PWM

Implementation of Sine-Triangle PWM

For implementation the IP-SPWM is chosen as this method conforms to the rules of
Space-vector PWM while the other method (PO-SPWM) disobeys the rules as explained
in the previous section. Instead of using two carrier signals (of amplitude ‘1pu’), it is also

47
possible to work with only one carrier with an amplitude of ‘0.5pu’.This is achieved by
subtracting ‘0.5pu’ from the positive carrier and the positive reference voltages and
adding ‘0.5pu’ to the negative carrier and the negative reference voltages (as in Fig. 9).
This method is reported in Reference 1.

+1

D D′′ D′
+0.5
B B′ B′′ B′′′
vY**
C C′ C ′′ C ′′′
v**
B

vt
0
O O′

v**
R
A A′ A′′ A′′′

−0.5
E E′

−1
0 0 0 0
+00 000 0 - - 0 000 +00
- - - -
Ts Ts
48
 Fig. 9: Steinke’s Method for SPWM Generation
Fig. 10 shows the basic structure of this method. The first main block is “Sign
identification and shift” block. In an initial step, sign of each phase reference voltage is
determined. The three sign signals are sent to the second main block “Phase output signal

control”. If for example, sign of vY* is positive, the phase output signal control sets the
switch pair ( SY 2 ,SY′ 2 ) to the constant state ( SY 2 = ON ,SY′ 2 = OFF ) and connects the
switch pair ( SY 1 ,SY′ 1 ) to the output TY of the pulse-width modulator.
If the sign is negative, the switch pair ( SY 1 ,SY′ 1 ) is gated to constant state
( SY 1 = OFF ,SY′ 1 = ON ) and connects the switch pair ( SY 2 ,SY′ 2 ) to the output TY of the
pulse-width modulator.

v**
R TR (SR1 / SR′ 1 )
v*R
(SR2 / SR′ 2 )
Sign vY** TY ( SY1 / SY′ 1 )
vY* Identification Normal PWM Phase output
& Generation signal control (SY2 / SY′ 2 )
shift
v**
B TB (SB1 / SB′ 1 )
v*B
(SB2 / SB′ 2 )

* * *
sign of vR ,vY49and vB
Fig. 10: Basic Signal Processing Structure for Steinke,s Method

So, we can summarize the method (Steinke,s Method) for Sine-Triangle PWM for 3-level
Inverter as below:

If v*x > 0 then, v** *

x = v x – 0.5 ---------(1.a)

If v*x < 0 then, v** *

x = v x + 0.5 ---------(1.b)

Where, x = R, Y, B

50
 Fig 11: Pole voltages (VRO) and Line voltage (VRY) of a Three-level Inverter
operating at fundamental frequency of 50Hz .PWM carrier frequency is 1 KHz.
Modulation Index=0.9.DC bus voltage=600 Volts

Preprocessing of the Phase reference voltages

If working with three-phase reference voltages instead of a voltage space vector, it is not
possible to utilize the whole output range with the phase reference voltage system being
free from a zero sequence voltage system. The whole range may be utilized, if the zero
sequence voltage system is added to the three-phase reference voltages that makes the
absolute values of the maximum and minimum phase reference voltage (after Steinke’s
transformation) equal to each other.

Unlike two-level inverter, the common-mode injection function,

51
−( vmax + vmin ) / 2 , does not yield always a centered space vector PWM for three-level
inverter. The injection functions can be derived for a three-level sine-triangle modulator
to achieve centered space vector modulation (CSVPWM) which are tabulated below (Ref
2).

Condition Common-Mode injection Function

vmid < 0 & ( vmax − vmin ) < 1 vmin

2
vmid > 0 & ( vmax − vmin ) < 1 vmax
2
vmid < 0 , ( vmax − vmin ) > 1 ( 1 − vmax )
−
2
& ( 1 − vmax ) > −vmid

vmid > 0 , ( vmax − vmin ) > 1 ( 1 + vmin )

2
& ( 1 + vmin ) > vmid

Others ( vmax + vmin )

−
2

Table-2: Common mode voltages for Three-Level Inverter CSVPWM

It is found in the above table that the common mode injection function for three level sine
triangle modulator is not unique, if we work with two carriers signals to generate SPWM
(ref. IP-SPWM).
But, instead of calculating common mode injection function with the original three-phase

reference voltages ( v*R ,vY* ,v*B ), if they are determined using the transformed (Steinke’s

Transformation) reference voltages ( v** ** **

R ,vY ,vB ) then the expression of the common-

mode voltage is found to be unique.

′ = Max( v**
vmax ** **
R ,vY ,vB ) -------------------------------------(2.a)

52
 ′ = Min( v**
vmin ** **
R ,vY ,vB ) --------------------------------------(2.b)

′ + vmin
( vmax ′ )
vCM = − ----------------------------------------(2.c)
2

R ,vY ,vB ) = ( vR ,vY ,vB ) + ( vCM ,vCM ,vCM ) ------(2.d)

( v*** *** *** ** ** **

The final Block-Diagram of the scheme for Sine-Triangle modulation for 3-level inverter
is as follows,

v*R v** v*** TR ( SR1 / SR′ 1 )

R R
Sign Commom-
( SR2 / SR′ 2 )
Identification ** mode
vY vY*** TY Phase output ( SY 1 / SY′ 1 )
vY* & Voltage Normal
shift Calculator PWM signal
(Equations v**
B (Equations v***
B Generation TB control ( SY 2 / SY′ 2 )
v*B
1.a 2.a, 2.b, 2.c
( SB1 / SB′ 1 )
& 1.b) & 2.d)
( SB2 / SB′ 2 )

* * *
sign of vR ,vY and vB

Fig. 12

Another alternative scheme has been reported in Ref. 3 for Sine-Triangle modulation for
Three-level Inverter. The scheme is described in the following sections.

53
Assuming that the reference for the three-level inverter is available in the form VREF ∠θ
the nearest pivot vector can be identified. The nearest pivot vector can also be identified
using 3-phase sinusoidal references based on the conditions shown in Table-3. The pivot
vectors can be expressed as three phase quantities ( vPNR ,vPNY ,vPNB ) as shown in the last

column of Table-3. Subtracting the nearest pivot vector from ( v*R ,vY* ,v*B ) as shown in
equation (3) gives the tentative three-phase reference for the conceptual two-level
inverter.

R ,vY ,vB ) = ( vR ,vY ,vB ) − ( vPNR ,vPNY ,vPNB ) ---------------------- (3)

( v** ** ** * * *

r
Conditions Nearest Pivot Vector ( VPN ) Pivot Vector as 3-phase
quantity ( vPNR ,vPNY ,vPNB )
r
v*R = max( v*R , vY* , v*B ) V1 2 1 1
( ,− ,− )
3 3 3
v*R > 0
r
v*B = max( v*R , vY* , v*B ) V2 1 1 2
( , ,− )
3 3 3
v*B < 0
r
vY* = max( v*R , vY* , v*B ) V3 1 2 1
( − , ,− )
3 3 3
vY* > 0
r
v*R = max( v*R , vY* , v*B ) V4 2 1 1
(− , , )
3 3 3
v*R < 0
r
v*B = max( v*R , vY* , v*B ) V5 1 1 2
( − ,− , )
3 3 3
v*B > 0
r
vY* = max( v*R , vY* , v*B ) V6 1 2 1
( ,− , )
3 3 3
vY* < 0

54
 Table-3

Calculation of Dwell times and switching instants

The maximum and minimum values of ( v** ** **

R ,vY ,vB ) are identified as shown in

equations (4.a) & (4.b)

MAX = max( vR ,vY ,vB ) -----------------------------------(4.a)

v** ** ** **

MIN = min( vR ,vY ,vB ) ------------------------------------(4.b)

v** ** ** **

The middle value is designated as v**

MID . We have,

MAX + vMID + vMIN = 0 --------------------------------------(5)

v** ** **

Let an offset voltage v** ** ** **

OFF be added as a zero-sequence component to ( vMAX ,vMID ,vMIN )

to ensure that the dwell time for the pivot vector is equally divided between the two pivot
states.

Then, the value of v**

OFF is found to be,

MAX + vMIN ) vMID

( v** ** **
v**
OFF =− = ---------------------------(6)
2 2

The offset voltage, added as a zero-sequence component to ( v** ** **

R ,vY ,vB ) , yields the

modified three-phase reference for the conceptual two-level inverter ( v*** *** ***
R ,vY ,vB ) as

55
 shown in (7). The switching instants for the three phase are available from

( v*** *** ***

R ,vY ,vB ) .

R ,vY ,vB ) = ( vR ,vY ,vB ) + ( vOFF ,vOFF ,vOFF ) ----------(7)

( v*** *** *** ** ** ** ** ** **

The two-level PWM from ( v*** *** ***

R ,vY ,vB ) can be translated into 3-level PWM waveform

using the final pivot vector as shown in Table-4.

Final 2-level S R1 S R′ 2 SY 1 SY′ 2 S B1 S B′ 2

Pivot PWM
Vector
r
V1 HIGH ON OFF OFF OFF ON OFF
LOW OFF OFF OFF ON OFF ON
r
V2 HIGH ON OFF ON OFF OFF OFF
LOW OFF OFF OFF OFF OFF ON
r
V3 HIGH OFF OFF ON OFF OFF OFF
LOW OFF ON OFF OFF OFF ON
r
V4 HIGH OFF OFF ON OFF OFF OFF
LOW OFF ON OFF OFF OFF OFF
r
V5 HIGH OFF OFF OFF OFF ON OFF
LOW OFF ON OFF ON OFF OFF
r
V6 HIGH ON OFF OFF OFF ON OFF
LOW OFF OFF OFF ON OFF OFF
S R′ 1 = S R1 S R 2 = S R′ 2 SY′ 1 = SY 1 SY 2 = SY′ 2 S B′ 1 = S B1 S B 2 = S B′ 2

Table-4
ur ur
V 11( − + − ) V 10 ( 0 + − ) ur
V 9( + + − )

56

ur ur ur
V 12 ( − + 0 ) V 3 ( 0 + 0 , −0 − ) ur V 8 ( +0− )
 Fig. 13: Space-Phasor Diagram for 3-level Inverter
Common mode voltage and Midpoint voltage unbalance of Three-Level Inverter and its
Mitigation

A three-level inverter feeding a three-phase motor is shown in Fig.1 (a). The space
vectors associated with such inverter are shown in Fig. 1(b).

57
 SR 1 SY 1 SB 1
+
- SR 2 SY 2 SB 2 IR
~
IMID IY
O R Y
~ N
O B IB
’
SR1 SY1
’ ’
S B1 ~
+
’ ’ ’
Motor
- SR2 SY2 S B2

Fig. 1(a) Three-level inverter feeding a three-phase motor

V 11 V 10 V9

V 12 V3
V2 V8

V REF
θ V1
V 13 V4 V7
Vz

V 14 V5 V6 V 18

V 15 V 16 V 17

58
 Fig. 1(b) Space vectors of three-level inverter
Common mode voltage:

Referring to Fig. 1 (a), the common mode voltage is the voltage between motor neutral
N and the mid-point of the dc bus O. The output pole voltages of the inverter may be
written as,

Fig. 1 (three-level inverter)

It is assumed that motor neutral is open. The instantaneous sum of the motor phase
voltages is zero. With this the expression for common mode voltage may be written as,
1
VNO = ( VAO +VBO +VCO ) (1)
3

The instantaneous sum of the pole voltages however is not zero. Hence there is a finite
potential difference between motor neutral and mid-point of the dc bus. This has a
significant effect on the bearing failures of the motor, which is explained later. The
common-mode voltage of the three-level inverter depends on the applied inverter states,
which are shown in Table-1.

Mid-point current:

Referring to Fig. 1 (a) the mid-point current is the current flowing out of the mid-point
‘O’ of the dc bus. Depending on the inverter states the mid-point current is the sum of the
line currents, which are connected to the mid-point. The mid-point current of the three-
level inverter depends on the applied inverter states, which are shown in Table-1.

59
 Table-1

Space-Vectors Inverter-States Common mode Mid-point current

voltage

r
V1 (+00) Vdc/6 -iR
r
V1 (0--) -Vdc/3 iR
r
V2 (++0) Vdc/3 iB
r
V2 (00-) -Vdc/6 -iB
r
V3 (0+0) Vdc/6 -iY
r
V3 (-0-) - Vdc/3 iY
r
V4 (0++) Vdc/6 iR
r
V4 (-00) - Vdc/6 -iR
r
V5 (00+) Vdc/6 -iB
r
V5 (--0) -Vdc/3 iB
r
V6 (+0+) Vdc/6 iY
r
V6 (0-0) - Vdc/6 - iY
r
V8 (+0-) 0 iY
r
V10 (0+-) 0 iR
r
V12 (-+0) 0 iB
r
V14 (-0+) 0 iY
r
V16 (0-+) 0 iR
r
V18 (+-0) 0 iB
r
V7 (+--) - Vdc/6 0
r
V9 (++-) Vdc/6 0

60
 r
V11 (-+-) - Vdc/6 0
r
V13 (-++) Vdc/6 0
r
V15 (--+) - Vdc/6 0
r
V17 (+-+) Vdc/6 0
r
Vz (000) 0 0
r
Vz (+++) Vdc/4 0
r
Vz (---) - Vdc/4 0

Mitigation of common mode voltage and mid-point current:

r r
Referring to the inverter states (Fig. 1(b)) the space vectors V1 - V6 are pivot vectors,
which correspond to the zero states of a two-level inverter. Each pivot vector consists of
two inverter states. The dwell time for each pivot vector can be divided into any fraction
between its two-inverter states. This does not affect the fundamental component of the
pole voltage of the inverter. This strategy can be used to mitigate the common-mode
voltage problem in case of three-phase motor (fed by a three-level inverter) and mid-
point current issues in case of a three-level inverter.
Mitigation of common mode voltage:

Referring to Fig. 2, let us consider a case when the reference vector VREF is encircled
by vectors V1,V7 and V8. The switching sequence |(+00)-(+0-)-(+--)-(0--)||(0--)-(+--)-(+0-
)-(+00). The common-mode voltage associated with each of the applied inverter states are
given in Table-2. The dwell time for the pivot vector V1 is T1. Let us consider the
inverter state (+00) is applied for duration (K.T1), while the inverter state (0--) is applied
for a duration of [(1-K)T1]. The common-mode voltage averaged over a switching sub-
cycle can be made zero by proper selection of K. The fraction K is calculated using
equations (2) and (3).

61
 V9

V2 V8 (T8)
(+ 0 -)

VREF

V0 V1 (T1) V7 (T7)
(+ 0 0) (+ - -)
(0 - -)

Fig. 2

Table-2

Switching state (+ 0 0) (+ 0 -) (+ - -) (0 - -)

Common mode voltage (pu) (1/6) (0) (-1/6) (-1/3)

Vdc = 1pu
Dwelling time K.T1 T8 T7 (1-K).T1

(1/6).K.T1 + 0.T8 + (-1/6).T7 + (1-K)T1.(-1/3) = 0 (2)

2 T6
K= + (3)
3 3T1

62
Mid point current:

Considering the same reference vector VREF as shown in Fig. 2 the mid-point current
associated with each of the applied inverter states are given in Table-3. Similar to the
common-mode voltage mitigation technique, the mid-point current averaged over a
switching sub-cycle can also be made zero by proper selection of K. The fraction K is
calculated using equations (4) and (5).

Table-3

Switching state (+ 0 0) (+ 0 -) (+ - -) (0 - -)

Mid point current (-IR) (IY) (0) (IR)

Dwelling time K.T1 T8 T7 (1-K).T1

-IR.K.T1 + IY.T8 + 0.T7 + (1-K)T1.IR = 0 (4)

⎛ I ⎞⎛ T ⎞
K = 0.5 + 0.5 ⎜ Y ⎟ ⎜ 8 ⎟ (5)
⎝ I R ⎠ ⎜⎝ T1 ⎟⎠

63
 Effect of Common mode voltages

Recently in the literature it is found that there are number of cases of motor bearing
failures by bearing currents particularly when the motor is fed from a PWM inverter. It is
investigated that the presence of common mode voltage (between motor neutral and the
mid-point of the dc bus) and the capacitive coupling between stator winding and the rotor
surface are responsible for driving a current through motor bearings. This is reported in
this section.

+
C1 _
A

O B
N
C
+
C2 _ Motor

Fig. 1

64
Referring to Fig. 1, the common mode voltage is the voltage between motor neutral N
and the mid-point of the dc bus O. The output pole voltages of dc-ac inverter may be
written as,

It is assumed that motor neutral is open. The instantaneous sum of the motor phase
voltages is zero. With this the expression for common mode voltage may be written as,
1
VNO = (VAO + VBO + VCO )
3
The instantaneous sum of the pole voltages however is not zero. Hence there is a finite
potential difference between motor neutral and mid-point of the dc bus. Let us see its
effect on the motor.

As per IEEE recommended grounding practices,

(1) The motor enclosure is grounded for personal and equipment safety.
(2) The mid point of the dc bus is normally grounded through some finite low
impedance to make the fault current flow to actuate the relays in case of motor
insulation failure. This is because the dc bus may be obtained through an isolation
transformer at the input side and a bridge rectifier.

Referring to Fig. 2, different capacitive couplings inside a motor that may cause bearing-
current may be realized as follows.
(1) Between stator winding conductors and rotor metal surface (through air gap and
winding insulation)
(2) Oil film, which acts as insulator

65
It should be noted that though the magnitude of the common mode voltage is less but due
to stepped nature the dv/dt is high. This high dv/dt causes a significant amount of
capacitive current to flow through these stray capacitances. The path for such currents is
shown in Fig. 2. The current enters in the rotor surface from stator winding and flows
thorough rotor shaft and finally returns to the mid-point of the dc bus through bearing oil
film and motor enclosure. It should be noted that the oil film is not an ideal capacitor.
When the rotor shaft rotates the oil film capacitance between the balls and bearing races
frequently discharges. The discharge current cause pitting on the race and also dries up
the oil film. Both of these cause increased bearing friction and finally bearing failure.

Stator winding

Ball

Oil flim

Rotor
Shaft

Stator winding

Fig. 2

66