Ain Shams University

Faculty of Engineering

Arithmetic Logic Unit

Documentation

Computer Organization 3rd Year Mechatronics Students,

Computer & Systems Department,

Faculty of Engineering,

Ain Shams University, Egypt.

Under supervision of :

Dr. Mona Fahmy Ismail.

Prepared by:

Ahmed Abdelshakour Allam

Ahmed Abdelaziz Mohamed

Sherif Mostafa Eltoukhi

Mahmoud Soliman Aglan

Mahmoud Yehia Mohamed

Yehia Zakaria Mohamed

May16th 2011
Table Of Contents

list Of Figures (Page 3)

list Of Tables (Page 4)

Acknowledgment (Page 5)

Introduction (Page 6)

Project Objective (Page 7)

ALU Circuit Design (Page 8)

ALU - V.1.0 (Page 8)
ALU - V.1.1 (Page 12)
ALU - V.2.0 (Page 13)
ALU - V.2.1 (Page 14)
ALU - V.3.0 (Page 16)
ALU - V.3.1 (Page 19)

ALU Circuit Simulation (Page 23)

ALU Circuit Implementation (Page 25)

Hardware components (IC) search & selection. (Page 26)
Hardware components data sheets analyzation. (Page 28)
Board layout designing. (Page 32)
Hardware connections documenting & recording. (Page 35)
ALU circuit testing & debugging. (Page 38)

Summary (Page 40)

Contact Information (Page 42)

2
List Of Figures

List Of Figures

Figure (1) ALU - V.1.0 Logic Operations Part Design. (Page 6)

Figure (2) ALU - V.1.0 Arithmetic Operations Part Design. (Page 8)
Figure (3) ALU - V.1.0 Design. (Page 9)
Figure (4) ALU - V.1.1 Design. (Page 10)
Figure (5) ALU - V.2.0 Design. (Page 11)
Figure (6) ALU - V.2.1 Design. (Page 12)
Figure (7) ALU - V.3.0 Design. (Page 16)
Figure (8) ALU - V.3.1 Design. (Page 19)
Figure (9) ALU - 4 bit Design Scheme. (Page 20)
Figure (10) ALU - Simulation Circuit on ISIS Proteus Software. (Page 22)
Figure (11) 4 BIT ADDER IC (Page 26)
Figure (12) XOR IC (Page 26)
Figure (13) AND IC (Page 27)
Figure (14) OR IC (Page 27)
Figure (15) 4 BIT MULTIPLEXER IC (Page 28)
Figure (16) 2 BIT MULTIPLEXER IC (Page 28)
Figure (17) NOT IC (Page 29)
Figure (18) Board Layout Schematic Design. (Page 30)
Figure (19) Board Layout Real View. (Page 31)
Figure (20) Final Board Look. (Page 37)

3
List Of Tables

List Of Tables

Table (1) ALU Requirements. (Page 5)

Table (2) Relations Between The Arithmetic Part Required Functions. (Page 7)
Table (3) ALU - V.3.0 Truth Table. (Page 14)
Table (4) ALU - V.3.0 Invert A K map representation. (Page 15)
Table (5) ALU - V.3.0 Invert B K map representation. (Page 15)
Table (6) ALU - V.3.0 CTRL Line K map representation. (Page 15)
Table (7) ALU - V.3.1 Truth Table. (Page 17)
Table (8) ALU - V.3.1 Invert A K map representation. (Page 18)
Table (9) ALU - V.3.1 Invert B K map representation. (Page 18)
Table (10) ALU - V.3.1 CTRL Line K map representation. (Page 18)
Table (11) ALU - V.3.1 Used Hardware Components List. (Page 24)
Table (12) ALU - V.3.1 Used Hardware Components Modified List. (Page 25)
Table (13) ALU - V.3.1 Used Hardware Components ICs Numbers List. (Page 25)
Table (14) IC Numbers on Board Layout Design. (Page 32)
Table (15) Hardware Connections Documenting & Recording List. (Page 33)

4
Acknowledgment

Special Thanks For

Dr. Mona Ismail

For all her efforts during Computer Organization & Digital Logic Design courses

For 3rd Year Mechatronics Department at Ain Shams university.

Leading Us to create this ALU between your hands.

5
Introduction

Arithmetic Logic Unit

An arithmetic logic unit (ALU) is a digital circuit that performs arithmetic and logical operations.
The ALU is a fundamental building block of the central processing unit (CPU) of a computer, and
even the simplest microprocessors contain one for purposes such as maintaining timers.

Most ALUs can perform the following operations:

• Bitwise logic operations (AND, NOT, OR, XOR).

• Integer arithmetic operations (addition, subtraction, and sometimes multiplication

and division, though this is more expensive)
• Bit-shifting operations (shifting or rotating a word by a specified number of bits to the left or
right, with or without sign extension). Shifts can be seen as multiplications and divisions by a
power of two.

The processors found inside modern CPUs and graphics processing units (GPUs) accommodate
very powerful and very complex ALUs; a single component may contain a number of ALUs.

Mathematician John von Neumann proposed the ALU concept in 1945, when he wrote a report on
the foundations for a new computer called the EDVAC.

Research into ALUs remains an important part of computer science, falling under Arithmetic and
logic structures in the ACM Computing Classification System.

6
Project Objective

Project Objective
Design a 4-bit ALU with 3 selection Lines: Mode M, Select S1 and S0.
The mode input (M) selects between logic (M = 0) and arithmetic (M =1) operations.
C is a carry bit, which is used in operations requiring increment.
The used numbers are unsigned.
The output of the ALU must be 4-bit number called F.
The functions performed by the ALU are given in the below (Table (1)):

M=0
S1 S0 C Function Operation (Bit wise)

0 0 X Ai Bi AND

0 1 X Ai +Bi OR

1 0 X Ai ⊕Bi XOR

1 1 X (Ai ⊕Bi)' XNOR

M=1

S1 S0 C Function Operation (Bit wise)

0 0 0 A Transfer A

0 0 1 A +1 Increment A by 1

0 1 0 A+B Add A & B

0 1 1 A+B+1 Increment the sum of A & B by 1

1 0 0 A + B’ A plus one’s complement of B

1 0 1 A-B Subtract B from A

1 1 0 A’ + B B plus one’s complement of A

1 1 1 B-A Subtract A from B

Table (1).

7
ALU Circuit Design

ALU Circuit Design

The main target from this project was to make a simple designed ALU circuit with a few hardware
components as much as possible, in order to reduce the cost to the minimum & avoid complex
design that would be difficult to implement.

ALU - V.1.0
In the beginning, Analyzation was made to the main required functions from the ALU to perform
and with the help of the given table (See Page 7), It was noticed that there are two types of
operation which are:
1- Logic operations (AND, OR ,XOR & XNOR).
2- Arithmetic operations (A, A+1, A+B, ................).
Then it was decided to start working on each type of operations alone on one bit only, so the
beginning was with the logic operations,making the following circuit (Figure (1)).

Figure (1).
8
From the circuit shown in (Figure (1)), it was noticed that the following hardware components are
used:

1. Two 2x1 Multiplexers to select between A,B & their invert Values (to use them later in
the Arithmetic operations or incase we needed them in the logic operations) (using two
NOT gates to get the invert values of A & B).
2. One AND Gate to perform the AND operation.
3. One OR Gate to perform the OR operation.
4. One XOR Gate to perform the XOR operation.
5. One NOT Gate to perform the XNOR operation (by inverting the XOR Gate output).
6. One 4x1 Multiplexer to select the required output of the required operation from the
output of all the performed logic operation (using S1 & S0 as the multiplexer control
lines).

Then it was decided to start working on the arithmetic operations, it was noticed that there are
some relations between the required functions listed on the following (Table (2)):

Main Function Pseudo Function With C =

A A+0 0

A +1 A+0 1

A+B A+B 0

A+B+1 A+B 1

A + B’ A + B’ 0

A-B A + B’ 1

A’ + B A’ + B 0

B-A A’ + B 1

Table (2).

This lead to making of the following circuit (Figure (2)).

9
 Figure (2).

From the circuit shown in (Figure (2)), it was noticed that the following hardware components are
used:

1. Three 2x1 Multiplexers, Two of them are used to select between A,B & their invert
Values (using two NOT gates to get the invert values of A & B); While the third one is
used to select the required output of the required operation from the output of the two
adders.
2. Two One bit Adders, The first of them to perform the A + 0 functions (when both cases
of c = 0 & 1), While the second to perform all the remaining functions.

After that an integration between the two parts of the ALU (Figure (1) & Figure (2)) was maed,
Using only Two extra 2x1 multiplexers as the Mode selections for the ALU, making the following
circuit of (Figure (3)).

10
 Figure (3).

The problems of that design were that:

1. It was away from our target making a compact design with a few hardware compo-
nents.
2. This design was not easy to implement.
3. Some hardware components were not available in the market.
4. Large number of Control lines, made it difficult to get the required function and so the
required output.
So it was decided to work on this design again trying to avoid all the problems, faced in the ALU -
V.1.0, Introducing ALU - V.1.1.

11
ALU - V.1.1
In this version of ALU a new trial was made to avoid the problems, faced on the previous design
by a simple idea which is to put one mode selection multiplexer at the end of the ALU circuit, to
select between the output of the logic operations part & the arithmetic operations part, instead of
using two multiplexers at the beginning of the ALU circuit, introducing the following circuit of ALU
v1.1 (Figure (4)).

Figure (4).

In this design a modification was made to the previous design through:

1. Reducing the hardware components number.
2. Simplifying the design a little bit.
3. Reducing the number of control lines used on the ALU.
But it was thought that more reduction is need on the hardware components number in order to
achieve the compact design, and this lead to ALU V.2.0.

12
ALU - V.2.0
In this version of ALU a new trial was made to reduce the number of hardware components in
order to reach the most possible compact design (Figure (5)).

Figure (5).

In this version it is noticed that a modification was made to the previous design through:
1. Removing one of the two used adders & instead we use a 2x1 multiplexer to select
between wether adding A and B or A and Zero (Since the pseudo functions (See Page
9) could be simplified to A + 0 & A or A’ + B or B’ ).
2. Removing the 2x1 multiplexer used to select between the output of the two adders as a
result of the previous point.
But this design problem was that it increased the number of control lines used in the ALU, an
other trial was made to modify this problem making ALU - V.2.1.

13
ALU - V.2.1
In this version of ALU nothing was changed whether in design or in hardware number, but the
mentality about the control lines & use them, So a rearrange to control lines was made in order to
use the same control line more than one time if possible (Figure (6)).

Figure (6).

In this version it is noticed that S1 & S0 (The two main selection lines) were used twice.
1. In the logic operation part of the circuit as a selection lines to the 4x1 multiplexer.
2. In the arithmetic operation part of the circuit as a selections lines to the two 2x1
multiplexers used to get A & B inverts.

14
Since that if the logic part of the ALU (i.e mode 0) is desired to be used, S1 & S0 will be used in
order to get the required result of the required logic operation, & the arithmetic part output (i.e
mode 1) will no longer be important (due to using S1 & S0 randomly from the arithmetic part view)
& vise versa.

But the problem of large number of control lines (Five control lines) is still present since they lead
to more time adjusting them to perform the required task, which is unreasonable to spend the
same time for entering your data (inputs) to just adjust the operation required to be performed.
And so this lead to ALU V.3.0.

15
ALU - V.3.0
In this version of ALU, the main focus was on reducing the number of control lines (even if it was
necessary to increase the number of hardware components), in order to increase the ALU
performance through reducing the function execution time.
The main focus was on the arithmetic operations part of the circuit since it had four control lines
(S0, S1, Adding Control Line & Cin), compared to two control lines only on the logic operations
part (S0 & S1).
It was decided to make new truth table for the for the arithmetic part between the required
number of control lines & the four control lines from the previous design like the following
(Table (3)).

Required Control Lines M=1 ALU - V.2.1 Contol Lines

S1 S0 C Function Invert A Invert B CTRL Line Cin

0 0 0 A 0 0 0 0

0 0 1 A +1 0 0 0 1

0 1 0 A+B 0 0 1 0

0 1 1 A+B+1 0 0 1 1

1 0 0 A + B’ 0 1 1 0

1 0 1 A-B 0 1 1 1

1 1 0 A’ + B 1 0 1 0

1 1 1 B-A 1 0 1 1

Table (3).

Then a K map representation was made in order to find out some relations between ALU - V.2.1
Control Lines (Invert A(S0),Invert B(S1) & CTRL Line), & the required control lines (S1 & S0) in the
following (Table (4),Table (5) &Table (6)) .

16
For Invert A.

S0\S1 0 1
0 0 0

1 0 1

Table (4).
Invert A = S0 . S1

For Invert B.

S0\S1 0 1
0 0 1

1 0 0

Table (5).
Invert B = S0’ . S1

For CTRL Line.

S0\S1 0 1
0 0 1

1 1 1

Table (6).
CTRL Line = S0 + S1

Using the formulas got from the K maps:

1. Invert A = S0 . S1
2. Invert B = S0’ . S1
3. CTRL Line = S0 + S1
The following design (Figure (7)) could be made (using simple logic gates).

17
 Figure (7).

But this design made another problem which was that it had increased the number of hardware
components, & so we tried to reduce them in our final design ALU -V3.1.

18
ALU - V.3.1
In this version of ALU, The main focus was on reducing the number of hardware components in
order to reduce the cost to the minimum.
The same approach was followed as last design ALU V.3.0 with only one change in the truth table
that lead to components reduction which was that Invert B value when S1 & S0 = zero, was
assumed to be Don’t Care since that its values are not important as it is supposed to add A and
Zero (using CTRL Line), (Table (7)).

Required Control Lines M=1 ALU - V.2.1 Contol Lines

S1 S0 C Function Invert A Invert B CTRL Line Cin

0 0 0 A 0 X 0 0

0 0 1 A +1 0 X 0 1

0 1 0 A+B 0 0 1 0

0 1 1 A+B+1 0 0 1 1

1 0 0 A + B’ 0 1 1 0

1 0 1 A-B 0 1 1 1

1 1 0 A’ + B 1 0 1 0

1 1 1 B-A 1 0 1 1

Table (7).

Then a K map representation was made in order to find out the new relations between ALU - V.2.1
Control Lines (Invert A(S0),Invert B(S1) & CTRL Line), & the required control lines (S1 & S0) in the
following (Table (8),Table (9) &Table (10)) .

19
For Invert A.

S0\S1 0 1
0 0 0

1 0 1

Table (8).
Invert A = S0 . S1

For Invert B.

S0\S1 0 1
0 X 1

1 0 0

Table (9).
Invert B = S0’

For CTRL Line.

S0\S1 0 1
0 0 1

1 1 1

Table (10).
CTRL Line = S0 + S1

Using the formulas got from the K maps:

1. Invert A = S0 . S1
2. Invert B = S0
3. CTRL Line = S0 + S1
The following design (Figure (8)) could be made (using simple logic gates).

20
Figure (8).

21
Finally the output signal pin F is to be connected to a Light Emitter Diode (LED) in order to identify
the operation output whether one (LED is ON) or zero (LED is OFF) .

This was the most simplified design version of one bit ALU, achieving by it the main targets which
were:

1. Simple design.
2. Easy circuit to implement.
3. Small number of hardware components.
4. Small number of control lines.
5. High performance.
6. Low cost.
7. Low power consumption.
8. Easy to maintain.
9. Safe to the environment.

It should be mentioned that this one bit

ALU should be repeated four times
consequently to get the four bit ALU at
last (Figure (9)).

Figure (9).

22
ALU Circuit Simulation

ALU Circuit Simulation

After settled on the final design, a trial to simulate the design on computers was made in order to
know whether if the final design is working correctly or not.

Simulo software (http://simulo.codeplex.com/) was used to simulate the logic part of the circuit (bit
wise), since this program is very simple & contains a few hardware components in the program
library (usually used for logic circuits simulation).

Also ISIS Proteus software (http://www.labcenter.com/products/pcb_overview.cfm) was used to

simulate the arithmetic part of the circuit (bit wise), since this program is more advanced &
contain more hard components in the program library (which couldn’t be found in Simulo software
& it was hard to implement these missing components using the available components in the
software library).

Later after selecting the hardware components (See Page 26), ISIS Proteus was used again to
simulate the complete circuit of the ALU (4 bits), (Figure (10)).

23
Figure (10).

24
ALU Circuit Implementation

ALU Circuit Implementation

The implementation is considered the phase at which all the paper work (research, designs &
calculations) & all the visual work (simulation & layout drawing) come into a real object could be
hold in your hands.

The implementation phase was divided into sub-phases in order to:

1. Work more faster.
2. Work more accurate.
3. Handle the tasks between the team members more effectively.

These sub-phases are:

1. Hardware components (IC) search & selection.
2. Hardware components data sheets analyzation.
3. Board layout designing.
4. Hardware connections documenting & recording.
5. ALU circuit testing & debugging (incase of failures & errors).

25
1.Hardware Components Search & Selection
This phase was the start to search for the hardware components (IC) that could be used to
implement the ALU.
These components (used on the ALU - V.3.1 Design) are listed on the following (Table (11)):

No. Hardware Component Type Number Off Comments

1 1 BIT ADDER 4 1/bit

2 XOR 4 1/bit

3 AND 8 2/bit

4 OR 8 2/bit

5 4 BIT Multiplexer 4 1/bit

6 2 BIT Multiplexer 16 4/bit

7 NOT 12 3/bit

8 4 I/O Switch 2 For data entry

9 1 I/O Switch 2 Control Lines

10 2 I/O Switch 1 Control Lines

Table (11).

Then an internet search & a market search started in parallel in order to find the hardware
components ICs numbers, data sheets & to know which of them is available in the market (Egypt
in our case).
Google search engine was used to search for ICs numbers & data sheets, also a search was
made among the egyptian electronics stores such as Ram Electronics
(http://ram-e-shop.com/test11/) to look for the available components & ICs at the market.

Some components were not found on the market such as the 1 BIT ADDER (that resulted in
making an overflow flag detector a very difficult process, since it will be needed to implement the
Adders manually using logic gates), while other components like (Logic Gates) were found to be
more than one (of the same type) in the single IC.

26
This lead to modification of pervious table into the following (Table (12)):

No. Hardware Component Type Number Off Comments

1 4 BIT FULL ADDER 1 This adder will be used for the whole
ALU (4 bit wise)

2 XOR (x 4/IC) 1 4 Gates/IC

3 AND (x 4/IC) 2 4 Gates/IC

4 OR (x 4/IC) 2 4 Gates/IC

5 4 BIT Multiplexer (x 2/IC) 2 1/2 bit

6 2 BIT Multiplexer (x 3/IC) 6 4/bit

7 NOT (x 6/IC) 2 6 Gates/IC

8 4 I/O Switch 2 For data entry

9 1 I/O Switch 2 Control Lines

10 2 I/O Switch 1 Control Lines

Table (12).

Finally the ICs numbers were determined in the following (Table (13)):

No. Hardware IC Model Number Number Comments

Component Type Off
1 4 BIT FULL ADDER 74S283 1 This adder will be used for
the whole ALU (4 bit wise)

2 XOR (x 4/IC) 74HC86 1 4 Gates/IC

3 AND (x 4/IC) 74LS08 2 4 Gates/IC

4 OR (x 4/IC) 74HC38 2 4 Gates/IC

5 4 BIT Multiplexer (x 2/ (HCC/HCF)4052 2 1/2 bit

IC)

6 2 BIT Multiplexer (x 3/ (HCC/HCF)4053 6 4/bit

IC)

7 NOT (x 6/IC) 74HC04 2 6 Gates/IC

Table (13)

27
2.Hardware Components Data Sheets Analyzation
In this phase, A simplification was made to the data sheets of the selected components in order to
making the ICs installation on the board easy and fast as much as possible.

For each IC as simple figure was drawn containing the important data of the IC (Figure (11),
Figure (12), Figure (13), Figure (14), Figure (15), Figure (16) & Figure (17)).

Figure (11).

Figure (12).

28
Figure (13).

Figure (14).

29
Figure (15).

Figure (16).

30
 Figure (17).

All the previous figures lead to the board layout designing in the next phase (See Page 32) as
they help in estimating where the inputs & outputs are & how should the ICs should be placed in a
very small area with the shortest possible connection paths.

31
3.Board Layout Designing
In this phase, Board layout design was made (after knowing the number of ICs used & all the data
related to these ICs), aiming to reduce the circuit physical area ,aiming to reduce the number of
connections & common nodes & aiming to shorten the connection paths, like in the following
(Figure (18) & Figure (19)).

Figure (18).

32
 Figure (19).

In this board layout design, it is noticed that every IC was given a unique number (Table (14)) to
ease the connections documentation & recording and so to facilitate the traceability of errors
when testing debugging.

Also it is noticed that white space on the board layout design are to be used for entry switches &
output detectors (LEDs)(Later it was needed to move the switches & the output detectors (LEDs)
out from this board & put them in a new one to make data entry & the control process more easier
for the user (See Page 39, Figure (20))).

33
Also it is noticed that the suggested number of ICs required for the implementation of the ALU
were 16 ICs however to facilitate the connection of the wires and to ensure that every 1-bit ALU
was clearly distinguished from the other bits and to make the connections as simple as possible 3
extra ICs were used (Two 4 BIT Multiplexer ICs and One 2 BIT Multiplexer IC); The extra ICs
made sure that every 1-bit ALU clearly distinguished from the other 4 bits and facilitated the
connections of the wires facilitating the testing and debugging process.

IC Number on Layout IC Model Number IC Type

1 (HCC/HCF)4053 2 BIT Multiplexer (x 3/IC)

2 (HCC/HCF)4052 4 BIT Multiplexer (x 2/IC)

3 (HCC/HCF)4053 2 BIT Multiplexer (x 3/IC)

4 (HCC/HCF)4052 4 BIT Multiplexer (x 2/IC)

5 (HCC/HCF)4053 2 BIT Multiplexer (x 3/IC)

6 74LS08 AND (x 4/IC)

7 74HC38 OR (x 4/IC)

8 74HC04 NOT (x 6/IC)

9 74S283 4 BIT FULL ADDER

10 74HC86 XOR (x 4/IC)

11 74HC04 NOT (x 6/IC)

12 74HC38 OR (x 4/IC)

13 74LS08 AND (x 4/IC)

14 (HCC/HCF)4053 2 BIT Multiplexer (x 3/IC)

15 (HCC/HCF)4052 4 BIT Multiplexer (x 2/IC)

16 (HCC/HCF)4053 2 BIT Multiplexer (x 3/IC)

17 (HCC/HCF)4053 2 BIT Multiplexer (x 3/IC)

18 (HCC/HCF)4052 4 BIT Multiplexer (x 2/IC)

19 (HCC/HCF)4053 2 BIT Multiplexer (x 3/IC)

Table (14).

34
4.Hardware Connection Documenting & Recording
In this phase, A table (Table (15)) was made illustrating the nodes numbers between wires con-
nections all over the board (using the previous data sheets analysis (See Page 28) & board layout
design (See Page 32)), however this table helped a lot later in debugging & testing processes as
it facilitated the traceability of each connection path.

From To
# IC/# Leg # IC/# Leg
A/4 13/13
13/13 12/13
B/4 13/12
13/12 12/12
12/13 10/13
12/12 10/12
10/14 11/13
13/11 18/12
12/11 18/14
10/11 18/15
11/12 18/11
13/13 19/12
13/13 11/1
11/8 19/13
12/12 19/1
12/12 11/11
11/10 19/2
19/15 19/3
19/4 9/12
19/14 9/11
9/10 17/13
18/13 17/2
14/11 19/11
14/9 19/9
S1 19/10
A/3 6/10
B/3 6/9
6/8 15/1
6/10 7/10
7/9 6/9
15/5 7/8
16/1 6/8

35
 From To
# IC/# Leg # IC/# Leg
15/2 10/8
7/9 6/8
7/10 1/8
8/13 10/9
6/10 10/10
7/10 15/4
8/8 14/12
8/13 10/8
14/14 9/14
6/8 14/1
8/11 7/9
14/2 8/10
15/8 15/6
15/8 15/7
14/15 14/3
14/8 14/5
6/6 14/11
7/6 14/9
S/2 14/10
14/4 9/15
14/10 15/9
15/10 S1
15/3 16/12
9/13 16/3
A/A1 1/12
A/A2 1/8
1/12 8/1
8/12 1/13
1/12 6/1
6/1 7/1
10/4 A/2
B/1 10/5
B/2 7/2
7/2 6/2
6/2 1/1
7/2 8/3
1/2 8/4
1/14 9/3
1/15 1/3
1/8 1/7
1/7 1/6

36
 From To
# IC/# Leg # IC/# Leg
1/6 1/5
1/4 9/2
6/6 2/11
2/12 6/3
7/3 2/14
10/6 8/5
8/6 2/10
3/2 2/13
3/1 9/1
3/15 Out
6/6 1/11
6/4 7/5
6/3 7/4
1/9 7/6
6/4 1/10
2/10 7/4
7/5 2/9
Table(15).

37
5.ALU Circuit Testing & Debugging
After the implementation phase the circuit was installed on the board and wired up; Although the
circuit was carefully implemented, this didn’t prevent connection problems to arise which required
the revision of the connections to check whether the wires were connected to their designated
locations on the board or not.

Some connections were found to be loose and fixed others were connected to wrong nodes and
corrected others were missing and were installed.

The next phase was to check whether the ALU performed all of its functions correctly.

As expected there were some errors in the output of the ALU some of them were because of faulty
ICs but most of them were because of problems related to the ICs fitting on the board.

After making sure that the ALU was performing its main functionality correctly, it was then subject
to a thorough test to make sure that every possible input to the ALU produced the desired output.

After the testing phase some accessory parts were installed (Proper Dip switches) (Figure (20))
and the circuit was subjected to a final rough test to make sure that the recently installed parts
didn’t affect any of the ALU functionalities and were properly working.

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Figure (20).

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Summary

An arithmetic logic unit (ALU) is a digital circuit that performs arithmetic and logical operations.
The ALU is a fundamental building block of the central processing unit (CPU) of a computer, and
even the simplest microprocessors contain one for purposes such as maintaining timers.

Project Objective was to design a 4-bit ALU with 3 selection Lines: Mode M, Select S1 and S0.
The mode input (M) selects between logic (M = 0) and arithmetic (M =1) operations. C is a carry
bit, which is used in operations requiring increment. The output of the ALU must be 4-bit number
called F

The main target from this project was to make a simple designed ALU circuit with a few hardware
components as much as possible, in order to reduce the cost to the minimum & avoid complex
design that would be difficult to implement.

After many trials as shown in this documentation, an optimum design was achieved having
advantages over regular designs such as:

1. Simple design.
2. Easy circuit to implement.
3. Small number of hardware components.
4. Small number of control lines.
5. High performance.
6. Low cost.
7. Low power consumption.
8. Easy to maintain.
9. Safe to the environment.

Although this design has many advantages, still it has a setback that some hardware components
were not available in the market. These setback resulted in not implementing an over flow flag
detection.

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After settled on the final design, a trial to simulate the design on computers was made in order to
know whether if the final design is working correctly or not. Simulo software was used to simulate
the logic part of the circuit (bitwise). Also ISIS Proteus software was used to simulate the arithme-
tic part of the circuit (bit wise) and the complete circuit of the ALU (4 bits).

The implementation is considered the phase at which all the paper work (research, designs &
calculations) & all the visual work (simulation & layout drawing) come into a real object could be
hold in your hands. This Phase was divided into sub-phases in order to increase work efficiency,
these sub phases are:
1. Hardware components (IC) search & selection.
2. Hardware components data sheets analyzing.
3. Board layout designing.
4. Hardware connections documenting & recording.
5. ALU circuit testing & debugging (in case of failures & errors).

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Contact Information

For more information

Please Contact Us at:

Ahmed Abdelshakour Allam

ahmabdabd@hotmail.com

Ahmed Abdelaziz Mohamed

ahmedoz_89@hotmail.com

Sherif Mostafa Eltoukhi

sherif_el_toukhi@live.com

Mahmoud Soliman Aglan

mahmoud.soliman@aybasu.com

Mahmoud Yehia Mohamed

mahmooodgaaad@yahoo.com

Yehia Zakaria Mohamed

yahia.zakaria@aybasu.com

Thank you !

Project’s Team

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