CONFIDENTIAL EE/OCT 2003/KEE322

UNIVERSITI TEKNOLOGI MARA

FINAL EXAMINATION

COURSE DIGITAL ELECTRONICS

COURSE CODE KEE322
DATE 17 OCTOBER 2003
TIME 3 HOURS (8.30 a.m -11.30 a.m)

FACULTY Electrical Engineering

SEMESTER June 2003 - November 2003
PROGRAMME/CODE Diploma in Electrical Engineering (Electronics) / EE111

INSTRUCTIONS TO CANDIDATES

1. Answer FIVE (5) questions only.

2. Each question is allocated TWENTY (20) marks.

3. Do not bring any material into the examination room unless permission is given by the
invigilator.

4. Please check to make sure that this examination pack consists of:
i) the Question Paper
ii) an Answer Booklet - provided by the Faculty
iii) a seven-page Appendix

DO NOT TURN THIS PAGE UNTIL YOU ARE TOLD TO DO SO

This examination paper consists of 8 printed pages
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CONFIDENTIAL EE/OCT 2003/KEE322

QUESTION 1

a) For each statement, indicate the term being described.

(i) Arrangement of output transistors in a standard TTL circuit

(ii) Another term that describes pull-down transistor
(iii) A quantitative measure of noise immunity
(iv) When a LOW output receives current from the input of the circuit it is driving
(v) Number of inputs that an output can safely drive
(vi) A common measure used to compare overall performance of different 1C
families
(6 marks)

b) For a 74AS20 chip (data sheet in APPENDIX 1), determine the maximum case of the
following:

(i) the average propagation delay

(ii) the average power dissipation per gate
(iii) the speed-power product
(6 marks)

c) For the logic circuit shown in Figure 1c, calculate the loading current that the
74HOO gate has to sink and source. Stpte problem/problems encountered, if any,
during the current sinking and sourcing through the gate. Refer to the relevant data
sheets in the appendix.
(5 marks)

Figure 1c

d) To prevent unused inputs from floating, the unused input are tied-together. Describe
how the tied-together inputs are considered as a single load and separate loads.

(3 marks)

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QUESTION 2

a) Use TABLE 2 in APPENDIX 6 to find the fan-out for interfacing the first logic
family to drive the second.

(i) 74AS to 74ALS

(ii) 74F to 74
(iii) 74AHC to 74AS
(iv) 74HC to 74ALS
(8 marks)

b) A Totem-pole output structure can cause current spikes to occur when switching
between LOW to HIGH. Why do current spikes occur?
(2 marks)

c) Figure 2c shows a logic family based on bipolar technology.

Name the gate structure.

State one advantage and one disadvantage of the gate structure.
State one reason why emitter followers are required at the output stage of the
gate structure.
(iv) Perform the necessary analysis to determine the potentials at VCi, VC2, Vout1
and Vout2 for LOW input A and HIGH input B.
(10 marks)

300 Q R 2 § 300
V
VC1 C2

'OUt1 0__V^ OUt2

Input A K^lnput B
R R
V
E 1
3mA <;
<
•< I ikQ
ir

o
VEE = -5.2 V

Figure 2c

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CONFIDENTIAL EE/OCT 2003/KEE322

QUESTION 3
cc

output

B
1 kQ
Figure 3a

a) For the circuit shown in Figure 3a, assume for all transistors VCEsat = 0.2 V, VBE = 0.6
V and for diode D during forward bias has Vdiode = 0.7 V. Both inputs A and B are at
logical "0" i.e. 0.2 V.

Name the logic gate structure shown in Figure 3a.

Copy the circuit into the answer booklet. Show the path of the current flowing
in the circuit and mark "ON" or "OFF" at each transistor to show their states.
(iii) Determine the potential at the output, Vx, with respect to the ground.
(iv) Calculate the total current drawn by the gate from the dc power supply i.e.
Vcc-
(v) Calculate the total power dissipated by the gate.
(10 marks)

b) List two advantages that CMOS has over TTL and two advantages that TTL
has over CMOS.
(4 marks)

c) Two different logic circuits have the characteristics shown in Table 3c.

(i) Which circuit has the best LOW-state dc noise immunity?

(ii) Which circuit has the best HIGH-state dc noise margin?
(iii) Which circuit can operate at higher frequencies?
(iv) Which circuit draws the most supply current?
(6 marks)
Table 3c
Parameter Circuit X Circuit Y
Vsupply (V) 5 6
VlH(min) (V) 1.8 1.6
VlL(max) (V) 0.7 0.9
VoH(min) (V) 2.5 2.2
VoL(max) (V) 0.3 0.4
bLH (ns) 18 10
tpHt (ns) 14 8
PD (mW) 10 16
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QUESTION 4

a) Referring to TABLE 1 and TABLE 2 in APPENDIX 6, state and explain the

problems encountered, if any, during the HIGH-state and LOW-state interfacing
when:

(i) the CMOS 4000B series drive the TTL 74ALS series
(ii) the TTL 74AS series drive the CMOS 74AHC series
(iii) the CMOS 74HCT series drive the TTL 74 series
(iv) the TTL 74LS series drive the CMOS 74ACT series
For each problem encountered, suggest a solution to make the interfacing possible.

(10 marks)

b) Figure 4b shows a resistive model of a CMOS inverter driving resistive loads.

Table 4b gives the resistance values of the MOSFET under the specified conditions.

What is the disadvantage of a CMOS inverter driving resistive loads

compared to the one without resistive loads?
If the circuit is fed with an ideal input voltage (0 V for LOW and 5 V for HIGH),
calculate the LOW-state and HIGH-state output voltages i.e. V0u and VQH-
Also, calculate the associated sinking and sourcing current.
If the circuit is fed with a non-ideal input voltage (1.5 V for LOW and 3.5 V for
HIGH), calculate the LOW-state and HIGH-state output voltages i.e. VOL and
VOH.
(10 marks)
VDD = +5 V

1
PMOS 2kQ

Vin

NMOS V0 3kQ

Figure 4b

Table 4b

NMOS PMOS
RWOFF) RWON) Rp(OFF) Rp(ON)
Ideal
inputs 1.2MD 120 Q 1.2MQ 240 D

Non-ideal
Inputs 3kQ 250 Q 5 kQ 500 Q

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QUESTION 5

a) Figure 5a shows a TTL signal line changing from HIGH to LOW state. The reflection
coefficients at the sending end is -0.80 and at the receiving end is +1.5.Explain in
detail how undershoot and ringing occurs at the V2end.
(10 marks)

Output of TTL driver

130 Q
t=0 p = -0.80

6V \s"
Vs ) 120
I V0 Vo
V2

r r
i f T

I
Figure 5a

b) Figure 5b shows a CMOS inverter driving a capacitive load, CL. The value of Vout is
governed by the exponential law given below:

Vout = VDD e'tfRC for HIGH to LOW transistions

Vout = VDD (1 - e'VRC ) for LOW to HIGH transistions

Assume the values of the capacitive load is 95 pF, RN(ON) is 130 Q, RP(0N) is 250 Q
and the defined boundary for LOW and HIGH outputs are 1.5 V and 3.5 V,
respectively.
Calculate the rise and fall times of the CMOS inverter.

Vnn = 5 V
(10 marks)

RP

Vin
-o-
V,out
CL

Figure 5b

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QUESTION 6

a) The input to a CMOS inverter is slowly changing as shown in Figure 6a.

Name the input structure that the inverter should use in order to avoid rapidly
changing output.
Comment on the difference of the input-output transfer characteristic of a
typical CMOS inverter using the input structure you have mentioned above.
Illustrate your answer with Vout versus Vin graphs.
Assume the output of the CMOS inverter, with the input structure you
mentioned above, switches states to HIGH at 2.1 V and LOW at 2.9 V of the
input. For the input signal waveform shown in Figure 6a, sketch the
corresponding Vout versus t graph of both typical CMOS inverter as well as the
CMOS inverter using the input structure you have mentioned.
Note:
Please use the paper in the APPENDIX 7 and submit it with the answer
booklet.
(10 marks)

Vin

2.9V

2.5V

2.1 V

Figure 6a

b) For the circuit shown in Figure 6b, the output of gate 1 is connected to the input C of
gate 2. Inputs A, B and D are grounded. Assume for all transistors VCEsat = 0.1 V,
VBE = 0.7 V and for diode D during forward bias has Vdiode = 0.7 V.

Name the logic gate structure of gate 2 shown in Figure 6b.

Determine the potentials at point VP, VC2, VC3 and Vx, with respect to the
ground,
(iii) Calculate the total current drawn by the gate from the dc power supply i e
Vcc.
(iv) Calculate the total power dissipated by the gate.
(10 marks)

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Gatel Gate 2
(NOR gate)

Figure 6b

END OF QUESTION PAPER

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CONFIDENTIAL APPENDIX 1 EE/OCT 2003/KEE322

SN54AS20, SN74AS20
DUAL 4-INPUT POSITIVE-NAND GATES

1ibsolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage. VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... ... 7 V
............................. 7V
Operating free-a r temperature rar ge: SN54AS20 . . . . . . . . . . . . . . . . . - 55 °C to 125°C
SN74AS20 . . . . . . . . . . . . . . . . . . . . . . . 0°C t o 70 °C
Storage tempera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°Cto 1SO°C

recommended oper iting conditions

SN54AS20 SN74AS20
UNIT
MIN NOM MAX MIN NOM MAX
Vcc Supply voltage 4.5 5 S.5 4.9 S 5.5 V
V(H HlQh'level input voltage 2 2 V
V|L Low-level Input voltage 0.8 0.8 V
'OH High-tflval output current -2 -2 mA
IOL Low-lave! output current 20 20 mA
TA Operating free-air temperature -SS 12S 0 70 °c

electrical characteristics over recommended operating-free-air temperature range (unless otherwise

noted)
SNS4AS20 SN74AS20
PARAMETER TEST C<momoNs UNIT
MIN TYP' MAX MCN TYP1 MAX
VIK 4 6v
Vcc * - . l| « -18 mA -1.2 - 1.2 V
VOH Vcc = 4.S V to 5.5 V. IQH = - 2 m A vcc -* VCC- 2 V
VOL VCC - 4.S V. IOL = 20 mA 0.3S O.S 0.35 O.S V
h VCC - S.8 V, V| •• 7 V 0.1 0.1 mA
IIH VCC " S.B V. V| = 2.7 V 20 20 cA
Hi VCC ' &.S V. V| * 0.4 V -O.S -O.S mA

<o« VCC * 5.5 V. Vo •= 2.2S V -30 - 112 -30 -112 mA

'CCH VCC * 5.5 V. V| ^ 0 V 1 1.6 1 1.6 mA
"CCL Vcc " 6-5 v- V| •> 4.6 V 5.4 8.7 S.4 8.7 mA

' All typical values in at Vcc •= 6 V, TA . 25 "C.

* Tto oiftput conditions have b»n chosen tp produce a current that closdy'approximates one half of the true short -circuit output current, IQS-

switching characteristics (see Note 1 )

Vcc - 4-6 V to S.S V.
Cj. - SO pF,
FROM TO Hi - BOO 0.
PARAMETER UNIT
IINPUTI (OUTPUT! TA - MIN to MAX
SNS4AS20 SN74AS20
MIN MAX MIN MAX
«PLH . Any Y 1 6.S 1 S
ns
<PHL Any Y 1 S 1 4.6

MOTE 1 : Load circuit and voltage waveforms are shown In Section 1 .

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 EE/OCT 2003/KEE322
CONFIDENTIAL APPENDIX 2

00
CON SECTION DIAGRAMS
PINOUT A

54/7400
54H/74HOO
54S/74SOO LI 3 Vcc
E 3
54LS/74LSOO m
QUAD 2-INPUT NAND GATE
E
E
-J<£ S3
US
E —' g r— 3
E __ J J.TL I]
OHO|7 I]

ORDERING CODE: See Section 8

aiu COMMERCIAL GRADE MILITARY GRADE ,„„ PINOUT 0
PKQS ftllT VCC - +5.0 V ±5%. Vcc - +5.0 V ±10%, „-_
WUI
TA-0«Cto+70*C TA«-65*Cto+12S*C
Plastic 7400PC. 74HOOPC
tt
DIP (Pi 74L800PC. 74SOOPC
G
Ceramic 7400DC. 74HOODC 5400DM, (4HOODM ..
DIP (D) 74LSOODC, 74SOODC 54LSOOOM, S4SOODM OA E
Flatpak A 74LSOOFC. 74SOOFC S4LSOOFM, 64SOOFM „
[TjONO
(F) B 7400FC. 74HOOFC 5400FM, S4HOOFM
3

INPUT LOADING/FAN-OUT: See Section 3 (or U.L. definition*

S4/74 (UL.) S4/74H (U.L.) 54/74S (UX.) 54/74LS (U.L.)
E
E 3^ a E

INNS HIGH/LOW HIGH/LOW HlOWtOW HIGH/LOW

Input* 1.0/1.0 1.25/1.25 1.25/1.25 0.5/0.25
Outputs 20/10 12.5/12.5 25/12.S 10/5.0
(2.SI

DC AND AC CHARACTERISTICS: See Section 3*

84/74 5*74H 54^48 S4^4LS
SYMBOL PARAMETER UNITS CONDITIONS
Mln Max Mln Max Mln Max Min Max
ICCM Power Supply 8.0 16.8 16 1.6
mA V(N = Gn<l ^
«Max
(COL Current 22 40 36 4.4 VIN « Open
»PLH 22 10 -2.0 4.S 10
Propagation Delay ns Fig*. 3-1, 3-4
tPML 15 10 2.0 S.O 10
•OO Urnlti ipptr «w operating Umpmlun tMgr. AC (Into upply K T« • *W«C IM Vcc - +5.0 V.

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 APPENDIX 3 EE/OCT 2003/KEE322
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20
CONNECTION DIAGRAMS
PINOUT A

54/7420
54H/74H20
54S/74S20 E 2) Vcc
54LS/74LS20 E 13
DUAL 4-1NPUT NAND GATE
NC(T 33
E 53 «c
E I
E II
o«o(T 3

ORDERING CODE: See Section 9

COMMERCIAL GRADE MIUTARY GRADE PINOUT B
PIN PKG
PKGS Vcc = +5.0 V ±5%, Vcc = +5.0 V ±10%,
OUT TYPE
TA-=0'Cto+70'C TA="55«CtO+125'C

Plastic 7420PC, 74H20PC 9A

DIP (PI 74S20PC. 74LS20PC E
Ceramic 7420DC, 74H200C S4200M. S4H20DM E 13
6A
DIP (01 74S20DC, 741S20DC S4S20DM. 54LS20DM ill
Flatptk 74S20FC. 74LS20FC 54S20FM, S4LS20FM tTjoNO
(Ft
7420FC, 74H20FC 5420FM. S4H20FM H
II
INPUT LOADING/FAN-OUT: See Section 3 tor U.I. definitions
II
PINS
$4/74 (U.L.) S4/74H (U.L) 54/746 (U.L.) S4/74LS (U.L)
HIGH/LOW HIGH/LOW HIGH/LOW HIGH/LOW
Inputs 1.0/1.0 1.25/1.25 0.5/0.25
Outputs 20/10 12.5/12.S 25/12.6 10/S.O
I2.S)

DC AND AC CHARACTERISTICS: See Section 3*

SYMBOL
'54/74 54/74H 54/74S 54/74LS
CONDITIONS
PARAMETER UNITS
Min Max Min Max Min Max Min Max
ICCH Power Supply 4.0 8.4 8.0 0.8 VIN = Gnd
mA Vcc = Max
ICCL Current 11 20 18 2.2 VIN = Open
IPLH Propagation Delay 22 2.0 4.5
Figs. 3-1. 3-4
tPHL IS 2.0 5.0
•DC UffllM tpply ov«r omitting Um(nr«(uf« rang*: AC llmllt »pply it T* « »M'C tnd Vcc * *t.O V.

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CONFIDENTIAL APPENDIX4

37
CONNECTION DIAGRAM
PINOUT A

54/7437
54LS/74LS37
QUAD 2-INPUT NAND BUFFER

ORDERING CODE: See Section 9

LI ———T 9vcc
COMMERCIAL GRADE MILITARY GRADE Dlcn
PIN
PKGS Vcc = +5.0 V ±5%, Vcc = +5.0 V ±10%, TypE
E ——i i— 01
OUT [J ——j I M~"L tij

Plastic [7 ———| t—— tt]

A 7437PC, 74LS37PC 9A
DIP (PI
Ceramic A 74370C, 74LS37DC 5437DM, 54LS370M 6A E ——".fi"*-3
DIP(O) GHO[T i-— g
Flatpak 7437FC, 74LS37FC 5437FM, 54LS37FM 31
A
(Ft

INPUT LOADING/FAN-OUT: See Section 3 tor U.L. dellnldons

54/74 (Ul~) 54/74LS (U.L.)
PINS HIGH/LOW HIGH/LOW
Inputs 1.0/1.0 0.5/0.25
Outputs 30/30 30/15
(7.5I

DC AND AC CHARACTERISTICS: See Section 3'

54/74 54/74LS ..„,_-
SYMBOL PARAMETER CONDITIONS
Mln Max Mln Max

Outpu t HIGH Voltage ——3~

2.4 2.5 Vcc = Max, IOH = -1.2 mA
VOH
2.4 2.7 VIN = VIL
XM.XC 0.4 tot = 48mA v ,
Vot Outpu t LOW Voltaoe • XM 0.4 V IW = 1?mA, ,„ Vlig =2 0 V
VlH 2 ov
XC 0.5 l0L = 24mA '
Oulout Short XM -20 -70 -30 -130
los Circuit Current XC -16 -70 -30 -130
Vcc •= Mln, VOUT = 0 V

ICCH Power Supply Current

15.5 2.0 Vin = Gnd v _ M
ICCL 54 12 "* VIN = Open """ '"""
»PLH 22 20
Propagation Delay Figs. 3-1, 3-4
tf>HL 15 20
*OC limit* apply ovar operating tamparalw* rano«: ACIIrnlti apply at T> * +25*0 and Vcc * +5.0 V.

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CONFIDENTIAL APPENDIX 5 EE/OCT 2003/KEE322

32
CONNECTION OIAORAM
PINOUT A

54/7432
54S/74S32
54LS/74LS32
QUAD 2-INPUT OR GATE
(T ___ " 2J»«
ORDERING CODE; See Section •
COMMERCIAL ORAOE MILITARY ORAOE
E —J filljg
MU n(o

PKO» .j.,- Vcc « +6.0 V ±6%. Vcc-«.OV±10*.

(7 ... I . n]
*"" TA-0«CtO+TO*C TA " -«S«C to 412S«C *™
PlMtlC . 7432PC, 74S32PC
BA
OIP(P) * 74L832PC E —-" rP-3
Ceremlc 74320C. 74S320C 6432DM. 64S320M ,. owofT 1—— 3
DIP(O) " 74LS320C MLS32DM
Fl*tp*k 7432FC, 74S32FC 6432FM. 64S32FM ..
A 3I
<R 74LS32FC ML632FM

INPUT LOADINO/FAN-OUT: See Section 3 tor U.L. definition*

S4/74* (O4-) I4/74LS (U.L.)
PIN*
HlOH/LOW HIGH/LOW HlOH/LOW
Inputs 1.0/1.0 1.25/1 JS O.S/0^5
Output* 20/10 29/12.6 10/64
(2.6)

OC AND AC CHARACTERISTIC*: See Section 9 lor U.L. definition*

(4/74 M/T4S S4/T4L*
SYMBOL PARAMETER UNtTS CONDITIONS
Mln Mw Mlrt M«x Mln. Mw
tecM 22 32 6J! „„ V1H-Open,__u.y
Power Supply Current
ted as Vm-Qnd
•KM Propegetlon Oeley
15 2.0 7.0 IS
n» fig*. 3-1, 3-5
tPHL 22 2.0 7.0 16
•OC limlU tfttr *Mr o^*r«ln« M<np*Miun (Mf«; AC ttfflll) wpl» M TA • +«4'C«>4VCC-+50V.

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CONFIDENTIAL APPENDIX 6 EE/OCT 2003/KEE322

TABLE 1 Input/output voltage levels (in volts) with VDD = VCc = +5 V

3.5 3.5 2.0 3.5 2.0 3.85 2.0 2.0 2.0 2.0 2.0
VlL(max) 1.5 1.0 0.8 1.5 0.8 1.65 0.8 0.8 0.8 0.8 0.8
FOH(min) 4.95 4.9 4.9 4.9 4.9 4.4 3.15 2.4 2.7 2.7 2.5
0.05 0.1 0.1 0.1 0.1 0.44 0.1 0.4 0.5 0.5 0.5
1.45 1.4 2.9 1.4 2.9 0.55 1.15 0.4 0.7 0.7 0.7
1.45 0.9 0.7 1.4 0.7 1.21 0.7 0.4 0.3 0.3 0.4

TABLE 2 Input/output currents for standard devices with a supply voltage of 5 V

1 40 nA 20 / 20 20 pA 20 /*A
1 1.6mA 0.4mA 0.5mA 100 fj-A 0.6 mA
24mA 8mA 0.4 mA 0.4 mA 2mA 400 mA 1.0 mA
24mA 8 mA 16 mA 8 mA 20mA 8mA 20 mA

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CONFIDENTIAL APPENDIX 7 EE/OCT 2003/KEE322

2.9V

2.5V

2.1V

0
Figure 6a

V,out t L

Output produced bv the tvoical CMOS inverter

Vout t k

Output produced by the CMOS inverter with the input structure mentioned

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