MATERIALS

SCIENCE &
ENGINEERING

ELSEVIER Materials Science and Engineering A199 (1995) 45-51

A

For a n e w educational strategy for ULSI microelectronics

Georges Kamarinos
Laboratoire de Physique des Composants ~ Semiconducteurs, 23, rue des Martyrs, BP 257, 38016 Grenoble Cgdex 1, France

Abstract

It is well established today that the development of integrated circuits, for at least the next decade, will be mainly based on scaled-
down CMOS technology on silicon (0.1/zm channel length, 108 transistors per chip, 10 ps delays...). A mass and efficient fabrication
must be based on two principles: (1) scientific fabrication, which means a sequence of sharply controlled physico-chemical processes;
(2) physical (not empirical) modeling and simulation of the working of the devices and of their coupling. In this paper, it is first shown
that such an approach needs to go back to the "first principles" of physics (as 50 years ago when semiconductors came into view).
Among the necessary physics developments in the domain of the physical-chemistry and of solid state physics, one can cite: molecular
dynamics; very thin oxidation and its relation to microroughness and surface states; non-Fickian diffusion; microcontamination; elec-
tromigration; exact solution of the Boltzmann transport equation (taking into account the electronic structure of the material, the tran-
sient regime and the quantum effects); analysis of the electric, electromagnetic and phononic coupling of devices and their noise; etc.;
Then it is shown that these developments need: (1) a revision of the classical educational program for microelectronics materials and
processes; a list of "new" topics to-be-developed is given; (2) a very tight coupling of R&D industrial laboratories with university
teams; they have to work on the same space and with the same equipment for technology research projects (doctor degree preparation).
The above two points can constitute the framework for a new educational strategy involving, in a new base, a closer collaboration be-
tween university and industry. Finally, it is shown that Grenoble can be a strong pole in an efficient European Network for the 21st
century silicon microelectronics.

Keywords: Silicon; Microelectronics; Integrated circuits; Electronics education

1. I n t r o d u c t i o n : the importance of silicon sity, 1.40/year in complexity, 1.24/year in speed.

microelectronics
It is well established today that in the heart of an elec-
tronic system, the signal processing unit is the principal
element; this unit is composed of electronic devices be-
longing to one or more integrated circuits (IC).
The development of these IC, and consequently the
development of computers, is based on the continuous
development of silicon microelectronics (Si-pe).
This technology goes continuously to:
- higher speeds (frequencies),
- higher scaling-down (miniaturization),
- higher densities (higher number of transistors per
cm2),
- higher complexity (higher number of functions in a
chip).
During the last decade the IC are characterized by an
increase of: 1.1 5/year in scaling-down, 1.31/year in den-
Stating that Si microelectronics is very important for
economic development is not sufficient: one has to add
that CMOS technology (Complementary Metal-Oxide-
Semiconductor) will cover probably more than 80% of
the world market of ICs in a few years (Fig. 1); in the
same figure one can see that Si will continue to cover
99% of the market when other semiconductors (like
GaAs) will continue to share only 1% of the same IC
world market [1].
It is thus evident that education concerning the physi-
cal-chemistry and the physics of:
- the silicon material,
- the physicochemical processes involved in the fabri-
cation of the electronic devices,
- the transport of carriers in electronic devices, when
they are scaled-down,
are of paramount importance for research and the industry
engineers for the immediate future.

0921-5093/95/$09.50 © 1995 Elsevier Science S.A. All rights reserved

S S D I 0921-5093(95)09906-9
46 G. Kamarinos I Materials Science and Engineering A199 (1995) 45-51

<1% 1% 1% 2%
100
,i, \ 1% Gabs
,4*/. ECL _ 4% " "" ~'\ AND OTHER
6% 4%
go 1-1"LAND 12% g% BIPOLAR
19% OTHER
15% 15%
80
20% 5% 1%
BIPOLAR
70 10%
ANALOG

60 <1%
PMOS
rr
50 24%
ill
13. 71%
40 81% MOS
NMOS 64%
41%
30

20
39%

10 CMOS
1% 1% BiCMOS
0 112% / / "',
I
1982 1987 1991 1996
($10.2B) ($2g.0B) ($52.2B) ($I07.0B)
1990
($47.8B)
YEAR

Fig. 1. World market for IC (1982-1996).

2. Today's state-of-the-art and expected progress for - a CMOS circuit,

the beginning of the 21st century in silicon
microelectronics
The R & D laboratories of the most important industries
today develop and study [1,2]:
- D R A M (memory) of 256 Mbit,
- transistors (MOST) of channel length (L) of 0.25/~m,
- integrated circuits having 108 MOSTs per chip,
- devices of a speed of 100 ps,
- processes on wafers of diameter 200 mm,
This is the V L S I (Very Large Scale Integration) step of
Si-/~e.
In the more advanced basic research laboratories to-
day:
- the M O S T of length L of 1000/k or less is a
" c o m m o n " object;
- the M O S T of 100/~ is fabricated and it works [3,4],
- the M O S T of (a channel length of) 300 ~ is correctly
modelled and simulated for its electrical working)
[5].
The trend for the first decade of the 21st century is the
fabrication of the Giga-Chip; this IC will be:
- memory of, at least, 1 Gigabit; it will be thus possible
to transmit:
- 10 Gigabit information/s, or to process:
- 1 GIPS (Giga-instructions/s); such an integrated cir-
cuit will have:
- 10 l° MOS transistors (the human brain has 10 ~2 neu-
rons).
- the channel length of a M O S T in such a chip will be
50oA,
- the speed of the M O S T will be on the order of 10 ps,
- the Si wafer, in the beginning of fabrication, will
have a diameter of 300 mm.
This will be the ULSI (Ultra Large Scale Integration)
step of Si-/~e. The cost of an industrial setting (pilot-line
and peripherals) for such a fabrication is higher than 109
US dollars [6].
It is therefore evident that a concentration of invested
capital for such a strategic activity is unavoidable. Such
industries will exist only in economically healthy coun-
tries where an important source of flexible and competent
technicians, engineers and researchers will be available in
place.
 G. Kamarinos / Materials Science and Engineering A199 (1995) 45-51
3. M a t e r i a l science and development of Si-/te:
remaining technological problems and educational
needs
The development of Si-/~e depends on the advance-
ment of the knowledge and the technological progress
concerning: (a) the technical processes of fabrication; (b)
the working of the devices and the integrated circuits.
(Evidently the design, the CAD, the architecture and
testing of IC are very important, but these fields are not
discussed in the present approach.)
In the following paragraphs, a very brief review of the
more important remaining problems of Materials Sciences
and Physics concerning the above items, (a) and (b), is
given. Education orientations are suggested.
3.1. Technical p r o c e s s e s
The lithography drives the rate of the development of
Si-/~e. Phase shift deep ultraviolet (P-S) lithography for
the near future (for lines of 100 nm) will replace the opti-
cal lithography (x = 400 nm) of today. For the ULSI step
(L < 1000/~) probably electron beam lithography will be
operational [7].
The problems facing this kind of lithography are es-
sentially two: (i) the back scattering of secondary elec-
trons; (ii) the coulombian interaction of primary electrons.
Oxidation [8] is also a key step in the fabrication. It
ensures not only the isolation between different devices
(thick oxides) but also the gate isolation (very thin oxides
or other dielectrics).
Thin gate oxidation (thickness not lower than 30 A) is
a very important step for ULSI and several physico-
chemical problems have now to be examined; one can
cite [9]:
- native oxidation (0-20 ]k),
- the influence of surface microroughness in thin oxi-
dation,
- the influence of surface microcontamination
(Ns < 101° cm -2) to thin oxidation,
- the relationship between electrical breakdown and
surface microroughness [ 10],
- the relationship between the electrical barrier in the
interface (Si/SiO2) and the oxide thickness,
- the preparation of ultra-clean oxides (to avoid dis-
persion of the threshold voltage of the MOS transis-
tor),
- etc.
The physics of ion implantation at very low energies
(3-15 keV) and with strong currents, for the fabrication
of shallow junctions (xj < 500/~) constitute the more im-
portant problem to be faced [11].
The Fickian approach for diffusion is always of the
highest interest and particularly' the defect-assisted diffu-
sion in preamorphization steps (for shallow junctions).
The macroscopic approach of the diffusion allows a nu-
47
merically possible calculation of 2D or 3D impurity pro-
files [12,13].
The CVD-PVD [14] (chemical and physical vapor
deposition) techniques are, of course, of rapidly increas-
ing interest. Indeed modern microelectronics has
"become" a surface science [15]; but the more important
processes are, yet, approached with an empirical and mac-
roscopic view, which is not satisfactory for reaching the
requirements of modeling and simulation of devices and
circuits [16]. We need therefore a "scientific approach"
to:
- surface reactions kinetics far from thermodynamic
equilibrium; one has to take this into account in such
an approach,
- the dynamics of gas flux near the surface,
- among other problems one can also cite selective
epitaxy,
- rapid thermal annealing has to be described and ex-
amined also in the light of non-equilibrium thermo-
dynamics.
The return to basic and classical thermodynamics and
the emergence of non-equilibrium thermodynamics and
molecular dynamics for nearly all the physico-chemical
steps of fabrication is the principal and the essential char-
acteristic of the new educational era for silicon microelec-
tronics. These "first principles" or elementary (particular)
approaches can give solid indications for the establish-
ment of macroscopic laws for oxidation, diffusion and
vapor deposition of thin films; these laws can then be
inserted into R&D simulation numerical programs.
This remark is also valid for the synthesis of silicides
(in particular germanium alloys) [17] and for more com-
plex phenomena such as electromigration [19] which now
constitutes a serious drawback of scaling-down as it
threatens the reliability of the circuits. For this phenome-
non, an abundant literature exists but a satisfactory de-
scription of the failure (of metallic lines) process as well
as the solution to technical problem are yet unknown.
ULSI silicon microelectronics requires a minimum in
the dispersion of the electrical characteristics of the tre-
mendous number of devices on a chip. This non-dis-
persion can be reached only by a very homogeneous fab-
rication on a Si wafer. Consequently each elementary
process must be exactly known and firmly controlled in
the environment and for the geometry of the R&D
equipment. The ULSI requires a scientific fabrication
which ensures a minimum number of random defects in
the circuit. In this context the role of microcontamination
[9,20] on the surface as well as in the bulk of the material
emerges as a first order item. It is known that the "zero-
defect" scientific fabrication needs the control of the in-
fluence of very low concentration of contaminants:
Nss < 10 9 cm -2 in the surface of less than 10 I1 cm -3 in the
bulk of the material [20].
So a number of very exciting metrological problems
await solution:
 48 G. Kamarinos I Materials Science and EngineeringA199 (1995)45-51
- How to measure these concentrations in a (already
doped or processed) surface or volume?
- How to detect a particle of 0.03/zm size locally in the
clean room of the R&D laboratory?
- How to measure two foreign particles in a milliliter
of a liquid used in a process in an R&D environ-
ment?
(to the above metrology challenges one can add the diffi-
culties of temperature, and AT, measurement in situ).
The above very brief review of the problems arising in
scientific fabrication, required by ULSI Si-/te, points out
that research activities concerning fabrication cannot be
performed far from the environment of the R&D labora-
tory. The absolute necessity of the injection of the basic
research activities in the R&D laboratories is a new re-
quirement. It is so evident that R&D laboratories con-
nected with the industrial centers must fund the insertion
of basic (university groups) research teams in their envi-
ronment; a direct consequence of this remark is also that a
part of the activity and the equipment of such a laboratory
must serve the education of future engineers and re-
searchers for ULSI Si-/ze.
3.2. Physics of working ULSI devices and circuits
The design and the simulation of working VLSI
ICs are based implicitly, up to now, on the partition prin-
ciple [21,22]. According to this principle an IC is a net-
work of discrete devices which are operating discretely;
they communicate only by established metallic connec-
tions.
This principle holds for the "macroscopic scale" of
integration where the channel length L of a MOS transis-
tor is longer than the mean free path of electrons l, and l is
very much longer than the radius of the collisions of car-
riers with the lattice
<< l < L, macroscopic scale
The macroscopic scale of integrations holds so that when
L is higher than 0.3/zm. For this scale all transport phe-
nomena can be satisfactorily approached with the con-
cepts of effective mass (m*eff), the bands of electron en-
ergies, etc.; the current is strongly connected to the elec-
tric field (except for very high frequencies (f> 100 GHz)
and the conduction regime is stationary.
The simulations of I,V characteristics of such devices
are based on hydrodynamic-like equations or, better, on
the classical integration of the Boltzmann equation. Even
high field effects are classically approached with suffi-
cient accuracy.
The future ULSI IC will include devices which will be
characterized by
~. << l = L, intermediate scale
The channel length of the elementary MOS transistor will
satisfy
200/~ < L < 1000 A,, ULSI line width
Here the partition principle fails, indeed:
- The screening effects and the corresponding lengths
depend on fields and geometry; the injection of
charge is not efficient and the "vertical quantifica-
tion" in the channel drives many transport global co-
efficients and effects.
- Inertial effects appear; the current is not highly cou-
pled with the electrical field (in time and space); the
transport becomes ballistic, the electron velocity
overshoot is observed and the collision cross sections
depend on fields.
In this step of integration, the Boltzmann treatment of
electronic transport is still valid if perturbation methods
are applied and high electric field effects are well ap-
proached in spite of their complexity [23].
For higher levels of integration, the nanostructures on
Si will be analyzed as quantum objects; their intercon-
nections will be seen as de Broglie wave guides and the
analysis of the influence of the high electric fields is yet
unknown [24]. Evidently these structures probably will
come after the ULSI step but even today the 9, fl struc-
tures, the permeable base transistor and the nanoparticular
systems (e.g. diodes on porous silicon) constitute 2D, 1D
or 0D nanostructures on silicon [25-29] (Fig. 2),
There are two important problems due to the scaling-
down and the high density of integration; they are caused
by two types of effects:
- the high electric field effects which provoke the deg-
radation (ageing) of the devices and the failure or the
loss of the reliability of an integrated circuit [30],
- the inter-devices coupling effects which affect the
reliability of the IC [21,22].
(a) The high electric fields ( E > 106V/cm) and the
conduction by hot carders result in the:
- injection into oxides (gate and isolation oxides),
- generation of crystalline defects near the drain or into
the gate oxide;
- impact ionization near the drain;
- increase in the electrical noise of the transistor ( l l f
excess noise).
To avoid these effects or to remediate them one must in-
tervene at two levels:
- in the design and fabrication of the device and of the
circuit (to find geometries softening the field near the
drain, drain engineering, to enhance the quality and
the purity of oxides, avoid microntamination and
control microroughness, to know exactly the 2D
profile of impurity diffusion),
- in the modeling of the working of the device and of
the circuit (to lower the drain voltage, VD goes to
1 V, to identify exactly the more sensitive transport
 G. Kamarinos / Materials Science and Engineering A199 (1995) 45-51
e" beam
X - rays
ion beams
DUV Optical
10 p.m
6~ / lithography (OL
I~l _ ] Industrial
1 ~tm 10 "1~ s
0,1 p.m 10"~2s
I.... approx, fail~ Debye length
* Retarded transport Mean free path
100,~ 10-13s
Quantum regime
10~ I 10-14s
Approximation meff fails
A 1oo A 1 pm
Attainable linewidths
* Existing "laboratory" devices
R-D "research-development" devices
R "research" devices
Fig. 2. Lithography linewidth and characteristic lengths for silicon.
Ferry's diagram for present devices.
parameters and to measure them, to know exactly the
2D transport of carriers).
To develop a detailed knowledge of the working of a
device the Mont6-Carlo methods of resolution of the
Boltzmann transport equation coupled with the energy
distribution and dissipation (and, to take into account
quantum effects, the Schr/Sndinger equation) must be de-
veloped [31 ] and transferred to R&D laboratories.
The advanced numerical method of resolution of non-
linear differential equations are of growing importance
for future engineers.
(2) The inter-device coupling is due to the high density
of the devices in a chip (more than 107 MOST per cm2).
The classical coupling, i.e. capacitive of electromag-
netic (for high frequencies) is satisfactorily approached
by classical methods of elementary electrostatics and
electromagnetism. On the contrary, thermal coupling has
been neglected up to now but this situation is rapidly
changing [31,32]. The slowing down of thermalization of
phonons due to selection rules in the Si/SiO2 interface is
an exciting problem for solid state physics.
The noise in very small devices, its dispersion and its
non-stationarity and non-ergodicity constitute another
exciting problem which is now studied after the observa-
tion of the Random Telegraph Signal Noise (RTS) which
is a one-electron phenomenon observed at room tempera-
ture [33-35]. This problem is evidently connected with
the concepts of local equilibrium in a system far from
thermodynamic equilibrium.
49
Evidently the noise is not, in first order, an inter-device
effect; nevertheless its dispersion for ULSI IC can seri-
ously affect the reliability and, so, low frequency noise
can constitute a limitation for scaling down [33-35].
Another class of effects which will emerge in this scale
of integration are the cooperative effects due to strong
electrical non-linear coupling of the devices [21,22]; tun-
neling effects, superlattice effects and chaotic effects are
Depletion layer already observed in several situations.
The influence of the above effects is now considered
as a drawback for the ULSI, but a new idea is slowly
emerging. All these cooperative effects can be positively
exploited in a new architecture of integrated circuit where
the emergence of these effects is favored; the era of
de Broglie electron
wavelength ~-e "holistic integration" would therefore be open: the circuit
now works as a whole and not as a system of connected
Cellular dimensions discrete devices.
nteratomic spacing It is evident that to analyze and describe the working
100 ~m
of ULSI devices, the quantum mechanics approach of
ULSI structures, the Boltzmann treatment of transport
with advanced numerical methods, the introduction of
advanced concepts of irreversible thermodynamics and
statistical mechanics as well as the methods of treatment
of the chaotic effects must enter the Educational Program
of future engineers and researchers. On the contrary, in
the situation concerning fabrication processes, basic
(university) research can blossom and can be developed
outside of R&D groups. Evidently a tight collaboration
between R&D groups and university teams is absolutely
necessary. The R&D laboratory can then furnish the uni-
versity group with the advanced devices for characteriza-
tion and comparison with modeling and simulation; the
two groups can collaborate for the definition of long term
objectives and thus, for their common program. The mu-
tual benefits of such a collaboration is obvious.
4. Conclusion
Some years ago for good engineering in silicon mi-
croelectronics, it was sufficient to know that a semicon-
ductor is a system of two electron reservoirs with elec-
tronic localized states in the gap. The carrier concentra-
tions are described by Fermi statistics and the currents are
approached by hydrodynamical equations.
With this elementary background, it was possible for
an engineer to understand and model the usual devices
and circuits [36].
Concerning the fabrication, classical chemistry and
physical chemistry of equilibrium were sufficient and
some complicated situations were approached by empiri-
cal laws.
Now advanced VLSI and the beginning of the ULSI
era are rapidly changing the landscape; quantum mechan-
ics is again necessary to understand the electric transport
in inversion layers, numerical treatment of the Boltzmann
transport equation is used for modelling the I,V character-
50 G. Kamarinos / Materials Science and Engineering A199 (1995) 45-51
istics and the statistical m e c h a n i c s and irreversible ther-
m o d y n a m i c s are n e e d e d to understand and exploit c o o p -
erative and i n t e r - d e v i c e c o u p l i n g effects.
C o n c e r n i n g the fabrication the necessity for the return
[37,38], to basic "first p r i n c i p l e s " and the end o f empir-
ism is obvious.
T h e p r o g r a m s o f E d u c a t i o n m u s t therefore be drasti-
cally revisited. O u r analysis also s h o w s that university
research m u s t be closer to the R & D laboratories.
In the c a s e o f research (and education o f doctor d e g r e e
students) w e s u g g e s t that the university groups must w o r k
in the s a m e p l a c e and with the s a m e e q u i p m e n t as the
R & D groups. F o r studies c o n c e r n i n g the electrical work-
ing o f d e v i c e s and circuits, the two types o f groups can
c o n s e r v e their g e o g r a p h i c a l i n d e p e n d e n c e .
S u c h a s c h e m e o f c o l l a b o r a t i o n is possible in several
places in E u r o p e . F o r e x a m p l e G r e n o b l e , in France, is a
p l a c e w h e r e strong university groups ( C N R S laboratories)
and large R & D laboratories ( C N E T / C N S , L E T I / C E A )
strongly c o n n e c t e d to Industry ( S G S - T H O M S O N ) exist.
O n e can find there the b e g i n n i n g o f such a collaboration
w h i c h for the m o m e n t exists o n l y due to a voluntary im-
pulsion.
References
[1] G. Courtois, CAD and testing of IC's and systems; where are we
going? TIMA/CNRS/INPG Grenoble, May 1993.
[2] (a) IEE (Journal of Electronic Engineering); spotlighting: semi-
conductors and ICs: the latest development trends on SRAMs,
ASSP LSIS, ASICs, Flash memories, MOSFETs etc. Collection of
technical review articles 29(308) (1992). (b) IEEE MICRO: chips,
systems, software, and applications. Special issue, Microelectron-
ics in Europe, August (1992).
[3] A. Harstein, Ultra-short channel Si MOSFET. Electrochemical
Society Spring Meeting, Washington, DC, 1991, pp. 432-433.
[4] Electronics: At IEDM, future IC's reach limits of theoretical
physics, (1993) p. 3 (review article).
[5] D.J. Franck, S.E. Laux and M.V. Fischetti, MontE-Carlo simula-
tion of a 30 nm Dual-Gate MOSFET: how short can Si do ?. In-
ternational Electron. Devices Meeting: IEDM 92, 1992, sponsored
by E.D Soc. of IEEE Technical Digest, 1992, pp. 553-556.
[6] D. Bois, Perspectives techniques et 6conomiques des composants
intEgrEs. L'onde dlectrique 73(6) (1993) 4-10.
[7] C. Morgan, Giin Shan Chen, C. Boothroyd, S. Bailex and C.
Humphreys, Ultimate limits of lithography, Phys. World, 5(11)
(1992) 28-32.
[8] E.A. Lewis and E.A. Irene, Models for the oxidation of silicon, J.
Vac. Sci. TechnoL A, •4(3) (1986) 916-925.
[9] T. Ohmi and T. Shibata, Scientific ULSI manufacturing in 21st
century. The electrochemical Society, Interface, 1 (1992) 32-37.
[10] S. Verhaverbeke, Dielectric breakdown in thermally grown oxide
layers. Thesis, Katholieke University Leuven, Imec, 1993.
[11] L. Laanab, G. Bergaud, M.M. Faye, D. Faure, A. Martinez and A.
Claverie, A model to explain the variation of "end of range"
densities with ion implantation parameters, Mater. Res. Soc.
Syrup. Proc., 279 (1993) 381-386.
[12] S. List, P. Pichler and H. Ryssel, Atomistie evaluation of diffusion
theories for the diffusion of dopants in vacancy gradients. Simu-
lation of Semiconductor Devices and Processes, Vol. 5, Springer-
Verlag, Vienna, 1993, pp. 97-100.
[13] M.E. Law, Achieving accurate 3D process simulation. Simulation
of Semiconductor Devices and Processes, Vol. 5, Springer-Verlag,
Vienna, 1993, pp. 1-8.
[14] K.E. Spear and J.O. Carsson, Chemical vapor deposition in the
21st century. The electrochemical Society, Interface, 2 (1993) 39-
47.
[15] D.K. Ferry, The role of interfaces in ultrasmall semiconductor
devices, J. Vac. Sci. Technol. B, 2(3) (1984) 504-509.
[16] F.Z. Bathaei, Silicon device miniaturization and its effect on
processing technics, Microelectronics J., 20(4) (1989) 1-9.
[17] K. Maex, Silicides for integrated circuits: TiSi2 and CoSi2. Imec
Leuven, Mater. Sci. Rep., (1993) in press.
[18] G. Abstreiter, Engineering the future of electronics, Phys. World,
5(3) (1992) 36--39.
[19] G.L. Baldini, I. De Munari, A. Scorzoni and F. Fantini, Elec-
tromigration in thin films for microelectronics, Microelectr. Re-
liab., 33(11/12)(1993) 1779-1805.
[20] W. Rieger, The impact of impurities in chemicals on the perform-
ance of DRAM's Siemens AG semiconductor grofip report, 1992,
Otto-Hahn-Ring 6 D-8000 Munchen 83, Germany.
[21] J.R. Barker, The physical limitations of integration and size re-
duction in semiconductors, Microelectronics J., 17(1) (1986) 15-
25.
[22] J.R. Barker, The physical limitations of integration and size re-
duction in semiconductors, Int. Conf. on New Trends in Inte-
grated Circuits Proceedings, Pads, 1987, pp. 240-246.
[23] F. Poupaud, About Boltzmann equations for transport modeling in
semiconductors. Simulation of Semiconductors Devices and Proc-
esses, Vol. 5, Springer-Verlag, Vienna, 1993, pp. 17-20.
[24] K. Hess and L.F. Registrer, Modeling nanostructure devices.
Simulation of Semiconductor Devices and Processes, Vol. 5,
Springer-Verlag, Vienna, 1993, pp. 9-16.
[25] P. Chenevier, G. Kamarinos and G. Pananakakis, Universal elec-
trical characteristics and frequency limits of the permeable base
transistor. Communication in ESSDERC'93, Proceedings, Fron-
ti~res Editions, Paris, 1993, pp. 121-124.
[26] G. Bomchil et al., Porous silicon material properties, visible
photo, and electrohiminescence, AppL Surf. Sci., 65/66 (1993)
394-407.
[27] L. Canham, Silicon optoelectronics at the end of the rainbow?
Phys. World, 5(3) (1992) 41-44.
[28] R. Herino, M. Rigeon, F. Muller and J.C. Vial, Vers une optoEiec-
tronique tout silicium? La Recherche, 23(240) (1992) 248-249.
[29] M.H. Devoret, D. Esteve and C. Urbina, L'Electronique /~ un
Electron, Bull. Soc. Fr. Phys., 93 (1994) 7-11.
[30] S. Cristoloveanu, Physical mechanisms of hot-carrier-induced
degradation in deep submicron MOSFETs. Invited conference in
ESSDERC'93, Proceedings, Fronti~res Editions, Pads, 1993, pp.
797-808.
[31] D. Chen, Z. Yu, K. Gwn, R. Gooscens and R.V. Dutton, Dual
energy transport model with coupled lattice and carrier tempera-
tures. Simulation of Semiconductor Devices and Processes, Vol.
5, Springer-Verlag, Vienna, 1993, pp. 157-160.
[32] G. Ghibaudo, H. Jaouen and G. Kamarinos, Integration density
limitation in 3D ICs due to heat dissipation, Europhys. Lett., 2(3)
(1986) 209-211.
[33] G. Kamarinos, Final report of EEC ESPRIT BRA No. 3017
"Noise", ENSERG/LPCS/CNRS, Grenoble, 1992.
[34] G. Kamadnos, Noise in advanced microelectronics: submicron, 2-
D gas and low temperature electronics. In T. Musha et al. (eds.)
Int. Conf. on Noise in Physical Systems and 1/f Fluctuation,
Kyoto, Japan, 1991, pp. 303-308.
[35] J. Brini, G. Ghibaudo, G. Kamarinos and O. Roux-Dit-Buisson,
Scaling-down and low frequency noise in MOSFET's. Are the
RTS's the ultimate components of the l/f noise? In P. Handel
(ed.), Quantum 1/f Noise and Other Low Frequency Fluctuations
in Electronic Devices, AlP Conference Proceedings 282, Am.
Inst. of Phys., New York, 1993, pp. 31--48.
 G. Kamarinos I Materials Science and Engineering A199 (1995) 45-51 51

[36] C.T. Sah, Fundamentals of Solid State Electronics, World Scien- [38] A.B. Fowler, A semicentury of semiconductors, Phys. Today,
tific, Singapore, 1991. October (1993) 59-62.
[37] G. Busch, Early history of the physics and chemistry of semicon-
ductors: from doubts to fact in a hundred years. Condensed Mat-
terNews. 2(1) (1993) 15-27.