40 Gbs Emphasis, CDR, and Equalizer CMOS Circuit Design

1
40 Gb/s Pre-emphasized Serializer,

Equalize, and CDR Circuit Design
with Full Channel Simulation
ZY Daniel Wu, Ansoft, LLC
© 2008 Ansoft, LLC All rights reserved. Ansoft, LLC Proprietary

Goals
2
• Ansoft provide a physics based simulation of real serial HDMI Category 2 Cable Compliance
TDR Tests
channel. Data0
TDR Source
VSS
0
U6
TDR Step Source1
OUTp
OUTm
Lead Line
T1298
T1297
T x _ Da ta _ p
T x _ Da ta _ n ref
0
Cable + Adapters
Rx _ Da t a _ p
Rx _ Da t a _ n
In 1
In Re f
In 1
L=2ft
Ou t1
Ou t Re f
Ou t1
Rx _ Da ta _ p
Rx _ Da ta _ n ref
T x _ Da ta _ p
T x _ Da ta _ n
Terminator
M
U5
TDR Terminator
Z
GND
0 0 0
In Re f Ou t Re f
0
L=2.02ft U12
U7
TDR Step Source1 L=2.2ft TDR Terminator
T x _ Da ta _ p Rx _ Da t a _ p Rx _ Da ta _ p T x _ Da ta _ p
OUTp In 1 Ou t1 P
Data1 VSS OUTm T1331 T x _ Da ta _ n ref Rx _ Da t a _ n In Re f Ou t Re f Rx _ Da ta _ n ref T x _ Da ta _ n M

Z
GND
0 In 1 Ou t1
0 T1334
In Re f Ou t Re f
0 0 0 0
L=2.21ft U13
U18
L=2.05ft TDR Terminator
TDR Step Source1
OUTp T x _ Da ta _ p Rx _ Da t a _ p In 1 Ou t1 Rx _ Da ta _ p T x _ Da ta _ p P
Data2 VSS OUTm T1371 T x _ Da ta _ n ref Rx _ Da t a _ n In Re f Ou t Re f Rx _ Da ta _ n ref T x _ Da ta _ n M

Z
GND
In 1 Ou t1
0
0 T1370
In Re f Ou t Re f
0 0 0 0
L=2.065ft
• This work shows how true transistor-level SerDes circuit can

be added.
• The benefit of this work is now SerDes IC designer can

realize full design & analysis including channel and data_in
R10
50 R13
integrated circuit.
E20 E26
50
V58
V1=-0.2
V2=0.2 0
GAIN=1 GAIN=-1
0 TRF=1/data_rat/5
PW=4/data_rat/5
TONE=0
V34
DC=0.782
U6
PCBtrl
Die_P Ball_P ln1 ln1_t Ball_P Die_P

ln2 ln2_t
Die_N Ball_N Ball_N Die_N
~0.681cm ~9cm ~0.681cm
• Based on the assessment of 65nm bulk CMOS, the wave of avdd
single-chip 40 Gb/s will be coming soon. (Think of 32nm

V27 V31
50
50
DC=0.782 DC=1.2
R16
R19
0 0
net0164 vco_tune
avdd
avdd
bulk CMOS)
in clk clk_o
inb out eq_out in clkb clk_ob
nbias outb eq_outb inb CDR out cdr_data_o
vtune outb cdr_data_ob
vco vco
agnd
agnd
vcob
avdd
0 0
avdd
V40
vcob
DC=0.6
v_irefp
0
v_irefn
agnd

3
Agenda
• Introduction & System Overview

• Circuit Designs
– Pre-emphasized Serializer
– Equalizer + Clock Data Recovery (CDR)
• Electrical Channel Modeling & Design
• QuickEye and VerifEye for Equalizer & CDR
• Conclusion

4
Introduction
&
System Overview

5
Introduction & System Overview

100 Gb/s or 40 Gb/s Architecture: Example
Electrical Optical Electrical
Interface link Interface
m lanes
n lanes n lanes
100 Gb/s 100 Gb/s
100 Gb/s 100 Gb/s
or or
or or
40 Gb/s 40 Gb/s
40 Gb/s 40 Gb/s
Optical Optical
ASIC ASIC
Module m lanes Module
n lanes n lanes
• Electrical lanes: ribbon cable, backplane

– 4X10G, 2X20G, or even 1X40G for 40 Gb/s
– 10X10G, 4X25G, 2X50G, or even 1X100G for 100 Gb/s
• Optical links: fibers, WDM, or complex modulation
– 4X10G, 2X20G, or even 1X40G for 40 Gb/s
– 10X10G, 4X25G, 2X50G, or even 1X100G for 100 Gb/s

6
Introduction & System Overview

D0
D1 40 Gbps PCB Channel

D2
Serializer De-Emphasizer
.
.
.
Dn
du le
Mo
Clk
p t ical
O
du le
Mo
p t ical
O
D0’
Continuous Serialized data D1’
Time CDR DeSerializer D2’
40 Gbps PCB Channel Equalizer .
.
.
Push speed to CMOS SerDes frontend Dn’
• used tech node (like 65nm) capable?
• single low cost backplane channel possible? Recovered clock

7
Circuit Designs
(w/ 65nm CMOS PDK)

8
Circuit Design_Pre-emphasized Serializer

Behavioral Simulation
(de, do)… for main cursor
RCONST
mux_in1
mux_in2
SP
SP
(dod, ded)… for post cursor
RbSb
SP
U1 retime_out1
mux2to3
de
RANDOMÎ
BSRC mux_in1 SP
10 Gb/s SAMPREP mux_out1 R Q D
ded U3
20 Gb/s Î
mux_out
C LATCH INV 4select2
mux_in2 DFF SINK SP
RANDOM Î
BSRC
10 Gb/s SAMPREP D Q C dedb
Q1
S
40 Gb/s
clk_in
I1 de
SP Q2 SP
mux_in3
mux_in4
retime_out2 de
SP
SP
I2
clk do
R Q D
do
RbSb
clkb SP
U2
mux2to3
C
D
DFF
Q
SINK
C
LATCH D
LATCH INV
dod do
RANDOMÎ
10 Gb/s
BSRC mux_in1 SP SP
sel
SAMPREP mux_out2 S C dodb
mux_out
20 Gb/s Î
RANDOM Î
BSRC mux_in2
10 Gb/s SAMPREP
INV
clk_in
RCONST
20 GHz
SP
clk_div2
20 GHz R Q
SINK
DCLK
C
DFF
D Q
S
10 GHz
SP
Pre-Emphasized
clk_in
Mux
de
+ 40 Gb/s
dod
do
+
ded
Reference paper: ISSCC 2008, 5.7, pp 110~ 111 tap weight <0:3>
20 GHz
9

Circuit Brief
20 Gb/s de
ded
10 Gb/s Î
10 Gb/s Î 40 Gb/s Î
10 Gb/s Î
10 Gb/s Î
do
dod
10 GHz
20 GHz Î

10
Simulation Results (TRL Length = 15 cm)
w/o pre-emphasize
V107
DC=1.2
0 rx
avdd
d0 d0
50
R135
d0b d0b
E77 E76 d1 d1
d1b d1b out out 1
E83 E84 d2 d2 outb
d2b d2b outb 2
E95 E94 d3 d3
0
GAIN=1 GAIN=-1
d3b d3b 0 W132 0 V138
E101 E102
0
50
V179 GAIN=1 GAIN=-1 DC=0.7
R136
w0
w/ pre- emphasize
0 w1 0
V75 V182 GAIN=1 GAIN=-1
0 w2 rxb
DC=1
0 w3
V85 V185 GAIN=1 GAIN=-1
0 0
DC=1 nbias
V93 V188
0 0 buf_bias
DC=1 V110
V103 DC=1.2*w0
clkinb
agnd
clkin
0 0 V122
DC=1
V175 0 V113 DC=0.56
0 0
VLO=-0.2V DC=1.2*w1
VHI=0.2V V176 0 V125
VTH=0V 0
TR=1/data_rat/10 VLO=-0.2V V116 DC=0.65
TF=1/data_rat/10 VHI=0.2V V177 DC=1.2*w2
BITWIDTH=1/data_rat VTH=0V 0
TR=1/data_rat/10 VLO=-0.2V
TF=1/data_rat/10 VHI=0.2V V178 0 V119
BITWIDTH=1/data_rat VTH=0V
TR=1/data_rat/10 VLO=-0.2V DC=1.2*w3
V171 TF=1/data_rat/10 VHI=0.2V
V1=-0.2
V2=0.2
BITWIDTH=1/data_rat VTH=0V
TR=1/data_rat/10 w0: MSB 0 V126 V130
V172 TF=1/data_rat/10 VA=0.3 VA=0.3
TRF=1/data_rat/5 BITWIDTH=1/data_rat
V1=-0.2 FREQ=20g FREQ=20g
PW=4/data_rat/5
TONE=0 V2=0.2 V173 0 THETA=0 0 THETA=180deg
TRF=1/data_rat/5
PW=4/data rat/5 V1=-0 2

11
Circuit Design_Equalizer + CDR
Reference paper: ISSCC 2008, 5.2, pp 100~ 101

Circuit Design_Equalizer & CDR
12
Equalizer Design Equation:

Ansoft Corporation XY Plot 1 CoupledTrlFreqRespond
0.00
Curve Info
Name X Y
m2 m1 40.0200 -18.3078 dB(S(Port1,Port1))
-10.00 LinearFrequency
m2 20.0400 -10.3544
dB(S(Port2,Port1))
m1 LinearFrequency
-20.00
Rp -30.00
Lp
Cp
Y1
-40.00
g m1 g m2 -50.00
-60.00
-70.00 DiffPair Response

g m3 -80.00
0.00 20.00 40.00 60.00
F [GHz]
80.00 100.00 120.00
Equalizer Response
CDR Design Equation: 2nd order Loop Filter (Type II, 3rd order)
1 − sin φ p sec φ p − tan φ p
Din Q1 Q3 T1 = =
ω p ⋅ cos φ p ωp
KVCO
s clk Kφ T2 =
( ) ( )
G ωp ⋅H ωp =1 =
1
ω p ⋅ T1
2
(
− K PD ⋅ KVCO 1 + jω p ⋅ T2 ) ⋅ T1
ω p C1 ⋅ N ⋅ (1 + jω p ⋅ T1 ) T2
Q2 2
T − K PD ⋅ KVCO
C1 = 1 ⋅
(
1 + ω p ⋅ T2 )2
ω p2 ⋅ N 1 + (ω p ⋅ T1 )2
÷N ≡ ÷1
T2
Z (s ) ⎛T ⎞
C 2 = C1 ⋅ ⎜⎜ 2 − 1⎟⎟
⎝ T1 ⎠
T
R2 = 2
C2
Circuit Design_Equalizer + DR
13
Simulation Results (TRL Length = 15 cm, FR4 Board)

Ansoft Corporation XY Plot 7 Top_15cmTRL Ansoft
NameCorporation
X Y XY Plot 8 Top_15cmTRL
0.00
615.00 m1 40.0000 -6.9054
Curve Info m1 Curve Info
dB(V(vco)-V(vcob))
V(vco_tune) Transient
Transient
-20.00
610.00
-40.00
Spectrum of VCO output
605.00
-60.00
(Clock output)
dB(V(vco)-V(vcob))
-80.00
600.00
V(vco_tune) [mV]
-100.00
595.00
590.00
VCO tuning voltage -120.00
-140.00
(locking & settling transient)

0.00 10.00 20.00 30.00 40.00 50.00 60.00 70.00 80.00
Spectrum [GHz]
585.00
avdd
Eye & Jitter of
V27 V31 VCO Output (=Clock Output)
50
50
DC=0.782 DC=1.2
R16
R19
580.00 0 0
net0164 vco_tune
avdd
avdd
0.00 50.00 100.00 150.00 200.00 250.00 300.00 350.00 400.00 450.00 500.00
Time [ns] R10
1
data ch_out in clk clk_o
50 R13
data_in datab ch_outb inb out eq_out in clkb clk_ob
2
E20 E26 nbias outb eq_outb inb CDR out cdr_data_o
50
W65 vtune outb cdr_data_ob
0 0
vco vco
V58
agnd
agnd
vcob
avdd
V1=-0.2
V2=0.2 0 0 0
GAIN=1 GAIN=-1
avdd
0 TRF=1/data_rat/5 V40
PW=4/data_rat/5 sig1_in sig1_out
TONE=0 vcob
DC=0.6
sig2_in sig2_out v_irefp
Input_ref Output_ref 0
V34
DC=0.782
v_irefn
0
agnd
0
Channel Output CT Equalizer Output CDR Data Output
LTI ? LTI ?
14
Electrical Channel
Modeling & Design

Modeling PCB Traces
15
(longest component in the channel)
Port1 Port2
sig1_in sig1_out
p1_ref sig2_in sig2_out p2_ref
Input_ref Output_ref
0 0
Ansoft Corporation XY Plot 1 CoupledTrlFreqRespond
0.00
Curve Info
Name X Y
m2 m1 40.0200 -18.3078 dB(S(Port1,Port1))
-10.00 LinearFrequency
m2 20.0400 -10.3544
dB(S(Port2,Port1))
m1 LinearFrequency
-20.00
-30.00
Y1
-40.00
In-direct Causality Enforcement

-50.00
-60.00
-70.00
-80.00
0.00 20.00 40.00 60.00 80.00 100.00 120.00
F [GHz]

Working with Known 10 Gb/s Channel
16
Ansoft Corporation XY Plot 8 Top_XilinxCh
Curve Inf o
m1
Ansoft Corporation XY Plot 7 Top_XilinxCh
-10.00 Name X Y dB(V(vco)-V(vcob))
615.00 m1 40.0000 -6.9275
Transient
Curve Info
V(vco_tune)
Transient
-30.00
610.00 Spectrum of VCO output

-50.00
(Clock output)
dB(V(vco)-V(vcob))
605.00 -70.00
-90.00
600.00
V(vco_tune) [mV]
-110.00
595.00
-130.00
590.00
VCO tuning voltage -150.00
0.00 10.00 20.00 30.00 40.00
Spectrum [GHz]
50.00 60.00 70.00 80.00
(locking & settling transient)

R10
data
50 R13
data_in datab
E20 E26
50
585.00
V58
V1=-0.2
V2=0.2 0
GAIN=1 GAIN=-1
0 TRF=1/data_rat/5
PW=4/data_rat/5
580.00 TONE=0
0.00 100.00 200.00 300.00 400.00 500.00 600.00 700.00 800.00
Time [ns] V34
DC=0.782
Eye & Jitter of
0
~9 cm VCO Output (=Clock Output)
Die_P Ball_P MS_P_1 MS_P_2 via_ms MS_P COAX_P
MS_N_1 MS_N_2 via_msbMS_N COAX_N
Die_N Ball_N
SL_P via_sl SL_P_1 SL_P_2 sma_sl SL_P
SL_N via_slb SL_N_1 SL_N_2 sma_slbSL_N
avdd
V27 V31
50
50
DC=0.782 DC=1.2
R16
R19
0 0
net0164vco_tune
avdd
avdd
ch_out in clk clk_o
CDR
nbias outb eq_outb inb out cdr_data_o
vco vco
agnd
agnd
vcob
avdd
0 0
avdd
V40
vcob
DC=0.6
v_irefp
v_irefn
agnd
Channel Output CT Equalizer Output
CDR Data Output

Soft-TDR Diagnoses for Known 10 Gb/s Channel
17
Vexcited
Soft_TDR
-Vexcited
For positive differential signal

Vdet ected (t ) = Vinc + Vreflect (t )........................( 1)
Z0
where Vinc = Vexcited
50 + Z 0
Vreflect (t ) Z L + (t ) − Z 0 V (t ) − Vinc Z L + (t ) − Z 0
Q = Γ(tested ) (t ) = ⎯⎯ ⎯⎯→ det ected
from (1)
=
Vinc Z L + (t ) + Z 0 Vinc Z L + (t ) + Z 0
Vdet ected + (t ) 2 Z L (t ) Vdet ected + (t )
⇒ = ⇒ Z L (t ) = Z0
Vinc Z L (t ) + Z 0 2Vinc − Vdet ected + (t ) Z L _ diff (t ) = Z L + (t ) + Z L − (t )
Vexcited
if Z 0 = 50Ω, then Vinc =
2
Vdet ected + (t )
∴ Z L + (t ) = ⋅ 50
Vexcited − Vdet ected + (t )
Vexcited is user definable when doing the SPICE simulation
Vdet ected (t ) is node voltage at the input, which is calculated form Nexxim.
For negative differential signal
Vdet ected - (t )
Z L − (t ) = ⋅ 50
− Vexcited − Vdet ected - (t )

Diagnoses for Known 10 Gb/s Channel
18
Ansoft Corporation XY Plot 1 FlipChip

0.00
Die_P Ball_P
R2 R7
detp pgkin_p
R3 K
detn pgkin_nDie_N Ball_N R8 -10.00
50 Z=50ohm K 40
50 P=10cm 40 0
Z=50ohm
0 -20.00
P=10cm
V9 V18
Y1
-30.00
Curve Inf o
dB(St(Die_P,Die_P))
Setup1 : Sw eep1
0 0 -40.00 dB(St(Die_P,Ball_P))
Setup1 : Sw eep1
dB(St(Die_N,Die_N))
Setup1 : Sw eep1
Ansoft Corporation XY Plot 4 ReDesign dB(St(Die_N,Ball_N))
150.00 Setup1 : Sw eep1
-50.00
Curve Info
Zp
Transient -60.00
Die_P Ball_P Zn
0.00 20.00 40.00 60.00
Freq [GHz]
80.00 100.00 120.00
Transient
100.00 Z_diff
Ansoft Corporation XY Plot 4 ReDesign
Transient 150.00
Z (ohm)
Die_N Ball_N
Y1
Curve Info
50.00
100.00
Zp
Transient
Z (ohm)
MS_P_1 MS_P_2 Zn
Transient
Y1
Z_diff
Transient
MS_N_1 MS_N_2 0.00

0.00 0.20 0.40 0.60
Time [ns]
0.80 1.00 1.20
50.00
MS_P 0.00
0.00 0.20 0.40 0.60
Time [ns]
0.80 1.00 1.20
MS_N 150.00
Curve Info
Zp
Transient
Zn
Transient
Z_diff
SL_P 100.00
Transient

150.00
SL_N Curve Info
Z (ohm)
Y1
Zp
Transient
Zn
Transient 50.00
Z_diff
SL_P_1 SL_P_2 100.00

Transient
SL_N_1 SL_N_2
Z (ohm)
Y1
0.00
0.00 0.20 0.40 0.60 0.80 1.00 1.20
Time [ns]
50.00
150.00
Curve Info
COAX_P Zp
Transient
COAX_N 0.00
Zn
Transient
0.00 0.20 0.40 0.60 0.80 1.00 1.20 Z_diff

Time [ns] 100.00 Transient
Z (ohm)
SL_P
Y1
SL_N 50.00
0.00
© 2008 Ansoft, LLC All rights reserved. 0.00 0.20 0.40 0.60
Time [ns]
0.80 1.00 1.20
Ansoft, LLC Proprietary
19
Re-Design BGA Package for 40 Gb/s Channel
Die_P Ball_P
R2 R7
detp pgkin_p
R3 K
detn pgkin_n Die_N Ball_N R8
50 Z=50ohm K 40
50 40 0
P=10cm Z=50ohm
P=10cm 0
V9 V18
Ansoft Corporation XY Plot 1 FlipChip

0.00
0 0

150.00
-10.00
Curve Info
Zp
Transient
-20.00
Zn
Transient
Z_diff
100.00 Transient
-30.00
Y1
Z (ohm)
Curve Info
-40.00
dB(St(Die_P,Die_P))
Setup1 : Sw eep1
dB(St(Die_P,Ball_P))
Setup1 : Sw eep1
50.00 -50.00 dB(St(Die_N,Die_N))
Setup1 : Sw eep1
dB(St(Die_N,Ball_N))
Setup1 : Sw eep1
-60.00
0.00 -70.00
0.00 0.20 0.40 0.60 0.80 1.00 1.20 0.00 20.00 40.00 60.00 80.00 100.00 120.00
Time [ns] Freq [GHz]

20
Work with 40 Gb/s DWu Channel Ansoft Corporation XY Plot 8 Top_dwuCh
Ansoft Corporation XY Plot 7 Top_dwuCh
615.00 Curve Info Curve Info
m1
V(vco_tune) Name X Y dB(V(vco)-V(vcob))
-10.00
Transient
Transient m1 40.0000 -6.8965
610.00
-30.00
Spectrum of VCO output

(Clock output)
-50.00
605.00
dB(V(vco)-V(vcob))
-70.00
600.00
V(vco_tune) [mV]
-90.00
595.00
-110.00
590.00
VCO tuning voltage
Eye & Jitter of
-130.00
585.00
(locking & settling transient) -150.00
0.00 10.00 20.00 30.00 40.00 50.00 60.00 70.00 80.00
VCO Output (=Clock Output)
Spectrum [GHz]
R10
50 R13
data_in
E20 E26
50
580.00
0.00 50.00 100.00 150.00 200.00 250.00 300.00 350.00 400.00 450.00 500.00 V58
Time [ns]
V1=-0.2
V2=0.2 0
GAIN=1 GAIN=-1
0 TRF=1/data_rat/5
PW=4/data_rat/5
TONE=0
V34
DC=0.782
U6
PCBtrl
Die_P Ball_P ln1 ln1_t Ball_P Die_P

ln2 ln2_t
Die_N Ball_N Ball_N Die_N
~0.681cm ~9cm ~0.681cm
avdd
V27 V31
50
50
DC=0.782 DC=1.2
R16
R19
0 0
net0164 vco_tune
avdd
avdd
in clk clk_o
nbias outb eq_outb inb CDR out cdr_data_o
agnd
vco vco
CT Equalizer Output
agnd
vcob
avdd
0 0
avdd
V40
vcob
DC=0.6
v_irefp
0
v_irefn
agnd
Channel Output
CDR Data Output

21
QuickEye and VerifEye

for
Equalizer and CDR

22
QuickEye & VerifEye for CDR avdd
“15 cm PCB FR4 channel” + Equalizer + CDR V27 V31
50
50
DC=0.782 DC=1.2
R16
R19
0 0
U5 net0164 vco_tune
avdd
avdd
switch1
R10
1
in1 data ch_out in clk clk_o
V101 50
out R13 inb out in clkb
data_in datab ch_outb eq_out clk_ob
V1=-0.2 2
in2 E20 E26 nbias outb inb CDR out
V2=0.2 eq_outb cdr_data_o
50
0 TRF=1/data_rat/5 0 W65 0 vtune outb cdr_data_ob
PW=4/data_rat/5 vco
ctrlp
ctrln
vco
TONE=0
agnd
agnd
vcob
avdd
V116
0 0 0
GAIN=1 GAIN=-1
avdd
V40
sig1_in sig1_out vcob
DC=0.6
sig2_in sig2_out v_irefp
V100
Input_ref Output_ref 0
V34
DC=0.782
0 v_irefn
0
Ansoft Corporation XY Plot 12 Top_15cmTRL_ImpRes
agnd
Ansoft Corporation XY Plot 2 PWL_EqEye_15cm
Curve Info
200.00 0.25
V(eq_out)-V(eq_outb)
Transient
0.25 0
150.00
Curve Info
Name X Y 0.20
m1 175.8193888496 -194.0969213901
V(ch_out)-V(ch_outb)
Transient
100.00
Curve Info
0.20
V(out)-V (outb)
Transient
50.00 0.15
0.15
V(out)-V(outb) [mV]
0.00
0.10
-50.00 0.10
-100.00 0.05
V(eq_out)-V(eq_outb) [V]
0.05
V(ch_out)-V(ch_outb) [V]
-150.00
0.00
m1
-200.00 0.00
174.00 175.00 176.00 177.00 178.00
Time [ns ]
-0.05
-0.05
out -0.10
-0.10
Name=chout_EqEye
-0.15
10k
10k
V126
R1531
-0.15
R127
-0.20
-0.20
outb
-0.25
1.720E-007 1.740E-007 1.760E-007 1.780E-007 1.800E-007
-0.25 Time [s]
1.720E-007 1.740E-007 1.760E-007 1.780E-007 1.800E-007
Time [s]

Name=eqout_EqEye
Step Response
0.25
10k
Curve Info
V1552
R1553
V(cdr_data_o)-V(cdr_data_ob)
Transient
0.20
0.15 • Useless before Locking !

0.10
• Random data needed for settling
Name=cdrout_EqEye
• “0000..11111…” data input

V(cdr_data_o)-V(cdr_data_ob) [V]
0.05
10k
V1559
R1560
0.00
-0.05
shouldn’t break the loop.
-0.10
-0.15
-0.20
-0.25
1.720E-007 1.740E-007 1.760E-007 1.780E-007 1.800E-007
Time [s]

23
QuickEye & VerifEye for CDR
“15 cm PCB FR4 channel” + Equalizer + CDR
Transient Ansoft Corporation
300.00
Rectangular Contour Plot 1 PWL_EqEye_15cm
AEYEPROBE(c
200.00 1.0000e+000
2.9764e-003
6.1585e-005
1.2743e-006
2.6367e-008
5.4556e-010
1.1288e-011
2.3357e-013
100.00 4.8329e-015
1.0000e-016
__Amplitude [mV]
0.00
-100.00
-200.00
-300.00
-0.20 0.00 0.20 0.40 0.60 0.80 1.00 1.20
__UnitInterval
Ansoft Corporation Rectangular Contour Plot 2 PWL_EqEye_15cm

AEYEPROBE(e
250.00 1.0000e+000
2.9764e-003
6.1585e-005
1.2743e-006
2.6367e-008
5.4556e-010
QuickEye
1.1288e-011
2.3357e-013
4.8329e-015
VerifEye
1.0000e-016
125.00
__Amplitude [mV]
0.00
-125.00
-250.00
-0.20 0.00 0.20 0.40 0.60 0.80 1.00 1.20
__UnitInterval
Ansoft Corporation Rectangular Contour Plot 3 PWL_EqEye_15cm

250.00
AEYEPROBE(c
1.0000e+000
2.9764e-003
6.1585e-005
1.2743e-006
2.6367e-008
5.4556e-010
125.00 1.1288e-011
2.3357e-013
4.8329e-015
1.0000e-016
__Amplitude [mV]
0.00
-125.00
-250.00
-0.20 0.00 0.20 0.40 0.60 0.80 1.00 1.20
__UnitInterval
• Check resembles between QE and Transient

© 2008 Ansoft, LLC All rights reserved. • Match the over-design principle for Gigabit SerDes IC Ansoft, LLC Proprietary
Conclusion
24
• 40 GB/s Pre-emphasized Serializer, Continuous-

Time Equalizer, and CDR circuit had been
designed with 65nm bulk CMOS and been tested
with various electrical channel.
• An practical electrical channel has been designed

and proposed for 40 Gb/s data transmission.
• A concept Quasi-LTI is proposed for locked CDR.
• A procedure of having QuickEye and VerifEye

handle Quasi-LTI circuit/system has been proposed
to get eye-diagram (or BER bathtub) in timely
fashion.
25
Reference
1. “Signal Processing Challenges Towards 100G Optical Links”, Andrew C. Singer,
University of Illnois at Urban Champaign & Finisar Corp., SE07_04, ISSCC 2008
2. “A T-Coil Enhanced 8.5 Gb/s High-Swing Source-Series-Terminated Transmitter in
65nm Bulk CMOS”, M. Kossel, C.Menolfi, J. Weiss, P. Buchmann, G. von Bueren, L.
Rodoni, T. Morf, T. Toifl, M. Schmatz, IBM Zurich Research Laboratory, Ruschlikon,
Switzerland, Session 5.7, ISSCC 2008
3. “A 40 Gb/s CMOS Serial-Link Receiver with Adaptive Equalization and CDR”, Chih-Fan
Liao, Shen-Iuan Liu, National Taiwan University, Taipei, Taiwan, Session 5.2, ISSCC
20008
4. “Single_ended and Differential TDR Measurement with the aid of Ansoft’s
Full_Wave_SPICE” ZhaoYin Daniel Wu, Shou-Fang Chen, AltraBroadband Inc., Irvine,
Ansoft HF User Workshop, 01/06/02
5. “10-gigabit Channel Virtual Design Kit”, Suresh Subramaniam, Xilinx Inc.; Lisa Murphy,
Ansoft Corporation, 2005 DesignCon, 01/31/05
Thank You!

40 Gbs Emphasis, CDR, and Equalizer CMOS Circuit Design

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40 Gbs Emphasis, CDR, and Equalizer CMOS Circuit Design

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1

40 Gb/s Pre-emphasized Serializer,

ZY Daniel Wu, Ansoft, LLC

© 2008 Ansoft, LLC All rights reserved. Ansoft, LLC Proprietary

Data1 VSS OUTm T1331 T x _ Da ta _ n ref Rx _ Da t a _ n In Re f Ou t Re f Rx _ Da ta _ n ref T x _ Da ta _ n M

Data2 VSS OUTm T1371 T x _ Da ta _ n ref Rx _ Da t a _ n In Re f Ou t Re f Rx _ Da ta _ n ref T x _ Da ta _ n M

• This work shows how true transistor-level SerDes circuit can

• The benefit of this work is now SerDes IC designer can

Die_P Ball_P ln1 ln1_t Ball_P Die_P

~0.681cm ~9cm ~0.681cm

• Based on the assessment of 65nm bulk CMOS, the wave of avdd

single-chip 40 Gb/s will be coming soon. (Think of 32nm

© 2008 Ansoft, LLC All rights reserved. Ansoft, LLC Proprietary

• Introduction & System Overview

© 2008 Ansoft, LLC All rights reserved. Ansoft, LLC Proprietary

© 2008 Ansoft, LLC All rights reserved. Ansoft, LLC Proprietary

Introduction & System Overview

• Electrical lanes: ribbon cable, backplane

© 2008 Ansoft, LLC All rights reserved. Ansoft, LLC Proprietary

Introduction & System Overview

D1 40 Gbps PCB Channel

© 2008 Ansoft, LLC All rights reserved. Ansoft, LLC Proprietary

© 2008 Ansoft, LLC All rights reserved. Ansoft, LLC Proprietary

Circuit Design_Pre-emphasized Serializer

Circuit Design_Pre-emphasized Serializer

© 2008 Ansoft, LLC All rights reserved. Ansoft, LLC Proprietary

Simulation Results (TRL Length = 15 cm)

© 2008 Ansoft, LLC All rights reserved. Ansoft, LLC Proprietary

Circuit Design_Equalizer + CDR

Reference paper: ISSCC 2008, 5.2, pp 100~ 101

© 2008 Ansoft, LLC All rights reserved. Ansoft, LLC Proprietary

Equalizer Design Equation:

-70.00 DiffPair Response

Simulation Results (TRL Length = 15 cm, FR4 Board)

Curve Info m1 Curve Info

(locking & settling transient)

Channel Output CT Equalizer Output CDR Data Output

© 2008 Ansoft, LLC All rights reserved. Ansoft, LLC Proprietary

Ansoft Corporation XY Plot 1 CoupledTrlFreqRespond

In-direct Causality Enforcement

© 2008 Ansoft, LLC All rights reserved. Ansoft, LLC Proprietary

Ansoft Corporation XY Plot 8 Top_XilinxCh

610.00 Spectrum of VCO output

(locking & settling transient)

Channel Output CT Equalizer Output

CDR Data Output

For positive differential signal

© 2008 Ansoft, LLC All rights reserved. Ansoft, LLC Proprietary

Ansoft Corporation XY Plot 1 FlipChip

MS_N_1 MS_N_2 0.00

Ansoft Corporation XY Plot 4 ReDesign

Ansoft Corporation XY Plot 4 ReDesign

SL_N Curve Info

SL_P_1 SL_P_2 100.00

0.00 0.20 0.40 0.60 0.80 1.00 1.20 Z_diff

Ansoft Corporation XY Plot 1 FlipChip

Ansoft Corporation XY Plot 4 ReDesign

© 2008 Ansoft, LLC All rights reserved. Ansoft, LLC Proprietary

Spectrum of VCO output

Die_P Ball_P ln1 ln1_t Ball_P Die_P

~0.681cm ~9cm ~0.681cm

CDR Data Output